√3 + √7=1.7320508075688772935274463415059 + 2.6457513110645905905016157536393
=4.3778021186334678840290620951451
√10=3.1622776601683793319988935444327
So, √3 + √7 > √10 is true.

A given connected graph is a Euler Graph if and only if all vertices of are of even degree.
Proof:
→ Let G(V, E) be an Euler graph. Thus G contains an Euler line Z, which is a closed walk.
→ Let this walk start and end at the vertex u ∈ V. Since each visit of Z to an intermediate vertex v of Z contributes two to the degree of v and since Z traverses each edge exactly once, d(v) is even for every such vertex.
→ Each intermediate visit to u contributes two to the degree of u, and also the initial and final edges of Z contribute one each to the degree of u. So the degree d(u) of u is also even.

The set of vertices has size n, the number of such subsets is given by the binomial coefficient C(n,2)⋅C(n,2)=n(n-1)/2.

A + AB’+ AB’C = A(1+B’+B’C) = A
No GATE is required to implement the function A.

If the switches are in parallel then use “+”, and if they are serial then use “ ”.
A(B+C) + AB + (A+B)C = AB + AC + AB + AC + BC
= (AB+AB) + (AC+AC) + BC
= AB + AC + BC

The function table for the Half Subtractor is as follows
A-B= D= A’B + AB’
X= A’B

W’ + W’Z + Z’XY = W’(1+Z) + Z’XY
= W’ + Z’XY
The term W’Z is redundant which is represented by GATE 2.

→ A dynamic hazard is the possibility of an output changing more than once as a result of a single input change.
→ Dynamic hazards often occur in larger logic circuits where there are different routes to the output (from the input).
→ If each route has a different delay, then it quickly becomes clear that there is the potential for changing output values that differ from the required / expected output. e.g.
→ A logic circuit is meant to change output state from 1 to 0, but instead changes from 1 to 0 then 1 and finally rests at the correct value 0. This is a dynamic hazard.
→ As a rule, dynamic hazards are more complex to resolve, but note that if all static hazards have been eliminated from a circuit, then dynamic hazards cannot occur.

X1= Y1
X2= Y1⊕ Y2
X3= Y2 ⊕ Y3

The square wave has alternating amplitudes(0 and 1) with duty cycle 1.
An odd number of cascaded NOT gates produce a square wave.

Note: Duty cycle= Ratio of durations in which the circuit is ON and OFF in a cycle.

Given, (12A7C)₁₆ = (0001 0010 1010 0111 1100)₂
MAke blocks of 3 bits each from LSB to MSB.
(Note: In the last block append zeros (as MSBs) if number bits is not three)
(000 010 010 101 001 111 100)
Each of the above blocks represents a digit in base 8 and they can be converted to base 8 as shown below.
= (0 2 2 5 1 7 4)₈

Excess-3 code is also called Self-Complementing Code. Because 1’s complement of an excess-3 number is equivalent to 9’s complement of the corresponding decimal digit.
→ In excess-3 code, each of the 4-bit numbers represents decimal digit which is 3 less than the actual decimal digit. So the bits have no fixed weight.
Excess-3 code is neither CRC nor Algebraic Code which is used for error detection and/or correction.

Hint: Number of bits=4
(Decimal value of maximum 4-bit number +1 )/2= (15+1)/2=8

-> JK flip flop accepts input J=K=1. When J=K=1, the state of the flip-flop gets complimented. But it's not a valid input in SR flip-flop.
-> JK flip flop doesn’t have a feedback path.

→ Given that the processor clock rate = 2.5 GHz, the processor takes 2.5 G cycles in one second.
→ Time taken to complete one cycle = (1 / 2.5 G) seconds
→ Since it is given that average number of cycles per instruction = 4, the time taken for completing one instruction=(4/2.5 G) = 1.6 ns
→ In the pipelined case we know in the ideal case CPI = 1, and the clock speed = 2 GHz.
→ Time taken for one instruction in the pipelined case = (1 / 2 G) = 0.5 ns
→ Speedup = 1.6/0.5 = 3.2

If we are given p instead of *p then it prints the address of k but we are printing the value of k.
The same rule applies in **m.
Output is 5 5 5

→ Given that the disk pack has 16 surfaces, 128 tracks per surface, 256 sectors per track and each sector size is 512 bytes.
→ So the disk pack capacity = 16*128*256*512 bytes = 256 MB
→ To specify a sector we need the information about surface number, track number and sector number within a track.
→ Surface number needs 4 bits as there are 16 surfaces(2⁴), track number needs 7 bits as there are 128 tracks(2⁷) within a surface, within a track the sector number needs 8 bits as there are 256 sectors (2⁸).
→ Total number bits needed to specify a particular sector = 4+7+8 = 19 bits.

→ Register renaming is used to eliminate hazards that arise due to WAR (Write After Read) and WAW(Write After Write) dependencies.

→ SISD (single instruction stream, single data stream) is a computer architecture in which a single uni-core processor, executes a single instruction stream, to operate on data stored in a single memory. This corresponds to the von Neumann architecture.
→ SISD is one of the four main classifications as defined in Flynn's taxonomy.
→ In this system, classifications are based upon the number of concurrent instructions and data streams present in the computer architecture. According to Michael J. Flynn, SISD can have concurrent processing characteristics.
→ Pipelined processors and superscalar processors are common examples found in most modern SISD computers.
→ Instructions are sent to the control unit from the Memory Module and are decoded and sent to the processing unit which processes on the data retrieved from Memory module and sent back to it.

Ptr = (char*) &a ; /* It is type casted to char* */
Printf (“%d”, *ptr) ; /* Here *ptr is referring a single character */
Printf (“%d”, *ptr) ;
Output: 64 /* @ ASCII value is 64 */
Note: Assume short a is 2 byte integer.

Explanation:
Let us consider n=6, then
1<=6 (correct)
2<=6 (correct)
4<=6 (correct)
8<=6 (False)
4 comparisons required
Option A:
⌊log n⌋+1
⌊log 6⌋+1
3+1=4 (correct)
Option B:
n=6 (False)
Option C:
⌊log n⌋
⌊log 6⌋=3 (False)
Option D:
⌊log ₂n⌋+1
⌊log ₂6⌋+1=2+1=3 (False)

Expression: 8 2 3 ^ / 2 3 * + 5 1 * –
Rule (1): If the element is a number, Push it into stack.
Rule (2): If the element is an operator, Pop operands from the stack. Evaluate the operator operation and Push the result back into the stack.

Total comparisons required
= No. of comparisons if element present in 1^st position + No. of comparisons if element present in 2^ndnd position + ............. + No. of comparisons if element present in n^th position
= 1+2+3+ ... + n
= n(n+1)/2
Since there are n elements in the list, so average no. of comparisons
= Total comparisons/Total no. of elements
= (n(n+1)/2)/n
= n+1/2

Given data, insertion order is 37, 38, 72, 48, 98, 11, 56
Hash function = f(key) = key mod 7

→ A binary tree where each non-leaf node has exactly two children. The number of leaves is n+1. Total number of nodes is 2n+1.
Note: if two leaves having the same parent are removed from the tree, the number of leaves and non-leaves will decrease by 1 because the parent will be a leaf. That means the difference between them is constant. And for a tree having just one node that difference is 1.

Divide and conquer sorting algorithms:
1. Quick sort
2. Merge sort
3. Heap sort
****Binary search also follows the divide and conquer.

→ A FSM(finite state machine) can be considered to be a turing machine of finite tape length without rewinding capability and unidirectional tape movement.
→ The finite state machine has less computational power than some other models of computation such as the Turing machine.
→ The computational power distinction means there are computational tasks that a Turing machine can do but a FSM cannot. This is because a FSM's memory is limited by the number of states it has.
→ A finite state machine has the same computational power as a Turing machine that is restricted such that its head may only perform "read" operations, and always has to move from left to right. That is, each formal language accepted by a finite state machine is accepted by such a kind of restricted Turing machine, and vice versa.

→ The best way to find correct answer is option elimination method.
→ We will guess strings which has even number of 1’s and that is not generated by wrong options OR which generate strings which doesn’t have even number of 1’s.
Option A: (Regular expression: (0*10*1)* ) doesn’t generate string such as { 110, 1100,....}
Option C: (Regular expression: 0*(10*1*)*0* generate string such as {1, 111,....} which have odd number of 1’s.
Option D: (Regular expression: 0*1(10*1)*10* doesn’t generate strings such as { 11101, 1111101, ….}.

Is ambiguous, as it has two parse tree for the string “abbaba”

G doesn’t produce all strings of an equal number of a’s and b’s, for ex: string “aabb” doesn’t generate by grammar G.
The language generated by G can be accepted by DPDA. We can notice that grammar G generates, a’s and b’s in pair, i.e. either “ab” or “ba”, so the strings in language are {ab, ba, abab, abba, baba, ….}
We can design the DPDA:

→ If L is recursive enumerable, then it implies that there exist a Turing Machine (lets say M1) which always HALT for the strings which is in L.
→ If L’ are recursively enumerable, then it implies that there exist a Turing Machine (lets say M2) which always HALT for the strings which is NOT in L(as L is complement of L’ Since we can combine both Turing machines (M1 and M2) and obtain a new Turing Machine (say M3) which always HALT for the strings if it is in L and also if it is not in L.
→ This implies that L must be recursive.

From the grammar, we can easily infer that it generates all the palindromes of odd length, for ex: strings {aba, bab, aaa, bbb, ….}

Grammar is belongs to Type 0 ,Type 1,Type 2,Type 3 because it is regular. Option D is right answer because they are asking only highest type number.

Access time of the symbolic table will be logarithmic if it is implemented by search time.

→ A recursive descent parser is a kind of top-down parser built from a set of mutually recursive procedures (or a non-recursive equivalent) where each such procedure implements one of the nonterminals of the grammar.
→ Thus the structure of the resulting program closely mirrors that of the grammar it recognizes.

→ Top-down parsing can be viewed as an attempt to find leftmost derivations of an input-stream by searching for parse-trees using a top-down expansion of the given formal grammar rules.
→ The inclusive choice is used to accommodate ambiguity by expanding all alternative right-hand-sides of grammar rules.

The main advantage of PC- relative addressing is that code may be position independent, i.e., it can be loaded anywhere in memory without the need to adjust any address.

Only Single resource available never occur deadlock because it violates circular wait and hold & wait condition.

→ Peephole optimization technique works locally on the source code to transform it into an optimized code.
→ By locally, we mean a small portion of the code block at hand.
→ These methods can be applied on intermediate codes as well as on target codes.

Here, 20P operations means 20 wait operations. It decrement value by 1 every time.
xV operations means x increments operations. It increment value by 1 every time.
→ New value of semaphore is 5 after performing xV operations
= -13 + xV
= 5
xV = 5 + 13
= 18
→ After applying 20P operations in semaphore value is = 7-20 = -13

If the system is deadlocked, it implies that each process is holding one resource and is waiting for one more. Since there are 3 processes and 4 resources, one process must be able to obtain two resources. This process requires no more resources and therefore it will return its resources when done.

Here, total 6 page faults but in question, they are clearly mentioned that the main memory already has the pages 1 and 2, with page one having brought earlier than page 2. It means 6-2=4.

→ Working set defines the amount of memory that a process requires in a given time interval.
→ It defines “the working set of information W(t,τ) of a process at time t to be the collection of information referenced by the process during the process time interval (t−τ,t)”.
→ Typically the units of information in question are considered to be memory pages. This is suggested to be an approximation of the set of pages that the process will access in the future (say during the next τ time units), and more specifically is suggested to be an indication of what pages ought to be kept in main memory to allow most progress to be made in the execution of that process.

Page size = 4 KB = 4 × 210 Bytes = 212 Bytes
Virtual Address = 32 bit
No. of bits needed to address the page frame = 32 - 12 = 20
TLB can hold 128 page table entries with 4-way set associative
⇒ 128/4=32=25
→ 5 bits are needed to address a set.
→ The size of TLB tag = 20 - 5 = 15 bits

→ Preemption is the act of temporarily interrupting a task being carried out by a computer system, without requiring its cooperation, and with the intention of resuming the task at a later time. Such changes of the executed task are known as context switches.
→ It is normally carried out by a privileged task or part of the system known as a preemptive scheduler, which has the power to preempt, or interrupt, and later resume, other tasks in the system.
→ Preemptive scheduling is the most suitable scheduling scheme for real time operating systems as it can always preempt other processes based on priority.
→ In real time operating systems, we have different tasks to perform simultaneously and also there are a few tasks which need to be performed first at priority basis.

→ Belady's anomaly is the phenomenon in which increasing the number of page frames results in an increase in the number of page faults for certain memory access patterns.
→ This phenomenon is commonly experienced when using the first-in first-out (FIFO) page replacement algorithm.
→ In FIFO, the page fault may or may not increase as the page frames increase, but in Optimal and stack-based algorithms like LRU, as the page frames increase the page fault decreases.

For maximum:
If there is common attribute in R and S, and every row of R match with every row of S then total no. of tuples will be mn.
For minimum:
If there is no common attribute between R and S or if there is common attribute but none of the row of R matches with rows of S then output tuples will be 0.

→ Which results titles of the five most expensive books.
→ The where clause of outer query will be true for 5 most expensive books.

Logical Schema includes
1. Avoiding data inconsistency
2. Able to construct query easily
3. Able to access data efficiently

The sum of all employee salaries can’t be represented by using the given six basic algebra operation. If we want to represent sum of salaries then we need to use aggregation operator.

→ A database trigger is procedural code that is automatically executed in response to certain events on a particular table or view in a database.
→ The trigger is mostly used for maintaining the integrity of the information on the database.
→ For example, when a new record (representing a new worker) is added to the employees table, new records should also be created in the tables of the taxes, vacations and salaries.
→Triggers can also be used to log historical data, for example to keep track of employees' previous salaries.

Disk Block size = 1 KBytes = 2¹⁰ Bytes = 1024 Bytes
Data recorder pointer size, r = 7 bytes
Value size, v = 9 bytes
Disk Block pointer, P = 6 bytes
⇒ Order of leaf be m, then
r*m+v*m+p <= 1024
7m+9m+6 <= 1024
16m <= 1024 - 6
m <= 63

Single level index
1. Primary index(Sparse): Ordered with key field
2. Clustered index(Sparse): Ordered with non key field
3. Secondary index(dense): Ordered with either key or non key field.

→ The extent to which the s/w can continue to operate correctly despite the introduction of invalid inputs is called as robustness
→ Robustness is the ability of a computer system to cope with errors during execution and cope with erroneous input

Functional Requirements include:
1. Descriptions of data to be entered into the system
2. Descriptions of operations performed by each screen
3. Descriptions of work-flows performed by the system
4. Descriptions of system reports or other outputs

→ The Functional Requirements Specification is designed to be read by a general audience. Readers should understand the system, but no particular technical knowledge should be required to understand the document.

Examples:
1. Interface requirements
2. Business requirements
3. Regulatory/Compliance requirements
4. Security requirements

Configuration management is not concerned with choice of hardware configuration for an application.

LOC L1 = X
L2 = 2X
Total cost of project: x/1000*1000000+5+100000
=2x/10000*750000+50000*5
=100×+500000
=150×+250000
⟹50×=500000-250000

Constructive Cost Model (COCOMO) formula for effort applied is
Effort Applied (E) = a_b(KLOC)^b_b [ person-months ]
= 2.2 x(20)_1.50
= 2.2 x 89.44
= 196.77

→ In the Spiral model of software development, the primary determinant in selecting activities in each iteration is risk handling
→ The spiral model is a risk-driven software development process model. Based on the unique risk patterns of a given project, the spiral model guides a team to adopt elements of one or more process models, such as incremental, waterfall, or evolutionary prototyping.

→ Bit stuffing is most easily described as insertion of a 0 bit after a long run of 1 bits.
→ In SDLC the transmitted bit sequence "01111110" containing six adjacent 1 bits is the Flag byte.
→ Bit stuffing ensures that this pattern can never occur in normal data, so it can be used as a marker for the beginning and end of frame without any possibility of being confused with normal data.

Dynamic Routing
→ The administrator configure a routing protocol on your network interfaces.
→ Routing protocol learns about other routers automatically.
→ Router and the other routers exchange routes, and each learns about the networks that the other is connected to.
→ When new networks are added or removed, the routers update each other.

→ In CSMA/CD once a collision is detected, the colliding devices send a jam signal.
→ Assuming you know the collision detection method used by CSMA/CD, the jam signals generated after collision informs the devices that a collision has occurred and invokes a random backoff algorithm which forces the devices on the Ethernet not to send any data until their timer expires. (everyone has a random timer value)
→ Once a transmitting device detects collision which is by examining the data over the Ethernet and identifying that it's not the data it has send, it does receive the jamming signal otherwise collision will keep happening.
→ As the jam signal is generated after collision hence the devices ideally won’t be sending any data during that time.

→ A router(or) a residential gateway can be enabled to act as a DHCP server.
→ Most residential network routers receive a globally unique IP address within the ISP network.
→ Within a local network, a DHCP server assigns a local IP address to each device connected to the network.

T_t = L / B => 1/ 10⁷ = 0.1 microsec
Given T_p = 200 m / microsec
In, 1 microsec it covers 200m
Therefore, in 0.1 microsec it is 200 * 0.1 = 20 meters

→ It is a class B address, so there 16-bits for NID and 16-bits for HID.
→ From HID, we took 6-bits for subnetting.
→ Then total subnets possible = ( 2⁶ ) - 2 = 62
→ Total hosts possible for each subnet = (2¹⁰) - 2 = 1022

CRC polynomial = x3+1 [∵ In data 3-zero’s need to be append to data]
= 1001

∴ Data transmitted is: 11001001011

Application Layer - Any size
Transport Layer - 65515 byte
Network layer - 65535 byte
Data link layer - 1500 byte

→ Transmission time (Tt)=1000/10⁶ seconds = 1 ms
→ Maximum number of frames that can be transmit to maximally pack them is
=(T_t+2T_p)/T_x
= (25+1)/1
=26 which is window size
→ Minimum sequence numbers required = 26
→ Minimum number of bits required for sequence number is 5.

→ User-defined tags are only allowed in XML but not in HTML. All the other options are correct for both XML and HTML.
→ SGML stands for Standard Generalized Markup Language and it was extended to HTML and XML.
→ Both XML and HTML are used to describe the content and layout of a webpage and are used with web browsers only.

Average access time = [H₁ * T₁] + [(1 - H₁) * H_m * T_m]
H₁ = 0.8, (1 - H₁) = 0.2
H₂ = 0.9, (1 - H₂) = 0.1
T₁ = Access time for level 1 cache = 1ns
T₂ = Access time for level 2 cache = 10ns
H_m = Hit rate of main memory = 1
T_m = Access time for main memory = 500ns
Average access time = [(0.8 * 1) + (0.2 * 0.9 * 10) + (0.2)(0.1) * 1 * 500]
= 0.8 + 1.8 + 10
= 12.6ns

→ It is nothing but multilevel inheritance.
→ If a class C is derived from class B, which is derived from class A, all through public inheritance, then a class C member function can access public and protected data of A and B and all data of C

Both statements are wrong. I. Logical errors can’t solve in compile time. Like dividing by error.
II. In c++ also we have to write exceptions.

→ DNS spoofing, also referred to as DNS cache poisoning, is a form of computer security hacking in which corrupt Domain Name System data is introduced into the DNS resolves cache, causing the name server to return an incorrect result record, e.g. an IP address.
→ This results in traffic being diverted to the attacker's computer (or any other computer).

2-pass Assembler can perform all of above operations.