Question 8037 – GATE 2016 [Set-1]
January 12, 2024Question 8101 – GATE 2016 [Set-2]
January 12, 2024Pipelining
| Question 9 |
A 5 stage pipelined CPU has the following sequence of stages:
IF — Instruction fetch from instruction memory. RD — Instruction decode and register read. EX — Execute: ALU operation for data and address computation. MA — Data memory access - for write access, the register read at RD stage is used. WB — Register write back.
Consider the following sequence of instructions:
I1 : L R0, 1oc1; R0 <= M[1oc1] I2 : A R0, R0 1; R0 <= R0 + R0 I3 : S R2, R0 1; R2 <= R2 - R0 Let each stage take one clock cycle.
What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of I1?
| 8 | |
| 10 | |
| 12 | |
| 15 |
Question 9 Explanation:
From memory stage we are using operator forwarding:
If we don’t use operator forwarding:
Total clock cycles = 8/11
There is no ’11’ in option.
Then no. of cycles = 8
Correct Answer: A
Question 9 Explanation:
From memory stage we are using operator forwarding:
If we don’t use operator forwarding:
Total clock cycles = 8/11
There is no ’11’ in option.
Then no. of cycles = 8