GATE 2017 [Set-1]

Question 25

Consider a two-level cache hierarchy with L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache is 0.1; the L2 cache experiences, on average, 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is __________.

A	0.05
B	0.06
C	0.07
D	0.08

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Question 25 Explanation:

It is given that average references per instruction = 1.4
For 1000 instructions total number of memory references = 1000 * 1.4 = 1400

These 1400 memory references are first accessed in the L1.
Since the miss rate of L1 is 0.1, for 1400 L1 references the number of misses = 0.1 * 1400 = 140

We know when there is a miss in L1 we next access the L2 cache.

So number of memory references to L2 = 140

It is given that there are 7 misses in L2 cache. Out of 140 memory references to L2 cache there are 7 misses.

Hence the miss rate in L2 cache = 7/140 = 0.05

Correct Answer: A