Theory-of-Computation

November 11, 2023

NTA UGC NET JUNE-2023 Paper-2

November 11, 2023

Theory-of-Computation

November 11, 2023

NTA UGC NET JUNE-2023 Paper-2

November 11, 2023

UGC NET CS 2015 Dec – paper-3

Question 5
A DMA controller transfers 32-bit words to memory using cycle stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer?
A
0.6%
B
0.12%
C
1.2%
D
2.5%
Question 5 Explanation: 
→ In one second, device is sending – 4800 characters to DMA
→ 1 character = 8 bits
→ So in one second, device is sending – (4800⨯8) bits to DMA
→ In one cycle, DMA sends – 32 bits.
→ To send (4800 ⨯ 8) bits DMA needs = (4800⨯8)/30 cycles = 1200 cycles
→ Now in one second CPU executes 106 instructions.
→ But because of cycle stealing, CPU has slow down and the % by which CPU gets slow down can be calculated as
= 1200/106 * 100
= 12/10000 * 100
=0.12%
Correct Answer: B
Question 5 Explanation: 
→ In one second, device is sending – 4800 characters to DMA
→ 1 character = 8 bits
→ So in one second, device is sending – (4800⨯8) bits to DMA
→ In one cycle, DMA sends – 32 bits.
→ To send (4800 ⨯ 8) bits DMA needs = (4800⨯8)/30 cycles = 1200 cycles
→ Now in one second CPU executes 106 instructions.
→ But because of cycle stealing, CPU has slow down and the % by which CPU gets slow down can be calculated as
= 1200/106 * 100
= 12/10000 * 100
=0.12%

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