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November 18, 2023Artificial-Intelligence
November 18, 2023Computer-Organization
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Question 1
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A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds. The registers that are used between the pipeline stages have a delay of 5 nanoseconds each.
The total time to execute 100 independent instructions on this pipeline, assuming there are no pipeline stalls, is ______ nanoseconds.
The total time to execute 100 independent instructions on this pipeline, assuming there are no pipeline stalls, is ______ nanoseconds.
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17160
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Question 1 Explanation:
In a pipeline with k-stages, number of cycles to execute n instructions = (k+n-1) cycles
Here k = 5, n = 100
So we need a total of 5+100-1 = 104 cycles.
Clock cycle time = maximum of all stage delays + register delay
= max(150, 120, 150, 160, 140) + 5 = 160+5 = 165 ns
Time in ns = 104*165 = 17160ns
Correct Answer: A
Question 1 Explanation:
In a pipeline with k-stages, number of cycles to execute n instructions = (k+n-1) cycles
Here k = 5, n = 100
So we need a total of 5+100-1 = 104 cycles.
Clock cycle time = maximum of all stage delays + register delay
= max(150, 120, 150, 160, 140) + 5 = 160+5 = 165 ns
Time in ns = 104*165 = 17160ns