Question 8134 – Computer-Organization
May 29, 2024Question 6735 – UGC NET CS 2016 July- paper-3
May 29, 2024Question 8069 – Computer-Organization
The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. The throughput increase of the pipeline is ________ percent.
Correct Answer: A
Question 26 Explanation:
In a pipelined processor the throughput is 1/clock cycle time.
Cycle time = max of all stage delays.
In the first case max stage delay = 800.
So throughput = 1/800 initially.
After replacing this stage with two stages of delays 600, 350… the cycle time = maximum stage delay = 600.
So the new throughput = 1/600.
The new throughput > old throughput.
And the increase in throughput = 1/600 – 1/800.
We calculate the percentage increase in throughput w.r.t initial throughput, so the % increase in throughput
= (1/600 – 1/800) / (1/800) * 100
= ((800 / 600) – 1) * 100
= ((8/6) -1) * 100
= 33.33%
Cycle time = max of all stage delays.
In the first case max stage delay = 800.
So throughput = 1/800 initially.
After replacing this stage with two stages of delays 600, 350… the cycle time = maximum stage delay = 600.
So the new throughput = 1/600.
The new throughput > old throughput.
And the increase in throughput = 1/600 – 1/800.
We calculate the percentage increase in throughput w.r.t initial throughput, so the % increase in throughput
= (1/600 – 1/800) / (1/800) * 100
= ((800 / 600) – 1) * 100
= ((8/6) -1) * 100
= 33.33%
33.33%
33.34%
33.35%
33.36%
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