Computer-Organization
April 11, 2025UPPCL AE 2022
April 11, 2025NTA UGC NET Aug 2024 Paper-2
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Question 5
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A CPU has a 5-stage pipeline with the following stages Fetch (F), Decode (D), Execute (E), Memory (M) and Write-back (W). Each stage takes one clock cycle to complete. Assume there are no pipeline stalls and the pipeline is initially empty. How many clock cycles are required to complete the execution of 10 instructions ?
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10
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14
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15
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19
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Question 5 Explanation:
For the first instruction, it will take 5 clock cycles to complete (one cycle per stage).
For the second instruction, the first instruction has already passed the fetch stage, so the second instruction will start fetching in the second cycle, while the first instruction proceeds through the next stages. This means that from the second instruction onward, we have overlapping stages.
So, the total number of clock cycles required to complete 10 instructions will be:
5 cycles for the first instruction.
1 cycle for each of the remaining 9 instructions (since they all overlap in the pipeline after the first).
Thus, the total number of cycles required for 10 instructions is:
5+(10−1)=5+9=14 clock cycles
For the second instruction, the first instruction has already passed the fetch stage, so the second instruction will start fetching in the second cycle, while the first instruction proceeds through the next stages. This means that from the second instruction onward, we have overlapping stages.
So, the total number of clock cycles required to complete 10 instructions will be:
5 cycles for the first instruction.
1 cycle for each of the remaining 9 instructions (since they all overlap in the pipeline after the first).
Thus, the total number of cycles required for 10 instructions is:
5+(10−1)=5+9=14 clock cycles
Correct Answer: B
Question 5 Explanation:
For the first instruction, it will take 5 clock cycles to complete (one cycle per stage).
For the second instruction, the first instruction has already passed the fetch stage, so the second instruction will start fetching in the second cycle, while the first instruction proceeds through the next stages. This means that from the second instruction onward, we have overlapping stages.
So, the total number of clock cycles required to complete 10 instructions will be:
5 cycles for the first instruction.
1 cycle for each of the remaining 9 instructions (since they all overlap in the pipeline after the first).
Thus, the total number of cycles required for 10 instructions is:
5+(10−1)=5+9=14 clock cycles
For the second instruction, the first instruction has already passed the fetch stage, so the second instruction will start fetching in the second cycle, while the first instruction proceeds through the next stages. This means that from the second instruction onward, we have overlapping stages.
So, the total number of clock cycles required to complete 10 instructions will be:
5 cycles for the first instruction.
1 cycle for each of the remaining 9 instructions (since they all overlap in the pipeline after the first).
Thus, the total number of cycles required for 10 instructions is:
5+(10−1)=5+9=14 clock cycles