Memory-Management

Question 1

Assume that in a certain computer, the virtual addresses are 64 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 8 kB and the word size is 4 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 128 valid entries. At most how many distinct virtual addresses can be translated without any TLB miss?

A
8×220
B
4×220
C
16×210
D
256×210
       Operating-Systems       Memory-Management       GATE 2019       Video-Explanation
Question 1 Explanation: 
A TLB has 128 valid entries.
So, it can refer to 27 pages.
Each page size is 8 kB & word is 4 bytes.
So, the total addresses of virtual address spaces that can be addressed
Question 2

Consider six memory partitions of sizes 200 KB, 400 KB, 600 KB, 500 KB, 300 KB and 250 KB, where KB refers to kilobyte. These partitions need to be allotted to four processes of sizes 357 KB, 210KB, 468 KB and 491 KB in that order. If the best fit algorithm is used, which partitions are NOT allotted to any process?

A
200KBand 300 KB
B
200KBand 250 KB
C
250KBand 300 KB
D
300KBand 400 KB
       Engineering-Mathematics       Memory-Management       GATE 2015 [Set-2]
Question 2 Explanation: 

Since Best fit algorithm is used. So, process of size,
357KB will occupy 400KB
210KB will occupy 250KB
468KB will occupy 500KB
491KB will occupy 600KB
So, partitions 200KB and 300KB are NOT alloted to any process.
Question 3

Consider a paging hardware with a TLB. Assume that the entire page table and all the pages are in the physical memory. It takes 10 milliseconds to search the TLB and 80 milliseconds to access the physical memory. If the TLB hit ratio is 0.6, the effective memory access time (in milliseconds) is  _________.

A
122
B
123
C
124
D
125
       Operating-Systems       Memory-Management       GATE 2014 [Set-3]
Question 3 Explanation: 
Tavg = TLB access time + miss ratio of TLB × memory access time + memory access time
= 10 + 0.4 × 80 + 80
= 10 + 32 + 80
= 122 ms
Question 4

The memory access time is 1 nanosecond for a read operation with a hit in cache, 5 nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation with a hit in cache and 10 nanoseconds for a write operation with a miss in cache. Execution of a sequence of instructions involves 100 instruction fetch operations, 60 memory operand read operations and 40 memory operand write operations. The cache hit-ratio is 0.9.  The average memory access time (in nanoseconds) in executing the sequence of instructions is   __________.

A
1.68
B
1.69
C
1.70
D
1.71
       Operating-Systems       Memory-Management       GATE 2014 [Set-3]
Question 4 Explanation: 
Total instruction = 100 instruction fetch operation + 60 memory operand read operation + 40 memory operand write op
= 200 instructions (operations)
Time taken for fetching 100 instructions (equivalent to read) = 90*1ns + 10*5ns = 140ns
Memory operand Read operations = 90% (60)*1ns + 10% (60) × 5ns = 54ns + 30 ns = 84ns
Memory operands Write operations time = 90% (40)*2ns + 10% (40)*10ns
= 72ns + 40ns = 112ns
Total time taken for executing 200 instructions = 140 + 84 + 112 = 336ns
∴ Average memory access time = 336 ns/200 = 1.68ns
Question 5

A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.

What is the size of a page in KB in this computer?

A
2
B
4
C
8
D
16
       Operating-Systems       Memory-Management       GATE 2013
Question 5 Explanation: 
Let the size of page is = 2p B
So the no. of entries in one page is 2p/4, where 4 is the page table entry size given in question.
So we know that process size or virtual address space size is equal to
No. of entries × Page size
So total no. of entries for 3 level page table is,
(2p/4)×(2p/4)×(2p/4)
So, No. of entries × Page size = VAS
(2p/4)×(2p/4)×(2p/4)× (2p) = 246
24p = 252
4p = 52
p = 13
∴ Page size = 213
Question 6

A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.

What is the minimum number of page colours needed to guarantee that no two synonyms map to different sets in the processor cache of this computer?

A
2
B
4
C
8
D
16
       Operating-Systems       Memory-Management       GATE 2013
Question 6 Explanation: 
Architecture of physically indexed cache:

Architecture of virtual indexed physically tagged (VIPT):

VIPT cache and aliasing effect and synonym.
Alias: Same physical address can be mapped to multiple virtual addresses.
Synonym: Different virtual addresses mapped to same physical address (for data sharing).
So these synonyms should be in same set to avoid write-update problems.
In our problem VA = 46bits

We are using 16bits for indexing into cache.
To have two synonym is same set we need to have same 16 bits index for PA & VA.
Assume that physical pages are colored and each set should have pages of same color so that any synonyms are in same set.
Since page size = 8KB ⇒ 13bits
These 13bits are not translated during VA→PA. So 13bits are same out of 16 Index bits, 13 are same we need to make 3bits (16-13) same now.
3bits can produce, 23 = 8 combinations which can be mapped on the different sets, so we need 8 different colors to color our pages. >br> In physically indexed cache indexing is done via physical address bits, but in virtual indexed cache, cache is indexed from (offset + set) bits. In physical Index cache indexing is done one to one (1 index maps to one page in one block of cache). In VIPT we have more/ extra bits, so mapping is not one-one. Hence these extra bits have to be taken care, such that if two virtual address refers to same page in cache block of different sets then they have to be assumed same i.e., we say of same color and put same color page in one set to avoid write update problems.
Question 7

Let the page fault service time to 10 ms in a computer with average memory access time being 20 ns. If one page fault is generated for every 106 memory accesses, what is the effective access time for the memory?

A
21 ns
B
30 ns
C
23 ns
D
35 ns
       Operating-Systems       Memory-Management       GATE 2011
Question 7 Explanation: 
P = page fault rate
EA = p × page fault service time + (1 – p) × Memory access time
= 1/106×10×106+(1-1/106)×20 ≅ 29.9 ns
Question 8

In a paged segmented scheme of memory management, the segment table itself must have a page table because

A
the segment table is often too large to fit in one page
B
each segment is spread over a number of pages
C
segment tables point to page table and not to the physical locations of the segment
D
the processor’s description base register points to a page table
E
Both A and B
       Operating-Systems       Memory-Management       GATE 1995
Question 8 Explanation: 
The segment table is often too large to fit in one page. This is true and the segment table can be divided into pages. Thus page table for each segment table, pages are created.
Segment paging is different from paged segmentation.
Question 9

The capacity of a memory unit is defined by the number of words multiplied by the number of bits/word. How many separate address and data lines are needed for a memory of 4K × 16?

A
10 address, 16 data lines
B
11 address, 8 data lines
C
12 address, 16 data lines
D
12 address, 12 data lines
       Computer-Organization       Memory-Management       GATE 1995
Question 9 Explanation: 
ROM memory size = 2m × n
m = no. of address lines
n = no. of data lines
Given, 4K × 16 = 212 × 16
Address lines = 12
Data lines = 16
Question 10

A computer installation has 1000k of main memory. The jobs arrive and finish in the following sequences.

 Job 1 requiring 200k arrives
 Job 2 requiring 350k arrives
 Job 3 requiring 300k arrives
 Job 1 finishes
 Job 4 requiring 120k arrives 
 Job 5 requiring 150k arrives
 Job 6 requiring 80k arrives 

(a) Draw the memory allocation table using Best Fit and First fit algorithms.
(b) Which algorithm performs better for this sequence?

A
Theory Explanation.
       Operating-Systems       Memory-Management       GATE 1995
Question 11

Consider allocation of memory to a new process. Assume that none of the existing holes in the memory will exactly fit the process’s memory requirement. Hence, a new hole of smaller size will be created if allocation is made in any of the existing holes. Which one of the following statements is TRUE?

A
The hole created by worst fit is always larger than the hole created by first fit.
B
The hole created by best fit is never larger than the hole created by first fit.
C
The hole created by first fit is always larger than the hole created by next fit.
D
The hole created by next fit is never larger than the hole created by best fit.
       Operating-Systems       Memory-Management       GATE 2020
Question 11 Explanation: 
The size of hole created using best fit is never greater than size created by first fit. The best fit chooses the smallest available partition to fit the size of the process. Whereas, first fit and next fit doesn’t consider the size of the holes available.
Question 12

Consider a paging system that uses a 1-level page table residing in main memory and a TLB for address translation. Each main memory access takes 100 ns and TLB lookup takes 20 ns. Each page transfer to/from the disk takes 5000 ns. Assume that the TLB hit ratio is 95%, page fault rate is 10%. Assume that for 20% of the total page faults, a dirty page has to be written back to disk before the required page is read in from disk. TLB update time is negligible. The average memory access time in ns (round off to 1 decimal places) is ______.

A
154.5 ns
       Operating-Systems       Memory-Management       GATE 2020
Question 12 Explanation: 
M=100ns
T=20ns
D=5000ns
h=0.95
p=0.1, 1-p=0.9
d=0.2, 1-d=0.8
EMAT = h×(T+M)+(1-h)[(1-p)×2M+p[(1-d)[D+M]+d(2D+M)]+T]
= 0.95×(20+100)+(1-0.95)[(1-0.1)×200+(0.1)[(1-0.2)[5000+100]+(0.2)(10000+100)]+20]
= 154.5 ns
Question 13

A certain moving arm disk storage, with one head, has the following specifications.

 Number of tracks/recording surface = 200
 Disk rotation speed = 2400 rpm
 Track storage capacity = 62,500 bits 

The average latency of this device is P msec and the data transfer rate is Q bits/sec.
Write the value of P and Q.

A
P = 12.5, Q = 2.5×106
       Operating-Systems       Memory-Management       GATE 1993
Question 13 Explanation: 
RPM = 2400
So, in DOS, the disk rotates 2400 times.
Average latency is the time for half a rotation
= 0.5×60/2400 s
= 12.5 ms
In one full rotation, entire data in a track can be transferred. Track storage capacity = 62500 bits
So, disk transfer rate
= 62500 × 2400/60
= 2.5 × 106 bps
So,
P = 12.5, Q = 2.5×106
Question 14

(a) The access times of the main memory and the Cache memory, in a computer system, are 500 n sec and 50 n sec, respectively. It is estimated that 80% of the main memory request are for read the rest for write. The hit ratio for the read access only is 0.9 and a write-through policy (where both main and cache memories are updated simultaneously) is used. Determine the average time of the main memory.
(b) Three devices A, B and C are corrected to the bus of a computer, input/output transfers for all three devices use interrupt control. Three interrupt request lines INTR1, INTR2 and INTR3 are available with priority of INTR1 > priority of INTR2 > priority of INTR3.
Draw a schematic of the priority logic, using an interrupt mask register, in which Priority of A > Priority of B > Priority of C.

A
Theory Explanation.
       Operating-Systems       Memory-Management       GATE 1992
Question 15

Consider a 2-way set associative cache memory with 4 sets and total 8 cache blocks (0-7) and a main memory with 128 blocks (0-127). What memory blocks will be present in the cache after the following sequence of memory block references if LRU policy is used for cache block replacement. Assuming that initially the cache did not have any memory block from the current job?

 0 5 3 9 7 0 16 55 
A
0 3 5 7 16 55
B
0 3 5 7 9 16 55
C
0 5 7 9 16 55
D
3 5 7 9 16 55
       Operating-Systems       Memory-Management       GATE 2005-IT
Question 15 Explanation: 
The cache is 2-way associative, so in a set, there can be 2 block present at a time.
So,

Since, each set has only 2 places, 3 will be thrown out as its the least recently used block. So final content of cache will be
0 5 7 9 16 55
Hence, answer is (C).
Question 16

A disk has 8 equidistant tracks. The diameters of the innermost and outermost tracks are 1 cm and 8 cm respectively. The innermost track has a storage capacity of 10 MB.
What is the total amount of data that can be stored on the disk if it is used with a drive that rotates it with (i) Constant Linear Velocity (ii) Constant Angular Velocity?

A
(i) 80 MB (ii) 2040 MB
B
(i) 2040 MB (ii) 80 MB
C
(i) 80 MB (ii) 360 MB
D
(i) 80 MB (ii) 360 MB
       Operating-Systems       Memory-Management       GATE 2005-IT
Question 16 Explanation: 
Constant linear velocity:
Diameter of inner track = d = 1 cm
Circumference of inner track
= 2 * 3.14 * d/2
= 3.14 cm
Storage capacity = 10 MB (given)
Circumference of all equidistant tracks
= 2 * 3.14 * (0.5+1+1.5+2+2.5+3+3.5+4)
= 113.14 cm
Here, 3.14 cm holds 10 MB
Therefore, 1 cm holds 3.18 MB.
So, 113.14 cm holds
113.14 * 3.18 = 360 MB
So, total amount of data that can be hold on the disk = 360 MB.
For constant angular velocity:
In case of CAV, the disk rotates at a constant angular speed. Same rotation time is taken by all the tracks.
Total amount of data that can be stored on the disk
= 8 * 10 = 80 MB
Question 17

A disk has 8 equidistant tracks. The diameters of the innermost and outermost tracks are 1 cm and 8 cm respectively. The innermost track has a storage capacity of 10 MB.
If the disk has 20 sectors per track and is currently at the end of the 5th sector of the inner-most track and the head can move at a speed of 10 meters/sec and it is rotating at constant angular velocity of 6000 RPM, how much time will it take to read 1 MB contiguous data starting from the sector 4 of the outer-most track?

A
13.5 ms
B
10 ms
C
9.5 ms
D
20 ms
       Operating-Systems       Memory-Management       GATE 2005-IT
Question 17 Explanation: 
Radius of inner track is 0.5cm (where the head is standing) and the radius of outermost track is 4cm.
So, the header has to seek (4 - 0.5) = 3.5cm.
For 10m ------- 1s
1m ------- 1/10 s
100cm ------- 1/(10×100) s
3.5cm ------- 3.5/1000 s = 3.5ms
So, the header will take 3.5ms.
Now, angular velocity is constant and header is now at end of 5th sector. To start from front of 4th sector it must rotate upto 18 sector.
6000 rotation in 60000ms.
1 rotation in 10ms (time to traverse 20 sectors).
So, to traverse 18 sectors, it takes 9ms.
In 10ms, 10MB data is read.
So, 1MB data can be read in 1ms.
∴ Total time = 1+9+3.5 = 13.5ms
Question 18

Which one of the following is NOT shared by the threads of the same process?

A
Stack
B
Address Space
C
File Descriptor Table
D
Message Queue
       Operating-Systems       Memory-Management       GATE 2004-IT
Question 18 Explanation: 
Threads cannot share the stack to maintaining the function calls and they can have individual function call sequences.
Question 19

Consider a pipeline processor with 4 stages S1 to S4. We want to execute the following loop:
For(i=1:i<=1000; i++)
{I1,I2,I3,I4}
where the time taken (in ns) by instructions I1 to I4 for stages S1 to S4 are given below:

       S1   S2   S3   S4
I1:    1    2    1    2
I2:    2    1    2    1
I3:    1    1    2    1
I4:    2    1    2    1 
The output of I1 for i=2 will be available after

A
11 ns
B
12 ns
C
13 ns
D
28 ns
       Operating-Systems       Memory-Management       GATE 2004-IT
Question 19 Explanation: 

So, total time would be 13 ns.
Question 20

The storage area of a disk has innermost diameter of 10 cm and outermost diameter of 20 cm. The maximum storage density of the disk is 1400 bits/cm. The disk rotates at a speed of 4200 RPM. The main memory of a computer has 64-bit word length and 1µs cycle time. If cycle stealing is used for data transfer from the disk, the percentage of memory cycles stolen for transferring one word is

A
0.5%
B
1%
C
5%
D
10%
       Operating-Systems       Memory-Management       GATE 2004-IT
Question 20 Explanation: 
y μs is cycle time.
x μs is data transfer time.
% of time CPU idle is,
y/x × 100
Maximum storage density is given, so consider innermost track to get the capacity
= 2 × 3.14 × 5 × 1700 bits
= 3.14 × 14000 bits
Rotational latency = 60/4200 s = 1/70 s
Therefore, to read 64 bits, time required
(106 × 64)/(70 × 3.14 × 17000) μs = 20.8 μs
As memory cycle time given is 1μs,
Therefore, % CPU cycle stolen = (1/20.8) × 100 ≈ 5%
Question 21

A disk has 200 tracks (numbered 0 through 199). At a given time, it was servicing the request of reading data from track 120, and at the previous request, service was for track 90. The pending requests (in order of their arrival) are for track numbers

 30 70 115 130 110 80 20 25 
How many times will the head change its direction for the disk scheduling policies SSTF(Shortest Seek Time First) and FCFS (First Come Fist Serve)

A
2 and 3
B
3 and 3
C
3 and 4
D
4 and 4
       Operating-Systems       Memory-Management       GATE 2004-IT
Question 21 Explanation: 
SSTF: (90) 120 115 110 130 80 70 30 25 20
Direction changes at 120, 110, 130.
FCFS: (90) 120 30 70 115 130 110 80 20 25
Direction changes at 120, 30, 130, 20.
Question 22
In the context of operating systems, which of the following statements is/are correct with respect to paging?
A
Page size has no impact on internal fragmentation.
B
Multilevel paging is necessary to support pages of different sizes.
C
Paging incurs memory overheads.
D
Paging helps solve the issue of external fragmentation.
       Operating-Systems       Memory-Management       GATE 2021 CS-Set-1       Video-Explanation
Question 22 Explanation: 
  1. False, Large page size may lead to higher internal fragmentation.
  2. False, To support pages of different sizes, the Instruction set architecture should support it. Multi-level paging is not necessary.
  3. True, The page table has to be stored in main memory, which is an overhead. 
  4. True, Paging avoids the external fragmentation. 
Question 23
A byte addressable computer has a memory capacity of 2m KB( kbytes ) and can perform 2n operations. An instruction involving 3 operands and one operator needs maximum of
A
3m bits
B
3m + n bits
C
m + n bits
D
None of the above
       Computer-Organization       Memory-Management       ISRO-2018       Video-Explanation
Question 23 Explanation: 
Step-1: Memory capacity is 2m KB = 230m Bytes
Step-2: Total number of operations 2n
Step-3: Every instruction involving 3 operands and 1 operator
Step-4: Number of bits needed by instruction is= 3*(m+10)+n
=3m+n+30 bits
Question 24
The Operating System of a computer may periodically collect all the free memory space to form contiguous block of free space. This is called:
A
Concatenation
B
Garbage collection
C
Collision
D
Dynamic Memory Allocation
       Operating-Systems       Memory-Management       ISRO-2018       Video-Explanation
Question 24 Explanation: 
→ The Operating System of a computer may periodically collect all the free memory space to form a contiguous block of free space. This is called garbage collection
→ We can also use compaction to minimize the probability of external fragmentation.
→ In compaction, all the free partitions are made contiguous and all the loaded partitions are brought together.
Question 25
A computer has 1000 K of main memory. The jobs arrive and finish in the sequence
Job 1 requiring 200 K arrives
Job 2 requiring 350 K arrives
Job 3 requiring 300 K arrives
Job 1 finishes
Job 4 requiring 120 K arrives
Job 5 requiring 150 K arrives
Job 6 requiring 80 K arrives
Among the best fit and first fit, which performs better for this sequence?
A
First fit
B
Best fit
C
Both perform the same
D
None of the above
       Operating-Systems       Memory-Management       ISRO-2018       Video-Explanation
Question 25 Explanation: 
Main memory = 1000K
Job 1 requiring 200 K arrives
Job 2 requiring 350 K arrives
Job 3 requiring 300 K arrives and assuming continuous allocation:
Free memory = 1000 − 850(200 + 350 + 300) = 150 K (till these jobs first fit and best fit are same)
Since, job 1 finishes, Free memory = 200 K and 150 K
Case 1: First fit
Job 4 requiring 120 K arrives
Since 200 K will be the first slot, so Job 4 will acquire this slot only. Remaining memory = 200 – 120 = 80 K
Job 5 requiring 150 K arrives
It will acquire 150 K slot
Job 6 requiring 80 K arrives
It will occupy 80 K slot, so, all jobs will be allocated successfully.
Case 2: Best fit
Job 4 requiring 120 K arrives
It will occupy best fit slot which is 150 K. So, remaining memory = 150 − 120 = 30 K
Job 5 requiring 150 K arrives
It will occupy 200 K slot. So, free space = 200 − 150 = 50 K
Job 6 requiring 80 K arrives
There is no continuous 80 K memory free. So, it will not be able to allocate.
So, first fit is better.
Question 26
Consider a logical address space of 8 pages of 1024 words mapped into memory of 32 frames. How many bits are there in the logical address?
A
13 bits
B
15 bits
C
14 bits
D
12 bits
       Operating-Systems       Memory-management       ISRO CS 2008
Question 26 Explanation: 
logical address space = 8 pages of 1024 words
number of bits in logical address space = p (page bits) + d (offset bits)
number of bits = log28 + log21024 = 3 + 10 = 13 bits
Question 27
Let the page fault service time be 10 ms in a computer with average memory access time being 20 ns. If the one-page fault is generated for every 106 memory accesses, what is the effective access time for the memory?
A
21.4 ns
B
29.9 ns
C
23.5 ns
D
35.1 ns
       Operating-Systems       Memory-Management       ISRO-2016
Question 27 Explanation: 
Question 28
A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation lookaside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is:
A
11 bits
B
13 bits
C
15 bits
D
20 bits
       Operating-Systems       Memory-Management       ISRO-2016
Question 28 Explanation: 
Page size = 4 KB = 4 × 210 Bytes = 212 Bytes
Virtual Address = 32 bit
No. of bits needed to address the page frame = 32 - 12 = 20
TLB can hold 128 page table entries with 4-way set associative
⇒ 128/4=32=25
→ 5 bits are needed to address a set.
→ The size of TLB tag = 20 - 5 = 15 bits
Question 29
If the page size in a 32-bit machine is 4K bytes then the size of the page table is
A
1 M bytes
B
2 M bytes
C
4 M bytes
D
4 K bytes
       Operating-Systems       Memory-Management       ISRO CS 2011
Question 29 Explanation: 
→Page size is total space taken up by page and Page table entry size is memory taken for indexing the Page in Page Table
→Size of logical address = 32 bits
→Page size = 4K =22210=212 Bytes
→Number of pages = logical address space/ size of each page = 232/ 212= 220
→Page table size = number of pages * size of a page table entry
= 220 * 22
= 222
Question 30
In a system using a single processor, a new process arrives at the rate of six processes per minute and each such process requires seven seconds of service time. What is the CPU utilization?
A
70%
B
30%
C
60%
D
64%
       Operating-Systems       Memory-Management       ISRO CS 2011
Question 30 Explanation: 
From the given question,
The number of new processes will arrive per minute = 6
Each process require to complete its task = 7 secs
CPU utilization time within a minute = 6*7 = 42 secs
The percentage of CPU utilization = time which is spent for utilization / total time * 100
= (42/60) * 100
= 70%
Question 31
Consider a 32-bit machine where four-level paging scheme is used. If the hit ratio to TLB is 98%, and it takes 20 nanosecond to search the TLB and 100 nanoseconds to access the main memory what is effective memory access time in nanoseconds?
A
126
B
128
C
122
D
120
       Operating-Systems       Memory-Management       ISRO CS 2011
Question 31 Explanation: 
Hit ratio to TLB(H) is 98%
Searching time of TLB(T) is 20ns
Access time(M) is 100ns and four level paging scheme is used.
Effective Memory access Time, EAT = H* T+ (1 - H)[ T+ 4*M] + M]
EAT = (0.98 *20) + 0.02(20 + 400) + 100
= 19.6 + 8.4 + 100 = 128 ns
Question 32
Consider a logical address space of 8 pages of 1024 words each, mapped onto a physical memory of 32 frames. How many bits are there in the physical address and logical address respectively?
A
5, 3
B
10, 10
C
15, 13
D
15, 15
       Operating-Systems       Memory-Management       ISRO CS 2013
Question 32 Explanation: 
→Number of pages= 8= 23=(3 bits)
→Each page consists of 1024 words =210(10 bits)
→Logical address space consists of 8 pages of 1024 words each,
→Then the number of bits required for logical address is 3+10=13 bits.
→Total number of frames =32=25(5 bits).
→The logical memory is mapped to physical memory which means mapping should done between pages and frames.
→Physical address = 5(number of bits for frames) + 10 (number of bits for pages)= 15 bits
Question 33
In a 64-bit machine, with 2 GB RAM, and 8 KB page size, how many entries will be there in the page table if it is inverted?
A
218
B
220
C
233
D
251
       Operating-Systems       Memory-Management       ISRO CS 2013
Question 33 Explanation: 
Given data is
Memory size = 2 GB = 231
Page size = 8 KB = 213
Number of entries in inverted page table = physical address space / page size = 231/213 = 218
Question 34
Consider the following segment table in the segmentation scheme:

What happens if the logical address requested is Segment ID 2 and offset 1000?
A
Fetches the entry at the physical address 2527 for segment Id2
B
A trap is generated
C
Deadlock
D
Fetches the entry at offset 27 in Segment Id 3
       Operating-Systems       Memory-Management       ISRO CS 2014
Question 34 Explanation: 
From the question we need to find the logical address for segment id-2.
From given table,
Segment-2 has a base address = 1527 ‘
limit address = 498.
Process can access memory from the location 1527 to 2025(1527+498)
If the process tries to access the memory with offset 1000 then a segmentation fault trap will be generated.
In computing and operating systems, a trap, also known as an exception or a fault, is typically a type of synchronous interrupt caused by an exceptional condition (e.g., breakpoint, division by zero, invalid memory access)
Question 35
Dirty bit is used to indicate which of the following?
A
A page fault has occurred
B
A page has corrupted data
C
A page has been modified after being loaded into cache
D
An illegal access of page
       Operating-Systems       Memory-Management       ISRO CS 2014
Question 35 Explanation: 
→ The dirty bit allows for a performance optimization i.e., Dirty bit for a page in a page table helps to avoid unnecessary writes on a paging device
→ When a page is modified inside the cache and the changes need to be stored back in the main memory, the valid bit is set to 1 so as to maintain the record of modified pages.
Question 36
What is the size of the physical address space in a paging system which has a page table containing 64 entries of 11 bit each (including valid and invalid bit) and a page size of 512
A
211
B
215
C
219
D
220
       Operating-Systems       Memory-Management       ISRO CS 2014
Question 36 Explanation: 
Size of Physical Address = Paging bits + Offset bits
Paging bits = 11 – 1 = 10 (As 1 valid bit is also included)
Offset bits = log2 (page size) =log2 (512) =9
Size of Physical Address = 10 + 9 = 19 bits
There are 36 questions to complete.

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