RISC-and-CISC
Question 1 |
A processor X 1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X 2 operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for X 1 and X 2 . If the BPU has a prediction accuracy of 80%, the speed up (rounded off to two decimal places) obtained by X 2 over X 1 in executing P is____________.
1.43 |
Question 1 Explanation:
The effective CPI in X1 : (1+Stall frequency * No. of stall cycles)
It is given that there are 30% branch instructions and each branch instruction causes 2 stall cycles.
= 1+0.3*2 = 1.6
In X2 there is a branch predictor which predicts correctly 80% of the time. Only in 20% cases the prediction is wrong. So, out of the 30% of branch instructions only 20% of them now lead to stalls.
The effective CPI in X2 : (1+Stall frequency * No. of stall cycles) = (1+0.3*0.2*2) = 1.12
Since the processor speed remains the same, the clock cycle time also doesn’t change. Hence speedup of X2 over X1 : 1.6/1.12 = 1.43
It is given that there are 30% branch instructions and each branch instruction causes 2 stall cycles.
= 1+0.3*2 = 1.6
In X2 there is a branch predictor which predicts correctly 80% of the time. Only in 20% cases the prediction is wrong. So, out of the 30% of branch instructions only 20% of them now lead to stalls.
The effective CPI in X2 : (1+Stall frequency * No. of stall cycles) = (1+0.3*0.2*2) = 1.12
Since the processor speed remains the same, the clock cycle time also doesn’t change. Hence speedup of X2 over X1 : 1.6/1.12 = 1.43
There is 1 question to complete.