NTA UGC NET DEC-2022 Paper-2

Consider an unpipelined machine with 10nsec clock cycles which uses four cycles for ALU operations and branches whereas five cycles for memory operation. Assume that the relative frequencies of those operations are: 40% , 20% and 40%, respectively. Due to clock skew and setup pipeline let us consider that the machine adds one nsec overhead to the clock. How much speedup is observed in the instruction execution rate when a pipelined machine is considered.