Question 9393 – Cache
November 12, 2023
Question 16133 – Cache
November 12, 2023
Question 9393 – Cache
November 12, 2023
Question 16133 – Cache
November 12, 2023

Question 9394 – Cache

A CPU has a 32 KB direct mapped cache with 128-byte block size. Suppose A is a two-dimensional array of size 512×512 with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.

P1: for (i=0; i<512; i++) {
      for (j=0; j<512; j++) {
         x += A[i][j]; 
      }
    }

P2: for (i=0; i<512; i++) {
      for (j=0; j<512; j++) {
        x += A[j][i];
      }
    } 

P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.

The value of the ratio M1/M2 is:

Correct Answer: B

Question 15 Explanation: 
Total misses for [P2] = 512 * 512 = 262144
(for every element there would be a miss)
M1/M2 = 16384/262144 = 1/16
A
0
B
1/16
C
1/8
D
16
0 0 votes
Article Rating
Subscribe
Notify of
0 Comments
Inline Feedbacks
View all comments
0
Would love your thoughts, please comment.x
()
x
error: Alert: Content selection is disabled!!