Question 9098 – Software-Engineering
November 20, 2023
Question 1370 – Knowledge-representation
November 20, 2023
Question 9098 – Software-Engineering
November 20, 2023
Question 1370 – Knowledge-representation
November 20, 2023

Question 16767 – NTA-UGC-NET 2021 Dec & 2022 June Paper-2

A 4-stage pipeline has the stage delay as 150,120,160 and 140ns respectively. Registers that are used between the stages have delay of 5ns. Assuming constant locking rate, the total time required to process 1000 data items on this pipeline is____?

Correct Answer: B

Question 17 Explanation: 
First instruction will take complete four cycle for execution. And then after that all 999 instruction will take only 1 cycle for execution to be completed. So time required to process 1000 instruction or data items is,
1st instruction × 4 × clock time + 999 instruction × 1 × clock time
1 × 4 × 165ns + 999 × 1 × 165ns
= 1654.95ns
= 165.5μs
A
160.5 ms
B
165.5 ms
C
120.5 ms
D
590.5 ms
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