Question 7680 – UGC-NET DEC-2019 Part-2

Common RISC characteristics
→ Load/store architecture (also called register-register or RR architecture) which fetches operands and results indirectly from main memory through a lot of scalar registers. Other architecture is storage-storage or SS in which source operands and final results are retrieved directly from memory.
→ Fixed length instructions which (a) are easier to decode than variable length instructions, and (b) use fast, inexpensive memory to execute a larger piece of code.
→ Hardwired controller instructions (as opposed to microcoded instructions). This is where RISC really shines as hardware implementation of instructions is much faster and uses less silicon real estate than a microstore area.
→ Fused or compound instructions which are heavily optimized for the most commonly used functions.
→ Pipelined implementations with the goal of executing one instruction (or more) per machine cycle.
→ Large uniform register set
→ Minimal number of addressing modes
→ no/minimal support for misaligned accesses
Characteristic of CISC:
→ Complex instruction, hence complex instruction decoding.
→ Instruction are larger than one word size.
→ Instruction may take more than a single clock cycle to get executed.
→ Less number of general purpose register as operation get performed in memory itself.
→ Complex Addressing Modes.
→ More Data types.