OOPS
December 28, 2023JT(IT) 2018 PART-A General Aptitude
December 28, 2023GATE 2003
| Question 10 |
For a pipelined CPU with a single ALU, consider the following situations
I. The j + 1-st instruction uses the result of the j-th instruction as an operand II. The execution of a conditional jump instruction III. The j-th and j + 1-st instructions require the ALU at the same time
Which of the above can cause a hazard?
| I and II only | |
| II and III only | |
| III only | |
| All the three |
Question 10 Explanation:
I is belongs to the Data hazard.
II is belongs to the Control hazard.
III is belongs to the Structural hazard.
→ Hazards are the problems with the instruction pipeline in CPU micro architectures.
II is belongs to the Control hazard.
III is belongs to the Structural hazard.
→ Hazards are the problems with the instruction pipeline in CPU micro architectures.
Correct Answer: D
Question 10 Explanation:
I is belongs to the Data hazard.
II is belongs to the Control hazard.
III is belongs to the Structural hazard.
→ Hazards are the problems with the instruction pipeline in CPU micro architectures.
II is belongs to the Control hazard.
III is belongs to the Structural hazard.
→ Hazards are the problems with the instruction pipeline in CPU micro architectures.