Question 9816 – Pipelining
January 10, 2024Question 9811 – GATE 2000
January 10, 2024Question 9798 – Pipelining
Consider a 5-stage pipeline – IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (memory), and WB (Write Back). All (memory or register) reads take place in the second phase of a clock cycle and writes occur in the first phase of the clock cycle. Consider the execution of the following instruction sequence:
11: sub r2, r3, r4; /* r2 ← r3 – r4 */ 12: sub r4, r2, r3; /* r4 ← r2 – r3 */ 13: sw r2, 100(r1) /* M[r1+100] ← r2 */ 14: sub r3, r4, r2; /* r3 ← r4 – r2 */
(a) Show all data dependencies between the four instructions.
(b) Identify the data hazards.
(c) Can all hazards be avoided by forwarding in this case?
Correct Answer: A
Theory Explanation is given below.
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