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Question 9897 – Digital-Logic-Design
February 13, 2024
Question 9842 – Digital-Logic-Design
February 13, 2024
Question 9897 – Digital-Logic-Design
February 13, 2024
Question 9842 – Digital-Logic-Design
February 13, 2024

Question 9898 – Digital-Logic-Design

The maximum gate delay for any output to appear in an array multiplier for multiplying two n bit number is

Correct Answer: B

Question 41 Explanation: 
Total no. of gates being used for ‘n’ bit multiplication in an array multiplier (n*n) = (2n-1)
Total delay = 1 * 2n – 1 = O(2n – 1) = n
A
On2
B
O(n)
C
O(log n)
D
O(1)
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