Digital-Logic-Design
February 13, 2024Question 9842 – Digital-Logic-Design
February 13, 2024Question 9898 – Digital-Logic-Design
The maximum gate delay for any output to appear in an array multiplier for multiplying two n bit number is
Correct Answer: B
Question 41 Explanation:
Total no. of gates being used for ‘n’ bit multiplication in an array multiplier (n*n) = (2n-1)
Total delay = 1 * 2n – 1 = O(2n – 1) = n
Total delay = 1 * 2n – 1 = O(2n – 1) = n
On2
O(n)
O(log n)
O(1)