Question 17142 – NTA UGC NET JUNE-2023 Paper-2
May 12, 2024Question 9853 – Operating-Systems
May 12, 2024GATE 2006
| Question 62 |
A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is:
| 11 bits | |
| 13 bits | |
| 15 bits | |
| 20 bits |
Question 62 Explanation:
Page size = 4 KB = 4 × 210 Bytes = 212 Bytes
Virtual Address = 32 bit
No. of bits needed to address the page frame = 32 – 12 = 20
TLB can hold 128 page table entries with 4-way set associative
⇒ 128/4=32=25
→ 5 bits are needed to address a set.
→ The size of TLB tag = 20 – 5 = 15 bits
Virtual Address = 32 bit
No. of bits needed to address the page frame = 32 – 12 = 20
TLB can hold 128 page table entries with 4-way set associative
⇒ 128/4=32=25
→ 5 bits are needed to address a set.
→ The size of TLB tag = 20 – 5 = 15 bits
Correct Answer: C
Question 62 Explanation:
Page size = 4 KB = 4 × 210 Bytes = 212 Bytes
Virtual Address = 32 bit
No. of bits needed to address the page frame = 32 – 12 = 20
TLB can hold 128 page table entries with 4-way set associative
⇒ 128/4=32=25
→ 5 bits are needed to address a set.
→ The size of TLB tag = 20 – 5 = 15 bits
Virtual Address = 32 bit
No. of bits needed to address the page frame = 32 – 12 = 20
TLB can hold 128 page table entries with 4-way set associative
⇒ 128/4=32=25
→ 5 bits are needed to address a set.
→ The size of TLB tag = 20 – 5 = 15 bits