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GATE 2006
April 6, 2025
GATE 2006-IT
April 6, 2025
GATE 2006
April 6, 2025
GATE 2006-IT
April 6, 2025

GATE 2006-IT

Question 8

Which of the following DMA transfer modes and interrupt handling mechanisms will enable the highest I/O band-width?

A
Transparent DMA and Polling interrupts
B
Cycle-stealing and Vectored interrupts
C
Block transfer and Vectored interrupts
D
Block transfer and Polling interrupts
Question 8 Explanation: 
→ CPU has highest bandwidth in transparent DMA and polling. But it asked for I/O bandwidth not CPU bandwidth option. A is wrong.
→ In case of cycle stealing in each cycle time derive send data then wait again few CPU cycle it sends to memory. So, option B is wrong.
→ In case of polling CPU takes the initiative. So I/O bandwidth cannot be high. So, option D is wrong.
→ Consider block transfer in each single block device. Send data so bandwidth must be high. This makes option (C) correct.
Correct Answer: C
Question 8 Explanation: 
→ CPU has highest bandwidth in transparent DMA and polling. But it asked for I/O bandwidth not CPU bandwidth option. A is wrong.
→ In case of cycle stealing in each cycle time derive send data then wait again few CPU cycle it sends to memory. So, option B is wrong.
→ In case of polling CPU takes the initiative. So I/O bandwidth cannot be high. So, option D is wrong.
→ Consider block transfer in each single block device. Send data so bandwidth must be high. This makes option (C) correct.

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