Database-Management-System
August 17, 2023NIC-NIELIT Scientist-B 2020
August 18, 2023ISRO CS 2020
| Question 2 |
A non-pipelined CPU has 12 general purpose registers(R0, R1, R2,……..R12). Following operations are supported
ADD Ra, Rb, Rr Add Ra to Rb and store the result in Rr
MUL Ra, Rb, Rr Multiply Ra to Rb and store the result in Rr
MUL operations takes two clock cycles, ADD takes one clock cycle.
Calculate the minimum number of clock cycles required to compute the value of the expression XY+XYZ+YZ. The variables X, Y, Z are initially available in registers R0, R1 and R2 contents of these registers must not be modified.
ADD Ra, Rb, Rr Add Ra to Rb and store the result in Rr
MUL Ra, Rb, Rr Multiply Ra to Rb and store the result in Rr
MUL operations takes two clock cycles, ADD takes one clock cycle.
Calculate the minimum number of clock cycles required to compute the value of the expression XY+XYZ+YZ. The variables X, Y, Z are initially available in registers R0, R1 and R2 contents of these registers must not be modified.
| 5 | |
| 6 | |
| 7 | |
| 8 |
Question 2 Explanation:
In a non-pipelined processor, each instruction will take its full number of cycles to complete before the next instruction can begin.
1. Compute XY:
– MUL R0, R1, R3 (result stored in R3)
2. Compute XYZ:
– MUL R3, R2, R4 (result stored in R4)
3. Compute YZ:
– MUL R1, R2, R5 (result stored in R5)
4. Add the results:
– ADD R3, R4, R6 (add XY and XYZ, store result in R6)
– ADD R6, R5, R7 (add result of step 4 with YZ, store result in R7)
So, we have used a total of 3 MUL operations and 2 ADD operations. Each MUL operation takes 2 cycles, and each ADD operation takes 1 cycle.
Total cycles = (3 MUL operations * 2 cycles per MUL) + (2 ADD operations * 1 cycle per ADD) = 6 cycles.
Therefore, the correct answer is indeed B) 6 cycles.
1. Compute XY:
– MUL R0, R1, R3 (result stored in R3)
2. Compute XYZ:
– MUL R3, R2, R4 (result stored in R4)
3. Compute YZ:
– MUL R1, R2, R5 (result stored in R5)
4. Add the results:
– ADD R3, R4, R6 (add XY and XYZ, store result in R6)
– ADD R6, R5, R7 (add result of step 4 with YZ, store result in R7)
So, we have used a total of 3 MUL operations and 2 ADD operations. Each MUL operation takes 2 cycles, and each ADD operation takes 1 cycle.
Total cycles = (3 MUL operations * 2 cycles per MUL) + (2 ADD operations * 1 cycle per ADD) = 6 cycles.
Therefore, the correct answer is indeed B) 6 cycles.
Correct Answer: B
Question 2 Explanation:
In a non-pipelined processor, each instruction will take its full number of cycles to complete before the next instruction can begin.
1. Compute XY:
– MUL R0, R1, R3 (result stored in R3)
2. Compute XYZ:
– MUL R3, R2, R4 (result stored in R4)
3. Compute YZ:
– MUL R1, R2, R5 (result stored in R5)
4. Add the results:
– ADD R3, R4, R6 (add XY and XYZ, store result in R6)
– ADD R6, R5, R7 (add result of step 4 with YZ, store result in R7)
So, we have used a total of 3 MUL operations and 2 ADD operations. Each MUL operation takes 2 cycles, and each ADD operation takes 1 cycle.
Total cycles = (3 MUL operations * 2 cycles per MUL) + (2 ADD operations * 1 cycle per ADD) = 6 cycles.
Therefore, the correct answer is indeed B) 6 cycles.
1. Compute XY:
– MUL R0, R1, R3 (result stored in R3)
2. Compute XYZ:
– MUL R3, R2, R4 (result stored in R4)
3. Compute YZ:
– MUL R1, R2, R5 (result stored in R5)
4. Add the results:
– ADD R3, R4, R6 (add XY and XYZ, store result in R6)
– ADD R6, R5, R7 (add result of step 4 with YZ, store result in R7)
So, we have used a total of 3 MUL operations and 2 ADD operations. Each MUL operation takes 2 cycles, and each ADD operation takes 1 cycle.
Total cycles = (3 MUL operations * 2 cycles per MUL) + (2 ADD operations * 1 cycle per ADD) = 6 cycles.
Therefore, the correct answer is indeed B) 6 cycles.
What is the correct answer since in the video explanation it’s different. And option is option B) 6 in the video
Yes. The correct answer is 6 only. Please follow video explanation.