Adder

Question 1

Consider an eight-bit ripple-carry adder for computing the sum of A and B, where A and B are integers represented in 2’s complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is _________.

A
-1
B
-2
C
-3
D
-4
       Digital-Logic-Design       Adder       GATE 2016 [Set-2]
Question 1 Explanation: 
In the question, longest LATENCY means longest DELAY for the sum to get settle.
If we do 2's complement of 1 = 0000 0001, we get -1 = "1111 1111"

So, if B = -1, every carry bit is 1.
Question 2

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ____________.

A
19.1
B
19.2
C
18.1
D
18.2
       Digital-Logic-Design       Adder       GATE 2015 [Set-2]
Question 2 Explanation: 

Here, each Full Adder is taking 4.8 microseconds. Given adder is a 4 Bit Ripple Carry Adder. So it takes 4*4.8 = 19.2 microseconds.
Question 3

Consider the ALU shown below.

If the operands are in 2's complement representation, which of the following operations can be performed by suitably setting the control lines K and C0 only (+ and - denote addition and subtraction respectively)?

A
A + B, and A – B, but not A + 1
B
A + B, and A + 1, but not A – B
C
A + B, but not A – B or A + 1
D
A + B, and A – B, and A + 1
       Digital-Logic-Design       Adder       GATE 2003
Question 3 Explanation: 
The circuits performs
1) A+B when K=0 and C0 = 0. It is binary adder which performs addition of two binary numbers.
2) A - B = A+ B' + 1 when K=1 and C0 = 1 ;
Here XOR gates produce B' if K=1. Since 1⊕b= b'.
"1" in (A+B+1) is coming from C0.
Note: 2's complement of B is (B'+1). 3) A+1 when B=0, K=0, C0= 1.
Increments A.
Question 4

The number of full and half-adders required to add 16-bit numbers is

A
8 half-adders, 8 full-adders
B
1 half-adder, 15 full-adders
C
16 half-adders, 0 full-adders
D
4 half-adders, 12 full-adders
       Digital-Logic-Design       Adder       GATE 1999
Question 4 Explanation: 
For Least Significant Bit we do not need a full adder since initially carry is not present.
But for rest of bits we need full address since carry from previous addition has to be included into the addition operation.
So, in total 1 half adder and 15 full adders are required.
Question 5

An N-bit carry look ahead adder, where N is a multiple of 4, employs ICs 74181 (4 bit ALU) and 74182 (4 bit carry look ahead generator).

The minimum addition time using the best architecture for this adder is

A
proportional to N
B
proportional to log N
C
a constant
D
None of the above
       Digital-Logic-Design       Adder       GATE 1997
Question 6

Consider the circuit given below which has a four bit binary number b3b2b1b0 as input and a five bit binary number d4d3d2d1d0 as output. The circuit implements:

A
Binary of Hex conversion
B
Binary to BCD conversion
C
Binary to grey code conversion
D
Binary to radix-12 conversion
       Digital-Logic-Design       Adder       GATE 1996
Question 6 Explanation: 
Here ф means 0.
Whenever, b2 = b3 = 1, then only 0100, i.e., 4 is added to the given binary number. Lets write all possibilities for b.

Note that the last 4 combinations leads to b3 and b2 as 1. So, in these combinations only 0010 will be added.
1100 is 12
1101 is 13
1110 is 14
1111 is 15
in binary unsigned number system.
1100 + 0100 = 10000
1101 + 0100 = 10001, and so on.
This is conversion to radix 12.
Question 7
How many inputs are required in full adder circuit?
A
2
B
3
C
more than two inputs
D
None of the above
       Digital-Logic-Design       Adder       Nielit Scientist-B IT 4-12-2016
Question 7 Explanation: 
● The difference between a half-adder and a full adder is that the full-adder has three inputs and two outputs, whereas half adder has only two inputs and two outputs.
● The first two inputs are A and B and the third input is an input carry as C-IN. When a full-adder logic is designed, you string eight of them together to create a byte-wide adder and cascade the carry bit from one adder to the next.
● Note: Here, answer they are given ambiguous because it takes minimum 3 input line
Question 8
In which of the following adder circuits, the carry look ripple delay is eliminated?
A
Half Adder
B
Full Adder
C
Parallel adder
D
Carry-Look-Ahead adder
       Digital-Logic-Design       Adder       Nielit Scientist-B CS 2016 march
Question 8 Explanation: 
A carry-lookahead adder (CLA) or fast adder is a type of adder used in digital logic. A carry-lookahead adder improves speed by reducing the amount of time required to determine carry bits. It can be contrasted with the simpler, but usually slower, ripple-carry adder (RCA), for which the carry bit is calculated alongside the sum bit, and each bit must wait until the previous carry bit have been calculated to begin calculating its own result and carry bits. The carry-lookahead adder calculates one or more carry bits before the sum, which reduces the wait time to calculate the result of the larger-value bits of the adder.
Question 9
The number of full and half adders required to add 16-bit numbers is
A
8 half adders, 8 full adders
B
1 half adders, 5 full adders
C
16 half adders, 0 full adders
D
4 half adders, 12 full adders
       Digital-Logic-Design       Adder       NieLit STA 2016 March 2016
Question 9 Explanation: 
One half adder can add the least significant bit of the two numbers whereas full adders are required to add the remaining 15 bits as they all involve adding carries.
Question 10
Which of the following expression is not equivalent to ~x?
A
x NAND x
B
x NOR x
C
x NAND 1
D
X NOR 1
       Digital-Logic-Design       Adder       NieLit STA 2016 March 2016
Question 10 Explanation: 
Question 11
If half adders and full adders are implemented using gates, then for the addition of two 17 bit numbers (using minimum gates) the number of half adders and full adders required will be
A
0, 17
B
16, 1
C
1, 16
D
8, 8
       Digital-Logic-Design       Adder       ISRO CS 2015
Question 11 Explanation: 
1. An adder is a digital circuit that performs addition of numbers. The half adder adds two binary digits called as augend and addend and produces two outputs as sum and carry; XOR is applied to both inputs to produce sum and AND gate is applied to both inputs to produce carry.
2. The full adder adds 3 one bit numbers, where two can be referred to as operands and one can be referred to as bit carried in. And produces 2-bit output, and these can be referred to as output carry and sum.
Half adder is used to add two numbers of the least significant bits, so one half adder is required. In order to add remaining 16 bits of two numbers , we require 16 full adders
Question 12
The logic circuits binary adder which is used to add two 4-bits binary numbers, requires___half adder(s) and _____full adder(s).
A
4,0
B
1,3
C
2,2
D
3,1
       Digital-Logic-Design       Adder       KVS DEC-2017
Question 12 Explanation: 
Half Adder takes two input bits and output sum and carry. Full Adder takes three input bits(which includes one carry bit) and output sum and carry.
One Half- Adder adds least significant bits of the two numbers. Three Full Adders
Question 13
A full binary adder to add 4 bits requires_____ full adder(s) and ___half adder(s).
A
1,3
B
2,2
C
3,1
D
4,0
       Digital-Logic-Design       Adder       KVS 30-12-2018 Part B
Question 13 Explanation: 
Half Adder takes two input bits and output sum and carry. Full Adder takes three input bits(which includes one carry bit) and output sum and carry.
There is no carry in to the least significant bits. So one Half- Adder adds least significant bits of the two numbers.
Three Full Adders are used to add remaining bits along with carries.
Question 14
Consider a full - adder with the following input values:
(a)x = 1, y = 0 and C​ i​ (carry input) = 0
(b)x = 0, y = 1 and C​ i​ = 1 Compute the values of S(sum) and C​ o​ (carry output) for the above input values.
A
S = 1, C​ o​ = 0 and S = 0, C​ o​ = 1
B
S = 1, C​ o​ = 0 and S = 1, C​ o​ = 1
C
S = 1, C​ o​ = 1 and S = 1, C​ o​ = 0
D
S0 = 1, C​ o​ = 1 and S = 1, C​ o​ = 0
       Digital-Logic-Design       Adder       UGC NET CS 2015 Jun- paper-2
Question 14 Explanation: 

For the given x and y values, the correct option is A
There are 14 questions to complete.
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