Question 1

Consider an eight-bit ripple-carry adder for computing the sum of A and B, where A and B are integers represented in 2’s complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is _________.

       Digital-Logic-Design       Adder       GATE 2016 [Set-2]       Video-Explanation
Question 1 Explanation: 
In the question, longest LATENCY means longest DELAY for the sum to get settle.
If we do 2's complement of 1 = 0000 0001, we get -1 = "1111 1111"

So, if B = -1, every carry bit is 1.
Question 2

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ____________.

       Digital-Logic-Design       Adder       GATE 2015 [Set-2]
Question 2 Explanation: 

Here, each Full Adder is taking 4.8 microseconds. Given adder is a 4 Bit Ripple Carry Adder. So it takes 4*4.8 = 19.2 microseconds.
Question 3

Consider the ALU shown below.

If the operands are in 2's complement representation, which of the following operations can be performed by suitably setting the control lines K and C0 only (+ and - denote addition and subtraction respectively)?

A + B, and A – B, but not A + 1
A + B, and A + 1, but not A – B
A + B, but not A – B or A + 1
A + B, and A – B, and A + 1
       Digital-Logic-Design       Adder       GATE 2003
Question 3 Explanation: 
The circuits performs
1) A+B when K=0 and C0 = 0. It is binary adder which performs addition of two binary numbers.
2) A - B = A+ B' + 1 when K=1 and C0 = 1 ;
Here XOR gates produce B' if K=1. Since 1⊕b= b'.
"1" in (A+B+1) is coming from C0.
Note: 2's complement of B is (B'+1). 3) A+1 when B=0, K=0, C0= 1.
Increments A.
Question 4

The number of full and half-adders required to add 16-bit numbers is

8 half-adders, 8 full-adders
1 half-adder, 15 full-adders
16 half-adders, 0 full-adders
4 half-adders, 12 full-adders
       Digital-Logic-Design       Adder       GATE 1999
Question 4 Explanation: 
For Least Significant Bit we do not need a full adder since initially carry is not present.
But for rest of bits we need full address since carry from previous addition has to be included into the addition operation.
So, in total 1 half adder and 15 full adders are required.
There are 4 questions to complete.

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