Combinational-Circuit
Question 1 |
If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m + n is ____.
1034 |
Question 1 Explanation:
The size of the decoder required is 10 x 210 i.e., 10 x 1024.
Each output line of the decoder is connected to one of the 1K(= 1024) rows of RAM.
Each row stores 1 Byte.
m=10 and n=1024
Each output line of the decoder is connected to one of the 1K(= 1024) rows of RAM.
Each row stores 1 Byte.
m=10 and n=1024
Question 2 |
A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is _____.
5 |
Question 2 Explanation:
Number of registers is 32. Only one register has to be selected at any instant of time.
A 25x1 Multiplexer with 5 select lines selects one of the 32(= 25) registers at a time depending on the selection input.
The content from the selected register will be transferred through the output line to the Accumulator.
A 25x1 Multiplexer with 5 select lines selects one of the 32(= 25) registers at a time depending on the selection input.
The content from the selected register will be transferred through the output line to the Accumulator.
Question 3 |
Which one of the following circuits implements the Boolean function given below?
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Question 3 Explanation:
Question 4 |
Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16-bit code word is used to load a word in X, either from S or from R. S is a 1024-word memory segment and R is a 32-word register file. Based on the value of mode bit M, T selects an input word to load in X. P and Q interface with the corresponding bits in the code word to choose the addressed word. Which one of the following represents the functionality of P, Q, and T?
P is 10:1 multiplexer; Q is 5:1 multiplexer; T is 2:1 multiplexer | |
P is 10:2 ^10 decoder; Q is 5:2^ 5 decoder; T is 2:1 encoder | |
P is 10:2^ 10 decoder; Q is 5:2^ 5 decoder; T is 2:1 multiplexer | |
P is 1:10 de-multiplexer; Q is 1:5 de-multiplexer; T is 2:1 multiplexer |
Question 4 Explanation:
P is a 10:2^10 decoder that takes a 10-bit address from S-address as input and enable one of the 1024 words of the S memory.
Q is a 5:2^5 decoder that takes a 5-bit address from R-address as input and enable one of the 32 words of the R memory.
T is a 2x1 Multiplexer that select one of the 2 inputs and transmit it as output.
Q is a 5:2^5 decoder that takes a 5-bit address from R-address as input and enable one of the 32 words of the R memory.
T is a 2x1 Multiplexer that select one of the 2 inputs and transmit it as output.
Question 5 |
State whether the following statements are TRUE or FALSE with reason:
RAM is a combinational circuit and PLA is a sequential circuit.True | |
False |
Question 5 Explanation:
1) RAM is not a combinational circuit. For RAM, the input is the memory location selector and operation (read or write) and another byte (which can be input for write operation or output for read operation), and the output is either a success indicator (for write operation) or the byte at the selected location (for read operation). It does depend on past inputs, or rather, on the past write operations at the selected byte. This is a sequential logic circuit.
2) PLA is a combination circuit as ROM. PLA is a programmable AND array and a programmable OR array. A PLA with n inputs has fewer than 2n AND gates (otherwise there would be no advantage over a ROM implementation of the same size). A PLA only needs to have enough AND gates to decode as many unique terms as there are in the functions it will implement it.
2) PLA is a combination circuit as ROM. PLA is a programmable AND array and a programmable OR array. A PLA with n inputs has fewer than 2n AND gates (otherwise there would be no advantage over a ROM implementation of the same size). A PLA only needs to have enough AND gates to decode as many unique terms as there are in the functions it will implement it.
Question 6 |
A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001, ..., 9 by 1001. A combinational circuit is to be designed which takes these 4 bits as input and outputs 1 if the digit ≥ 5, and 0 otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required?
2 | |
3 | |
4 | |
5 |
Question 6 Explanation:
= A + BD + BC
= A + B (D + C)
So minimum two OR gates and 1 AND gate is required. Hence, in total minimum 3 gates is required.
Question 7 |
The amount of ROM needed to implement a 4 bit multiplier is
64 bits | |
128 bits | |
1 Kbits | |
2 Kbits |
Question 7 Explanation:
To implement a 4-bit multiplier we need to store all the possible combinations of 24 x 24 inputs and their corresponding 8 output bits. The total ROM size needed = 28 x 8 bits = 211 bits = 2 Kbits.
Hence option D is the answer.
Hence option D is the answer.
Question 8 |
In the following truth table, V = 1 if and only if the input is valid.
What function does the truth table represent?
Priority encoder | |
Decoder | |
Multiplexer | |
Demultiplexer |
Question 8 Explanation:
It is a 22 × 2 encoder. The inputs have priorities. So, it is a priority encoder.
Question 9 |
A clamp gate is an analog gate parametrized by two real numbers a and b, and denoted as clampa,b. It takes as input two non-negative real numbers x and y. Its output is defined as
Consider circuits composed only of clamp gates, possibly parametrized by different pairs (a, b) of real numbers. How many clamp gates are needed to construct a circuit that on input non-negative reals x and y outputs the maximum of x and y?
Consider circuits composed only of clamp gates, possibly parametrized by different pairs (a, b) of real numbers. How many clamp gates are needed to construct a circuit that on input non-negative reals x and y outputs the maximum of x and y?
1 | |
2 | |
3 | |
4 | |
No circuit composed only of clamp gates can compute the max function. |
Question 10 |
a | |
b | |
c | |
d | |
None of the above |
Question 11 |
Consider the following circuit
The function by the network above is
The function by the network above is
(AB)’E + EF + (CD)’F | |
(E’ + ABF’)(C+D+F’) | |
((AB)’+E)(E’+F’)(C+D+F’) | |
(A+B)E’ + (EF)’ + CDF’ |
Question 11 Explanation:
[ ((AB)’ E) + (EF) + (F(C+D)’) ]’
= ((AB)’ E)’ (EF)’ (F(C+D)’)’
= (AB+E’)(E’+F’)(F’+C+D)
= (ABE’ + ABF’ + E’ + E’F’)(F’+C+D)
= (ABF’+ E’(AB+1+F’))(F’+C+D)
= (ABF’+E’) (F’+C+D)
= ((AB)’ E)’ (EF)’ (F(C+D)’)’
= (AB+E’)(E’+F’)(F’+C+D)
= (ABE’ + ABF’ + E’ + E’F’)(F’+C+D)
= (ABF’+ E’(AB+1+F’))(F’+C+D)
= (ABF’+E’) (F’+C+D)
Question 12 |
Following Multiplexer circuits is equivalent to
Sum equation of full adder | |
Carry equation of full adder | |
Borrow equation for full subtraction | |
Difference equation of a full subtractor | |
Both A and D |
Question 12 Explanation:
The output Y of the given MUX is the equation for the difference of a full subtractor and Sum of a Full Adder.
Y is the difference between A and B where C is the Barrow.
Y is the Sum of A and B where C is the Carry_in.
Y = B’A’C + B’AC’ + BA’C’ + BAC
Y = (A ⊕ B ⊕ C)
Y is the difference between A and B where C is the Barrow.
Y is the Sum of A and B where C is the Carry_in.
Y = B’A’C + B’AC’ + BA’C’ + BAC
Y = (A ⊕ B ⊕ C)
Question 13 |
In a 8-bit ripple carry adder using identical full adders, each full adder takes 34ns for computing sum. If the time taken for 8-bit addition is 90ns, find the time taken by each full adDer to find carry.
6 ns | |
7 ns | |
10 ns | |
8 ns |
Question 13 Explanation:
Consider n-bit Ripple Carry Adder.
Total Delay = Delay_Sum + (n-1) Delay_Carry
Here, n=8.
90ns = 34 ns + 7 * Delay_Carry
56ns = 7 * Delay_Carry
Delay_Carry= 8ns
Total Delay = Delay_Sum + (n-1) Delay_Carry
Here, n=8.
90ns = 34 ns + 7 * Delay_Carry
56ns = 7 * Delay_Carry
Delay_Carry= 8ns
Question 14 |
The following circuit compares two 2-bit binary numbers, X and Y represented by X1X0 and Y1Y0 respectively. ( X0 and Y0 represent Least Significant Bids)
Under what condition Z will be 1?
Under what condition Z will be 1?
X > Y | |
X < Y | |
X = Y | |
X! = Y |
Question 14 Explanation:
Output of OR gate is 1 if at least one of the two inputs is1.
Case 1: X1=1 and Y1=0 which implies X > Y.
or Case 2: X1=Y1 and (X0=1 and Y0=0) which implies X > Y.
Z=1 in both of the above cases which implies X > Y.
Case 1: X1=1 and Y1=0 which implies X > Y.
or Case 2: X1=Y1 and (X0=1 and Y0=0) which implies X > Y.
Z=1 in both of the above cases which implies X > Y.
There are 14 questions to complete.