A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is _____.
A 25x1 Multiplexer with 5 select lines selects one of the 32(= 25) registers at a time depending on the selection input.
The content from the selected register will be transferred through the output line to the Accumulator.
If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m + n is ____.
Each output line of the decoder is connected to one of the 1K(= 1024) rows of RAM.
Each row stores 1 Byte.
m=10 and n=1024
P is 10:1 multiplexer; Q is 5:1 multiplexer; T is 2:1 multiplexer
P is 10:2 ^10 decoder; Q is 5:2^ 5 decoder; T is 2:1 encoder
P is 10:2^ 10 decoder; Q is 5:2^ 5 decoder; T is 2:1 multiplexer
P is 1:10 de-multiplexer; Q is 1:5 de-multiplexer; T is 2:1 multiplexer
Q is a 5:2^5 decoder that takes a 5-bit address from R-address as input and enable one of the 32 words of the R memory.
T is a 2x1 Multiplexer that select one of the 2 inputs and transmit it as output.
Optical encoders enable an angular displacement to be converted directly into a digital form.
Encoder resolution is often referred to in bits, which are binary units: a 16 bit resolution rotary encoder will have 65,536 (216) increments per turn, or PPR.
In the given question, 8-bit optical encoder will have 28 increments Resolution = 360/2n = 360/28 = 1.4o
D = AB + A’B , X = A’B
D = A’B + AB’ , X = AB’
D = A’B + AB’ , X = A’B
D = AB + A’B , X = AB’
A-B= D= A’B + AB’
What is the type of decoder required if the memory is built using 2K x 8 RAM chips?
5 to 32
6 to 64
4 to 64
7 to 128
We need to built memory with 4 byte words with a capacity of 221bits
So, number of 4-byte words memory = total number of bits / number of byte words
= 216 words
Given RAM chips are of size = 2K x 8
Memory to be built using these RAM chips = 216
Required RAM chips = (216 x 32) / (2K x 8) = 32 x 4
So, RAM chips contains 32 rows and each row with 4 columns.
A Decoder is required to select a specific row and multiplexer is required to select a particular column. 5 to 32 Decoder will be required to select the desired row.
Match the terms in List-I with the options given in List-II :
List-I List-II (a) Decoder (i) 1 line to 2n lines (b) Multiplexer (ii) n lines to 2n lines (c) De multiplexer (iii) 2n lines to 1 line (iv) 2n lines to 2n-1 lines
(a)-(ii), (b)-(i), (c)-(iii)
(a)-(ii), (b)-(iii), (c)-(i)
(a)-(ii), (b)-(i), (c)-(iv)
(a)-(iv), (b)-(ii), (c)-(i)
Multiplexer: Many to One
Demultiplexer: One to Many
f = A’B’C + A’B’C’
Assume that inputs are available only in true form and Boolean constant 1 and 0 are available.
So we can implement with minimum Two number of 2x1 multiplexers
xy + zx’+ wxy
xy +zx’ +yz
xy + zx’ +wz
→ Generally Hazard occurs due to different delays in different paths of the circuit.
→ In the expression xy +zx’ the variable x is in true form in one term(xy) and in complement in other term(zx').
→ Delay occurs due to the presence of NOT gate. If input xyz=111 then output is 1. If input xyz=011 then output stays momentarily in state 0 then settles in state 1.
→ Adding the term yz(select y from xy and z from zx') eliminates the hazard.
I. A circuit that adds two bits, producing a sum bit and a carry bit is called half adder.
II. A circuit that adds two bits, producing a sum bit and a carry bit is called full adder.
III. A circuit that adds two bits and a carry bit producing a sum bit and a carry bit is called full adder.
IV. A device that accepts the value of a Boolean variable as input and produces its complement is called an inverter.
I & II
II & III
I, II, III
I, III & IV
FALSE: A circuit that adds two bits, producing a sum bit and a carry bit is called full adder.
It is false because it is half adder
TRUE: A circuit that adds two bits and a carry bit producing a sum bit and a carry bit is called full adder.
TRUE: A device that accepts the value of a Boolean variable as input and produces its complement is called an inverter.
accepts one input and gives several output
accepts many inputs and gives many output
accepts many inputs and gives one output
accepts one input and gives one output
16 input MUX
8 input MUX
4 input MUX
2 input MUX
= 2n output lines.
= 16 output lines.
In order to provide 2 14 address lines we need 14 address lines and in order to provide 16 data lines we need 16 data lines.
Y= A+ B
Y = A | B
Y = A & B
Y = S ? A : B
A multiplexer can be used to implement if-else statements.
16 address lines, 7 data lines
7 address lines, 16 data lines
17 address lines, 16 data lines
16 address lines, 17 data lines
96 is greater than 64 and less than 128 ,So we need to consider 128.
96= 2x2x2x2x2x3 which is equivalent to 2 ^ 7
96K which is 2^7 x 2^10 =2^17
So address lines are 17
Word size is 16
So data lines are 2 ^16.
So option C is correct .
Under what condition Z will be 1?
X > Y
X < Y
X = Y
X! = Y
Case 1: X1=1 and Y1=0 which implies X > Y.
or Case 2: X1=Y1 and (X0=1 and Y0=0) which implies X > Y.
Z=1 in both of the above cases which implies X > Y.
Total Delay = Delay_Sum + (n-1) Delay_Carry
90ns = 34 ns + 7 * Delay_Carry
56ns = 7 * Delay_Carry
Sum equation of full adder
Carry equation of full adder
Borrow equation for full subtraction
Difference equation of a full subtractor
Both A and D
Y is the difference between A and B where C is the Barrow.
Y is the Sum of A and B where C is the Carry_in.
Y = B’A’C + B’AC’ + BA’C’ + BAC
Y = (A ⊕ B ⊕ C)
The function by the network above is
(AB)’E + EF + (CD)’F
(E’ + ABF’)(C+D+F’)
(A+B)E’ + (EF)’ + CDF’
= ((AB)’ E)’ (EF)’ (F(C+D)’)’
= (ABE’ + ABF’ + E’ + E’F’)(F’+C+D)
= (ABF’+ E’(AB+1+F’))(F’+C+D)
= (ABF’+E’) (F’+C+D)
8 half addres, 8 full adders
1 half adder, 15 full adders
16 half adders, 0 full adders
4 half adders, 12 full-adders
2n –input & I -output
1 –output & 2n output
2n-1 input & 1 output
2n+1 input & 1 output
The number of full and half adders required to add 16-bit numbers are
8 half adders, 8 full adders
1 half adder, 15 full adders
16 half adders, 0 full adders
half adders, 12 full adders
The number of control lines for a 8 to 1 multiplexer is
The gates required to build a half adder are
Ex-OR gate and NOR gate
Ex-OR gate and OR gate
Ex-OR gate and AND gate
Four NAND gates
In order to implement an n-variable switching function, a MUX must have
2n + inputs
2n – 1 inputs
7200+300n = 9600
300n = 9600-7200
X < Y
X ≥ Y
So from the above table we can clearly see that, for X>Y the value of Z is 1.
Consider circuits composed only of clamp gates, possibly parametrized by different pairs (a, b) of real numbers. How many clamp gates are needed to construct a circuit that on input non-negative reals x and y outputs the maximum of x and y?
No circuit composed only of clamp gates can compute the max function.