Question 1

A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is _____.

Question 1 Explanation: 
Number of registers is 32. Only one register has to be selected at any instant of time.
A 25x1 Multiplexer with 5 select lines selects one of the 32(= 25) registers at a time depending on the selection input.
The content from the selected register will be transferred through the output line to the Accumulator.
Question 2

If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m + n is ____.

Question 2 Explanation: 
The size of the decoder required is 10 x 210 i.e., 10 x 1024.
Each output line of the decoder is connected to one of the 1K(= 1024) rows of RAM.
Each row stores 1 Byte.
m=10 and n=1024
Question 3
Which one of the following circuits implements the Boolean function given below?
Question 3 Explanation: 
Question 4
Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16-bit code word is used to load a word in X, either from S or from R. S is a 1024-word memory segment and R is a 32-word register file. Based on the value of mode bit M, T selects an input word to load in X. P and Q interface with the corresponding bits in the code word to choose the addressed word. Which one of the following represents the functionality of P, Q, and T?
P is 10:1 multiplexer; Q is 5:1 multiplexer; T is 2:1 multiplexer
P is 10:2 ^10 decoder; Q is 5:2^ 5 decoder; T is 2:1 encoder
P is 10:2^ 10 decoder; Q is 5:2^ 5 decoder; T is 2:1 multiplexer
P is 1:10 de-multiplexer; Q is 1:5 de-multiplexer; T is 2:1 multiplexer
Question 4 Explanation: 
P is a 10:2^10 decoder that takes a 10-bit address from S-address as input and enable one of the 1024 words of the S memory.
Q is a 5:2^5 decoder that takes a 5-bit address from R-address as input and enable one of the 32 words of the R memory.
T is a 2x1 Multiplexer that select one of the 2 inputs and transmit it as output.
Question 5
Which of the following represents the function of a Multiplexer?
Y= A+ B
Y = A | B
Y = A & B
Y = S ? A : B
Question 5 Explanation: 
Multiplexer : It also known as a data selector, is a device that selects between several input signals and forwards it to a single output line. A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output. Here in fourth option “S” is used as select line to select either “A” or “B”.
A multiplexer can be used to implement if-else statements.
Question 6
Consider a memory unit of size 96k x 16, where first component represents the total number of words and that the second component represents the number of bits per word. What will be the number if address lines and input-output data lines?
16 address lines, 7 data lines
7 address lines, 16 data lines
17 address lines, 16 data lines
16 address lines, 17 data lines
Question 6 Explanation: 
Given memory unit is 96K x 16
96 is greater than 64 and less than 128 ,So we need to consider 128.
96= 2x2x2x2x2x3 which is equivalent to 2 ^ 7
96K which is 2^7 x 2^10 =2^17
So address lines are 17
Word size is 16
So data lines are 2 ^16.
So option C is correct .
Question 7

None of the above
Question 8
A clamp gate is an analog gate parametrized by two real numbers a and b, and denoted as clampa,b. It takes as input two non-negative real numbers x and y. Its output is defined as

Consider circuits composed only of clamp gates, possibly parametrized by different pairs (a, b) of real numbers. How many clamp gates are needed to construct a circuit that on input non-negative reals x and y outputs the maximum of x and y?
No circuit composed only of clamp gates can compute the max function.
Question 9
The following circuit compares two 2-bit binary numbers, X and Y represented by X1X0 and Y1Y0 respectively. ( X0 and Y0 represent Least Significant Bids)

Under what condition Z will be 1?
X > Y
X < Y
X = Y
X! = Y
Question 9 Explanation: 
Output of OR gate is 1 if at least one of the two inputs is1.
Case 1: X1=1 and Y1=0 which implies X > Y.
or Case 2: X1=Y1 and (X0=1 and Y0=0) which implies X > Y.
Z=1 in both of the above cases which implies X > Y.
There are 9 questions to complete.

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