CombinationalCircuit
Question 1 
A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is _____.
5 
Question 1 Explanation:
Number of registers is 32. Only one register has to be selected at any instant of time.
A 2^{5}x1 Multiplexer with 5 select lines selects one of the 32(= 2^{5}) registers at a time depending on the selection input.
The content from the selected register will be transferred through the output line to the Accumulator.
A 2^{5}x1 Multiplexer with 5 select lines selects one of the 32(= 2^{5}) registers at a time depending on the selection input.
The content from the selected register will be transferred through the output line to the Accumulator.
Question 2 
If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m + n is ____.
1034 
Question 2 Explanation:
The size of the decoder required is 10 x 2^{10} i.e., 10 x 1024.
Each output line of the decoder is connected to one of the 1K(= 1024) rows of RAM.
Each row stores 1 Byte.
m=10 and n=1024
Each output line of the decoder is connected to one of the 1K(= 1024) rows of RAM.
Each row stores 1 Byte.
m=10 and n=1024
Question 3 
Which one of the following circuits implements the Boolean function given below?
Question 3 Explanation:
Question 4 
Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16bit code word is used to load a word in X, either from S or from R. S is a 1024word memory segment and R is a 32word register file. Based on the value of mode bit M, T selects an input word to load in X. P and Q interface with the corresponding bits in the code word to choose the addressed word. Which one of the following represents the functionality of P, Q, and T?
P is 10:1 multiplexer; Q is 5:1 multiplexer; T is 2:1 multiplexer  
P is 10:2 ^10 decoder; Q is 5:2^ 5 decoder; T is 2:1 encoder  
P is 10:2^ 10 decoder; Q is 5:2^ 5 decoder; T is 2:1 multiplexer  
P is 1:10 demultiplexer; Q is 1:5 demultiplexer; T is 2:1 multiplexer 
Question 4 Explanation:
P is a 10:2^10 decoder that takes a 10bit address from Saddress as input and enable one of the 1024 words of the S memory.
Q is a 5:2^5 decoder that takes a 5bit address from Raddress as input and enable one of the 32 words of the R memory.
T is a 2x1 Multiplexer that select one of the 2 inputs and transmit it as output.
Q is a 5:2^5 decoder that takes a 5bit address from Raddress as input and enable one of the 32 words of the R memory.
T is a 2x1 Multiplexer that select one of the 2 inputs and transmit it as output.
Question 5 
The circuit shown in the given figure is a
full adder  
full subtractor  
shift register  
decade counter 
Question 5 Explanation:
The above diagram is full subtractor. The equation is D=X⊕Y⊕Bin and B_{out=X'Bin+X'Y+YBin}
Question 6 
By using an eightbit optical encoder the degree of resolution that can be obtained is (approximately)
1.8^{o}  
3.4^{o}  
2.8^{o}  
1.4^{o} 
Question 6 Explanation:
An optical encoder is an electromechanical device which has an electrical output in digital form proportional to the angular position of the input shaft.
Optical encoders enable an angular displacement to be converted directly into a digital form.
Encoder resolution is often referred to in bits, which are binary units: a 16 bit resolution rotary encoder will have 65,536 (216) increments per turn, or PPR.
In the given question, 8bit optical encoder will have 2^{8} increments Resolution = 360/2^{n} = 360/2^{8} = 1.4^{o}
Optical encoders enable an angular displacement to be converted directly into a digital form.
Encoder resolution is often referred to in bits, which are binary units: a 16 bit resolution rotary encoder will have 65,536 (216) increments per turn, or PPR.
In the given question, 8bit optical encoder will have 2^{8} increments Resolution = 360/2^{n} = 360/2^{8} = 1.4^{o}
Question 7 
For a binary halfsubtractor having two inputs A and B, the correct set of logical expressions for the outputs D (= A minus B) and X (=borrow) are
D = AB + A’B , X = A’B  
D = A’B + AB’ , X = AB’  
D = A’B + AB’ , X = A’B  
D = AB + A’B , X = AB’ 
Question 7 Explanation:
The function table for the Half Subtractor is as follows
AB= D= A’B + AB’
X= A’B
AB= D= A’B + AB’
X= A’B
Question 8 
Suppose you want to build a memory with 4byte words with a capacity of 2^{21} bits.
What is the type of decoder required if the memory is built using 2K x 8 RAM chips?
What is the type of decoder required if the memory is built using 2K x 8 RAM chips?
5 to 32  
6 to 64  
4 to 64  
7 to 128 
Question 8 Explanation:
In digital electronics, a binary decoder is a combinational logic circuit that converts binary information from the n coded inputs to a maximum of 2^{n} unique outputs.
We need to built memory with 4 byte words with a capacity of 221bits
So, number of 4byte words memory = total number of bits / number of byte words
= 2^{21}/(4*bytes)
= 2^{21}/(4*8)
=2^{21}/32=2^{21}/2^{5}
= 2^{16} words
Given RAM chips are of size = 2K x 8
Memory to be built using these RAM chips = 2^{16 Required RAM chips = (216 x 32) / (2K x 8) = 32 x 4 So, RAM chips contains 32 rows and each row with 4 columns. A Decoder is required to select a specific row and multiplexer is required to select a particular column. 5 to 32 Decoder will be required to select the desired row. }
We need to built memory with 4 byte words with a capacity of 221bits
So, number of 4byte words memory = total number of bits / number of byte words
= 2^{21}/(4*bytes)
= 2^{21}/(4*8)
=2^{21}/32=2^{21}/2^{5}
= 2^{16} words
Given RAM chips are of size = 2K x 8
Memory to be built using these RAM chips = 2^{16 Required RAM chips = (216 x 32) / (2K x 8) = 32 x 4 So, RAM chips contains 32 rows and each row with 4 columns. A Decoder is required to select a specific row and multiplexer is required to select a particular column. 5 to 32 Decoder will be required to select the desired row. }
Question 9 
Match the terms in ListI with the options given in ListII :
ListI ListII (a) Decoder (i) 1 line to 2^{n} lines (b) Multiplexer (ii) n lines to 2^{n} lines (c) De multiplexer (iii) 2^{n} lines to 1 line (iv) 2^{n} lines to 2^{n1} lines
(a)(ii), (b)(i), (c)(iii)  
(a)(ii), (b)(iii), (c)(i)  
(a)(ii), (b)(i), (c)(iv)  
(a)(iv), (b)(ii), (c)(i)

Question 9 Explanation:
Decoder:
Multiplexer: Many to One
Demultiplexer: One to Many
Multiplexer: Many to One
Demultiplexer: One to Many
Question 10 
Minimum number of 2x1 multiplexers required to realize the following function,
f = A’B’C + A’B’C’
Assume that inputs are available only in true form and Boolean constant 1 and 0 are available.
f = A’B’C + A’B’C’
Assume that inputs are available only in true form and Boolean constant 1 and 0 are available.
1  
2  
3  
7 
Question 10 Explanation:
Given function f = A’B’C + A’B’C’
=A’B’(C+C’) (C+C’=1)
=A’B’
=(A+B)’
So we can implement with minimum Two number of 2x1 multiplexers
=A’B’(C+C’) (C+C’=1)
=A’B’
=(A+B)’
So we can implement with minimum Two number of 2x1 multiplexers
Question 11 
A device which converts BCD to seven segment is called____
Encoder  
Decoder  
Decoder  
Demultiplexer 
Question 11 Explanation:
A Display Decoder is a combinational circuit which decodes and nbit input value into a number of output lines to drive a display
Question 12 
A halfadder is also known as :
AND Circuit  
NAND Circuit  
NOR Circuit  
EXOR Circuit 
Question 12 Explanation:
→ The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). The carry signal represents an overflow into the next digit of a multidigit addition. The value
of the sum is 2C + S. The simplest halfadder design incorporates an XOR gate for S and an AND gate for C. The Boolean logic for the sum (in this case S) will be A′B + AB′ whereas for the carry (C) will be AB.
Question 13 
Which of the following expression removes static hazard from a two level AND  OR gate implementation of xy +zx’
xy +zx’  
xy + zx’+ wxy  
xy +zx’ +yz  
xy + zx’ +wz 
Question 13 Explanation:
→ A static hazard occurs if a circuit produces incorrect output value momentarily before stabilizing to its correct value.
→ Generally Hazard occurs due to different delays in different paths of the circuit.
→ In the expression xy +zx’ the variable x is in true form in one term(xy) and in complement in other term(zx').
→ Delay occurs due to the presence of NOT gate. If input xyz=111 then output is 1. If input xyz=011 then output stays momentarily in state 0 then settles in state 1.
→ Adding the term yz(select y from xy and z from zx') eliminates the hazard.
→ Generally Hazard occurs due to different delays in different paths of the circuit.
→ In the expression xy +zx’ the variable x is in true form in one term(xy) and in complement in other term(zx').
→ Delay occurs due to the presence of NOT gate. If input xyz=111 then output is 1. If input xyz=011 then output stays momentarily in state 0 then settles in state 1.
→ Adding the term yz(select y from xy and z from zx') eliminates the hazard.
Question 14 
Which of the following statements are true ?
I. A circuit that adds two bits, producing a sum bit and a carry bit is called half adder.
II. A circuit that adds two bits, producing a sum bit and a carry bit is called full adder.
III. A circuit that adds two bits and a carry bit producing a sum bit and a carry bit is called full adder.
IV. A device that accepts the value of a Boolean variable as input and produces its complement is called an inverter.
I. A circuit that adds two bits, producing a sum bit and a carry bit is called half adder.
II. A circuit that adds two bits, producing a sum bit and a carry bit is called full adder.
III. A circuit that adds two bits and a carry bit producing a sum bit and a carry bit is called full adder.
IV. A device that accepts the value of a Boolean variable as input and produces its complement is called an inverter.
I & II  
II & III  
I, II, III  
I, III & IV 
Question 14 Explanation:
TRUE: A circuit that adds two bits, producing a sum bit and a carry bit is called half adder.
FALSE: A circuit that adds two bits, producing a sum bit and a carry bit is called full adder.
It is false because it is half adder
TRUE: A circuit that adds two bits and a carry bit producing a sum bit and a carry bit is called full adder.
TRUE: A device that accepts the value of a Boolean variable as input and produces its complement is called an inverter.
FALSE: A circuit that adds two bits, producing a sum bit and a carry bit is called full adder.
It is false because it is half adder
TRUE: A circuit that adds two bits and a carry bit producing a sum bit and a carry bit is called full adder.
TRUE: A device that accepts the value of a Boolean variable as input and produces its complement is called an inverter.
Question 15 
A multiplexer is a logic circuit that
accepts one input and gives several output  
accepts many inputs and gives many output  
accepts many inputs and gives one output  
accepts one input and gives one output 
Question 15 Explanation:
A multiplexer is a logic circuit that accepts many inputs and gives one output.
Demultiplex is just reverse of it.
Question 16 
In order to implement a n variable switching function, a MUX must have :
2^{n} inputs  
2^{n}+1 inputs  
2^{n1} inputs  
2^{n}1 inputs 
Question 16 Explanation:
In order to implement a n variable switching function, a MUX must have 2^{n} inputs.
Question 17 
If four 4 input multiplexers drive a 4 input multiplexer, we get a :
16 input MUX  
8 input MUX  
4 input MUX  
2 input MUX 
Question 17 Explanation:
If ‘n’ input lines, it will generate 2^{n} output lines.
Given, n=4
= 2^{n} output lines.
= 2^{4}
= 16 output lines.
Given, n=4
= 2^{n} output lines.
= 2^{4}
= 16 output lines.
Question 18 
The output of the following combinational circuit.
X.Y  
X+Y  
X⊕Y  
(X⊕Y)’ 
Question 18 Explanation:
Question 19 
The three outputs x_{1}x_{2}x_{3} from the 8 X 3 priority encoder are used to provide a vector address of the form 101x_{1}x_{2}x_{3}00. What is the second highest priority vector address in hexadecimal if the vector addresses are starting from the one with the highest priority ?
BC  
A4  
BD  
AC 
Question 19 Explanation:
Question 20 
How many address lines and data lines are required to provide a memory capacity of 16K x 16?
10,4  
16,16  
14,16  
4,16 
Question 20 Explanation:
16K x 16 means we have 2 ^{14} address lines and 16 data lines.
In order to provide 2 ^{14} address lines we need 14 address lines and in order to provide 16 data lines we need 16 data lines.
In order to provide 2 ^{14} address lines we need 14 address lines and in order to provide 16 data lines we need 16 data lines.
Question 21 
The parallel bus arbitration technique uses an external priority encoder and a decoder. Suppose, a parallel arbiter has 5 bus arbiters. What will be the size of priority encoder and decoder respectively?
4x2, 2x4
 
2x4, 4x2  
3x8, 8x3  
8x3, 3x8 
Question 21 Explanation:
Question 22 
Which of the following represents the function of a Multiplexer?
Y= A+ B  
Y = A  B  
Y = A & B  
Y = S ? A : B 
Question 22 Explanation:
Multiplexer : It also known as a data selector, is a device that selects between several input signals and forwards it to a single output line. A multiplexer of 2^{n }inputs has n select lines, which are used to select which input line to send to the output. Here in fourth option “S” is used as select line to select either “A” or “B”.
A multiplexer can be used to implement ifelse statements.
A multiplexer can be used to implement ifelse statements.
Question 23 
Consider a memory unit of size 96k x 16, where first component represents the total number of words and that the second component represents the number of bits per word. What will be the number if address lines and inputoutput data lines?
16 address lines, 7 data lines  
7 address lines, 16 data lines  
17 address lines, 16 data lines  
16 address lines, 17 data lines 
Question 23 Explanation:
Given memory unit is 96K x 16
96 is greater than 64 and less than 128 ,So we need to consider 128.
96= 2x2x2x2x2x3 which is equivalent to 2 ^ 7
96K which is 2^7 x 2^10 =2^17
So address lines are 17
Word size is 16
So data lines are 2 ^16.
So option C is correct .
96 is greater than 64 and less than 128 ,So we need to consider 128.
96= 2x2x2x2x2x3 which is equivalent to 2 ^ 7
96K which is 2^7 x 2^10 =2^17
So address lines are 17
Word size is 16
So data lines are 2 ^16.
So option C is correct .
Question 24 
The following circuit compares two 2bit binary numbers, X and Y represented by X_{1}X_{0} and Y_{1}Y_{0 }respectively. ( X_{0} and Y_{0} represent Least Significant Bids)
Under what condition Z will be 1?
Under what condition Z will be 1?
X > Y  
X < Y  
X = Y  
X! = Y 
Question 24 Explanation:
Output of OR gate is 1 if at least one of the two inputs is1.
Case 1: X_{1}=1 and Y_{1}=0 which implies X > Y.
or Case 2: X_{1}=Y_{1} and (X_{0}=1 and Y_{0}=0) which implies X > Y.
Z=1 in both of the above cases which implies X > Y.
Case 1: X_{1}=1 and Y_{1}=0 which implies X > Y.
or Case 2: X_{1}=Y_{1} and (X_{0}=1 and Y_{0}=0) which implies X > Y.
Z=1 in both of the above cases which implies X > Y.
Question 25 
In a 8bit ripple carry adder using identical full adders, each full adder takes 34ns for computing sum. If the time taken for 8bit addition is 90ns, find the time taken by each full adDer to find carry.
6 ns  
7 ns  
10 ns  
8 ns 
Question 25 Explanation:
Consider nbit Ripple Carry Adder.
Total Delay = Delay_Sum + (n1) Delay_Carry
Here, n=8.
90ns = 34 ns + 7 * Delay_Carry
56ns = 7 * Delay_Carry
Delay_Carry= 8ns
Total Delay = Delay_Sum + (n1) Delay_Carry
Here, n=8.
90ns = 34 ns + 7 * Delay_Carry
56ns = 7 * Delay_Carry
Delay_Carry= 8ns
Question 26 
Following Multiplexer circuits is equivalent to
Sum equation of full adder  
Carry equation of full adder  
Borrow equation for full subtraction  
Difference equation of a full subtractor  
Both A and D 
Question 26 Explanation:
The output Y of the given MUX is the equation for the difference of a full subtractor and Sum of a Full Adder.
Y is the difference between A and B where C is the Barrow.
Y is the Sum of A and B where C is the Carry_in.
Y = B’A’C + B’AC’ + BA’C’ + BAC
Y = (A ⊕ B ⊕ C)
Y is the difference between A and B where C is the Barrow.
Y is the Sum of A and B where C is the Carry_in.
Y = B’A’C + B’AC’ + BA’C’ + BAC
Y = (A ⊕ B ⊕ C)
Question 27 
Consider the following circuit
The function by the network above is
The function by the network above is
(AB)’E + EF + (CD)’F  
(E’ + ABF’)(C+D+F’)  
((AB)’+E)(E’+F’)(C+D+F’)  
(A+B)E’ + (EF)’ + CDF’ 
Question 27 Explanation:
[ ((AB)’ E) + (EF) + (F(C+D)’) ]’
= ((AB)’ E)’ (EF)’ (F(C+D)’)’
= (AB+E’)(E’+F’)(F’+C+D)
= (ABE’ + ABF’ + E’ + E’F’)(F’+C+D)
= (ABF’+ E’(AB+1+F’))(F’+C+D)
= (ABF’+E’) (F’+C+D)
= ((AB)’ E)’ (EF)’ (F(C+D)’)’
= (AB+E’)(E’+F’)(F’+C+D)
= (ABE’ + ABF’ + E’ + E’F’)(F’+C+D)
= (ABF’+ E’(AB+1+F’))(F’+C+D)
= (ABF’+E’) (F’+C+D)
Question 28 
The number of full and half adders required to add 16 – bit number is
8 half addres, 8 full adders  
1 half adder, 15 full adders
 
16 half adders, 0 full adders  
4 half adders, 12 fulladders 
Question 28 Explanation:
Question 29 
Consider the implementation of a Boolean function of ‘n’ variables using only one multiplexer and one inverter. The minimum specification of size of multiplexer required is ____________
2^{n} –input & I output  
1 –output & 2^{n} output  
2^{n1} input & 1 output  
2^{n+1} input & 1 output 
Question 29 Explanation:
The minimum specification of size of multiplexer required is 2^(n1) input & 1 output in which n1 variables will be given to n1 select lines and remaining one variable will be given to input lines.
Question 30 
The number of full and half adders required to add 16bit numbers are
8 half adders, 8 full adders  
1 half adder, 15 full adders  
16 half adders, 0 full adders  
half adders, 12 full adders

Question 30 Explanation:
For the first 15 bits we need 15 full adders and for LSB we need 1 half adder.
Question 31 
The number of control lines for a 8 to 1 multiplexer is
2  
3  
4  
5 
Question 31 Explanation:
No. of control lines for 8 to 1 multiplexer is log_{2} 8 = 3.
Question 32 
The gates required to build a half adder are
ExOR gate and NOR gate  
ExOR gate and OR gate  
ExOR gate and AND gate  
Four NAND gates 
Question 32 Explanation:
In half adder for sum value we need 1 XOR gate and for carry value we need 1 AND gate.
Question 33 
In order to implement an nvariable switching function, a MUX must have
2^{n} inputs  
2^{n} + inputs  
2^{n1} inputs
 
2^{n} – 1 inputs 
Question 33 Explanation:
In order to implement an nvariable switching function, a MUX must have 2^{n1} inputs, where we can give n1 variables and remaining 1 we can give to the select lines.
Question 34 
A terminal multiplexer has six 1200 bps terminals and ‘n’ 300 bps terminals connected to it. If the outgoing line is 9600 bps, what is the value of n ?
4  
8  
16  
28 
Question 34 Explanation:
According to given data,
(6*1200)+(n*300)= 9600
7200+300n = 9600
300n = 96007200
300n= 2400
n= 8
(6*1200)+(n*300)= 9600
7200+300n = 9600
300n = 96007200
300n= 2400
n= 8
Question 35 
The logic circuit given below is used to compare two unsigned 2bit numbers, X_{1}X_{0 }= X and
Y_{1} Y_{0} = Y, where X_{o} and Y_{o }are the least significant bits. (A small circle on any line in a logic
diagram indicates logical NOT). Which of the following always makes the output Z have the
value 1?
X >Y  
X < Y  
X =Y  
X ≥ Y

Question 35 Explanation:
So from the above table we can clearly see that, for X>Y the value of Z is 1.
Question 37 
A clamp gate is an analog gate parametrized by two real numbers a and b, and denoted as clamp_{a,b}. It takes as input two nonnegative real numbers x and y. Its output is defined as
Consider circuits composed only of clamp gates, possibly parametrized by different pairs (a, b) of real numbers. How many clamp gates are needed to construct a circuit that on input nonnegative reals x and y outputs the maximum of x and y?
Consider circuits composed only of clamp gates, possibly parametrized by different pairs (a, b) of real numbers. How many clamp gates are needed to construct a circuit that on input nonnegative reals x and y outputs the maximum of x and y?
1  
2  
3  
4  
No circuit composed only of clamp gates can compute the max function. 
Question 38 
Encoders are made by three ______ gates.
AND  
OR  
NAND  
XOR 
Question 38 Explanation:
Encoders are made by three OR gates
Encoder may also be designed by using 3 NAND gates. Thus both option B,C are correct.
Encoder may also be designed by using 3 NAND gates. Thus both option B,C are correct.
There are 38 questions to complete.