Consider the following data path of a simple non-pilelined CPU. The registers A, B, A₁, A₂, MDR, the bus and the ALU are 8-bit wide. SP and MAR are 16-bit registers. The MUX is of size 8 × (2:1) and the DEMUX is of size 8 × (1:2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally.

The CPU instruction “push r”, where = A or B, has the specification

     M [SP] ← r
     SP ← SP - 1

How many CPU clock cycles are needed to execute the “push r” instruction?

Consider the following assembly language program for a hypothetical processor. A, B, and C are 8 bit registers. The meanings of various instructions are shown as comments.

     MOV B, # 0   	;   B ← 0
     MOV C, # 8	        ;   C ← 8
Z :  CMP C, # 0	        ;   compare C with 0
     JZX	        ;   jump to X if zero flag is set
     SUB C, # 1	        ;   C ← C - 1
     RRC A, # 1 	;   right rotate A through carry by one bit. Thus:
                        ;   if the initial values of A and the carry flag are a7...a0 and
                        ;   c0 respectively, their values after the execution of this
                        ;   instruction will be c0a7...a1 and a0 respectively.
     JC Y	        ;   jump to Y if carry flag is set
     JMP Z	        ;   jump to Z
Y :  ADD B, # 1	        ;   B ← B + 1
     JMP Z	        ;   jump to Z
X :	

If the initial value of register A is A₀ the value of register B after the program execution will be

Consider the following assembly language program for a hypothetical processor. A, B, and C are 8 bit registers. The meanings of various instructions are shown as comments.

     MOV B, # 0   	;   B ← 0
     MOV C, # 8	        ;   C ← 8
Z :  CMP C, # 0	        ;   compare C with 0
     JZX	        ;   jump to X if zero flag is set
     SUB C, # 1	        ;   C ← C - 1
     RRC A, # 1 	;   right rotate A through carry by one bit. Thus:
                        ;   if the initial values of A and the carry flag are a7...a0 and
                        ;   c0 respectively, their values after the execution of this
                        ;   instruction will be c0a7...a1 and a0 respectively.
     JC Y	        ;   jump to Y if carry flag is set
     JMP Z	        ;   jump to Z
Y :  ADD B, # 1	        ;   B ← B + 1
     JMP Z	        ;   jump to Z
X :	

Which of the following instructions when inserted at location X will ensure that the value of register A after program execution is the same as its initial value?

Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.

 Instruction 	     Operation 	      Instruction Size(in words)
 MOV R1,5000; 	 ;R1 ← Memory[5000] 	         2
 MOV R2(R1); 	 ;R2 ← Memory[(R1)] 	         1
 ADD R2,R3; 	 ;R2 ← R2 + R3 	                 1
 MOV 6000,R2; 	 ;Memory[6000] ← R2 	         2
 HALT 	         ;Machine halts 	         1 

Consider that the memory is byte addressable with size 32 bits, and the program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be

Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.

 Instruction 	     Operation 	      Instruction Size(in words)
 MOV R1,5000; 	 ;R1 ← Memory[5000] 	         2
 MOV R2(R1); 	 ;R2 ← Memory[(R1)] 	         1
 ADD R2,R3; 	 ;R2 ← R2 + R3 	                 1
 MOV 6000,R2; 	 ;Memory[6000] ← R2 	         2
 HALT 	         ;Machine halts 	         1 

Let the clock cycles required for various operations be as follows:

Register to/ from memory transfer     : 3 clock cycles 
ADD with both operands in register    : 1 clock cycle 
Instruction fetch and decode          : 2 clock cycles per word  

The total number of clock cycles required to execute the program is

The memory locations 1000, 1001 and 1020 have data values 18, 1 and 16 respectively before the following program is executed.

MOVI Rs, 1        ; Move immediate
LOAD Rd, 1000(Rs) ; Load from memory
ADDI Rd, 1000     ; Add immediate
STOREI 0(Rd), 20  ; Store immediate 

Which of the statements below is TRUE after the program is executed?

Load R1,Loc1;	 Load R1 from memory location Loc1
Load R2,Loc2;	 Load R2 from memory location Loc2
Add R1,R2,R1;	 Add R1 and R2 and save result in R1
Dec R2;	         Decrement R2
Dec R1;	         Decrement R1
Mpy R1,R2,R3;	 Multiply R1 and R2 and save result in R3
Store R3,Loc3;   Store R3 in memory location Loc3

Assume that EA = (X)+ is the effective address equal to the contents of location X, with X incremented by one word length after the effective address is calculated; EA = −(X) is the effective address equal to the contents of location X, with X decremented by one word length before the effective address is calculated; EA = (X)− is the effective address equal to the contents of location X, with X decremented by one word length after the effective address is calculated. The format of the instruction is (opcode, source, destination), which means (destination ← source op destination). Using X as a stack pointer, which of the following instructions can pop the top two elements from the stack, perform the addition operation and push the result back to the stack.

Consider a three word machine instruction

ADD A[R0], @B

The first operand (destination) "A[R0]" uses indexed addressing mode with R0 as the index register. The second operand (source) "@B" uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is

Consider the following data path of a CPU.

The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR.

The instruction "add R0, R1" has the register transfer interpretation R0 <= R0+R1. The minimum number of clock cycles needed for execution cycle of this instruction is:

Consider the following data path of a CPU.

The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR.

The instruction "call Rn, sub" is a two word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is

      Rn <= PC + 1;
      PC <= M[PC]; 

The minimum number of CPU clock cycles needed during the execution cycle of this instruction is:

Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the main memory is implemented from memory location (0100)₁₆ and it grows upward. The stack pointer (SP) points to the top element of the stack. The current value of SP is (016E)₁₆. The CALL instruction is of two words, the first word is the op-code and the second word is the starting address of the subroutine (one word = 2 bytes). The CALL instruction is implemented as follows:

• Store the current value of PC in the stack.
• Store the value of PSW register in the stack.
• Load the starting address of the subroutine in PC.

The content of PC just before the fetch of a CALL instruction is (5FA0)₁₆. After execution of the CALL instruction, the value of the stack pointer is