A processor has 16 integer registers (R0, R1, …, R15) and 64 floating point registers (F0, F1, …, F63). It uses a 2-byte instruction format. There are four categories of instructions: Type-1, Type-2, Type-3 and Type-4. Type-1 category consists of four instructions, each with 3 integer register operands (3Rs). Type-2 category consists of eight instructions, each with 2 floating point register operands (2Fs). Type-3 category consists of fourteen instructions, each with one integer register operand and one floating point register operand (1R+1F). Type-4 category consists of N instructions, each with a floating point register operand (1F).

The maximum value of N is ________.

A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit instruction word has an opcode, two register operands and an immediate operand. The number of bits available for the immediate operand field is __________.

Consider a processor with 64 registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register r identifier, and a twelve-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. If a program has 100 instructions, the amount of memory (in bytes) consumed by the program text is _________.

For computers based on three-address instruction formats, each address field can be used to specify which of the following:

(S1) A memory operand
(S2) A processor register
(S3) An implied accumulator register

Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the main memory is implemented from memory location (0100)₁₆ and it grows upward. The stack pointer (SP) points to the top element of the stack. The current value of SP is (016E)₁₆. The CALL instruction is of two words, the first word is the op-code and the second word is the starting address of the subroutine (one word = 2 bytes). The CALL instruction is implemented as follows:

• Store the current value of PC in the stack.
• Store the value of PSW register in the stack.
• Load the starting address of the subroutine in PC.

The content of PC just before the fetch of a CALL instruction is (5FA0)₁₆. After execution of the CALL instruction, the value of the stack pointer is

A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ________.

Consider a hypothetical processor with an instruction of type LW R1, 20 (R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand memory?

Which of the following must be true for the RFE (Return From Exception) instruction on a general purpose processor?

I. It must be a trap instruction
II. It must be a privileged instruction
III. An exception cannot be allowed to occur during execution of an RFE instruction

In a simplified computer the instructions are:

  OP Rj,Ri - Performs Rj OP Ri and stores the result in register Ri. 
  OP m,Ri  - Performs val OP Ri and stores the result in Ri. val denotes the content of memory location m.
  MOV m,Ri - Moves the content of memory location m to register Ri.
  MOV Ri,m - Moves the content of register Ri to memory location m.

The computer has only to registers, and OP is either ADD or SUB. Consider the following basic block:

  t1 = a+b
  t2 = c+d
  t3 = e-t2
  t4 = t1-t3 

Assume that all operands are initially in memory. The final value of the computation should be in memory. What is the minimum number of MOV instructions in the code generated for this basic block?

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

       Instruction      Operation     Instruction size (no. of words)
       MOV R1,(3000)   R1 ← m[3000]                2
 LOOP: MOV R2,(R3)     R2 ← M[R3]                  1
       ADD R2,R1       R2 ← R1 + R2                1
       MOV (R3),R2     M[R3] ← R2                  1
       INC R3          R3 ← R3 + 1                 1
       DEC R1          R1 ← R1 - 1                 1
       BNZ LOOP        Branch on not zero          2
       HALT            Stop                        1 

Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal.

Assume that the memory is word addressable. The number of memory references for accessing the data in executing the program completely is:

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

       Instruction      Operation     Instruction size (no. of words)
       MOV R1,(3000)   R1 ← m[3000]                2
 LOOP: MOV R2,(R3)     R2 ← M[R3]                  1
       ADD R2,R1       R2 ← R1 + R2                1
       MOV (R3),R2     M[R3] ← R2                  1
       INC R3          R3 ← R3 + 1                 1
       DEC R1          R1 ← R1 - 1                 1
       BNZ LOOP        Branch on not zero          2
       HALT            Stop                        1 

Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal.

Assume that the memory is word addressable. After the execution of this program, the content of memory location 2010 is:

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

       Instruction      Operation     Instruction size (no. of words)
       MOV R1,(3000)   R1 ← m[3000]                2
 LOOP: MOV R2,(R3)     R2 ← M[R3]                  1
       ADD R2,R1       R2 ← R1 + R2                1
       MOV (R3),R2     M[R3] ← R2                  1
       INC R3          R3 ← R3 + 1                 1
       DEC R1          R1 ← R1 - 1                 1
       BNZ LOOP        Branch on not zero          2
       HALT            Stop                        1 

Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal.

Assume that the memory is byte addressable and the word size is 32 bits. If an interrupt occurs during the execution of the instruction “INC R3”, what return address will be pushed on to the stack?

A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)?

Consider a new instruction named branch-on-bit-set (mnemonic bbs). The instruction “bbs reg, pos, label” jumps to label if bit in position pos of register operand reg is one. A register is 32 bits wide and the bits are numbered 0 to 31, bit in position 0 being the least significant. Consider the following emulation of this instruction on a processor that does not have bbs implemented.

temp ← reg & mask 
Branch to label if temp is non-zero. 

The variable temp is a temporary register. For correct emulation, the variable mask must be generated by:

Consider a three word machine instruction

ADD A[R0], @B

The first operand (destination) "A[R0]" uses indexed addressing mode with R0 as the index register. The second operand (source) "@B" uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is

Consider the following data path of a CPU.

The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR.

The instruction "add R0, R1" has the register transfer interpretation R0 <= R0+R1. The minimum number of clock cycles needed for execution cycle of this instruction is:

Consider the following data path of a CPU.

The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR.

The instruction "call Rn, sub" is a two word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is

      Rn <= PC + 1;
      PC <= M[PC]; 

The minimum number of CPU clock cycles needed during the execution cycle of this instruction is:

Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.

 Instruction 	     Operation 	      Instruction Size(in words)
 MOV R1,5000; 	 ;R1 ← Memory[5000] 	         2
 MOV R2(R1); 	 ;R2 ← Memory[(R1)] 	         1
 ADD R2,R3; 	 ;R2 ← R2 + R3 	                 1
 MOV 6000,R2; 	 ;Memory[6000] ← R2 	         2
 HALT 	         ;Machine halts 	         1 

Consider that the memory is byte addressable with size 32 bits, and the program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be

Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.

 Instruction 	     Operation 	      Instruction Size(in words)
 MOV R1,5000; 	 ;R1 ← Memory[5000] 	         2
 MOV R2(R1); 	 ;R2 ← Memory[(R1)] 	         1
 ADD R2,R3; 	 ;R2 ← R2 + R3 	                 1
 MOV 6000,R2; 	 ;Memory[6000] ← R2 	         2
 HALT 	         ;Machine halts 	         1 

Let the clock cycles required for various operations be as follows:

Register to/ from memory transfer     : 3 clock cycles 
ADD with both operands in register    : 1 clock cycle 
Instruction fetch and decode          : 2 clock cycles per word  

The total number of clock cycles required to execute the program is

Consider the following assembly language program for a hypothetical processor. A, B, and C are 8 bit registers. The meanings of various instructions are shown as comments.

     MOV B, # 0   	;   B ← 0
     MOV C, # 8	        ;   C ← 8
Z :  CMP C, # 0	        ;   compare C with 0
     JZX	        ;   jump to X if zero flag is set
     SUB C, # 1	        ;   C ← C - 1
     RRC A, # 1 	;   right rotate A through carry by one bit. Thus:
                        ;   if the initial values of A and the carry flag are a7...a0 and
                        ;   c0 respectively, their values after the execution of this
                        ;   instruction will be c0a7...a1 and a0 respectively.
     JC Y	        ;   jump to Y if carry flag is set
     JMP Z	        ;   jump to Z
Y :  ADD B, # 1	        ;   B ← B + 1
     JMP Z	        ;   jump to Z
X :	

If the initial value of register A is A₀ the value of register B after the program execution will be

Consider the following assembly language program for a hypothetical processor. A, B, and C are 8 bit registers. The meanings of various instructions are shown as comments.

     MOV B, # 0   	;   B ← 0
     MOV C, # 8	        ;   C ← 8
Z :  CMP C, # 0	        ;   compare C with 0
     JZX	        ;   jump to X if zero flag is set
     SUB C, # 1	        ;   C ← C - 1
     RRC A, # 1 	;   right rotate A through carry by one bit. Thus:
                        ;   if the initial values of A and the carry flag are a7...a0 and
                        ;   c0 respectively, their values after the execution of this
                        ;   instruction will be c0a7...a1 and a0 respectively.
     JC Y	        ;   jump to Y if carry flag is set
     JMP Z	        ;   jump to Z
Y :  ADD B, # 1	        ;   B ← B + 1
     JMP Z	        ;   jump to Z
X :	

Which of the following instructions when inserted at location X will ensure that the value of register A after program execution is the same as its initial value?

Consider the following data path of a simple non-pilelined CPU. The registers A, B, A₁, A₂, MDR, the bus and the ALU are 8-bit wide. SP and MAR are 16-bit registers. The MUX is of size 8 × (2:1) and the DEMUX is of size 8 × (1:2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally.

The CPU instruction “push r”, where = A or B, has the specification

     M [SP] ← r
     SP ← SP - 1

How many CPU clock cycles are needed to execute the “push r” instruction?

Assume that EA = (X)+ is the effective address equal to the contents of location X, with X incremented by one word length after the effective address is calculated; EA = −(X) is the effective address equal to the contents of location X, with X decremented by one word length before the effective address is calculated; EA = (X)− is the effective address equal to the contents of location X, with X decremented by one word length after the effective address is calculated. The format of the instruction is (opcode, source, destination), which means (destination ← source op destination). Using X as a stack pointer, which of the following instructions can pop the top two elements from the stack, perform the addition operation and push the result back to the stack.

Following table indicates the latencies of operations between the instruction producing the result and instruction using the result.

Consider the following code segment.

Load R1,Loc1;	 Load R1 from memory location Loc1
Load R2,Loc2;	 Load R2 from memory location Loc2
Add R1,R2,R1;	 Add R1 and R2 and save result in R1
Dec R2;	         Decrement R2
Dec R1;	         Decrement R1
Mpy R1,R2,R3;	 Multiply R1 and R2 and save result in R3
Store R3,Loc3;   Store R3 in memory location Loc3