## Machine-Instructions

 Question 1

A processor has 16 integer registers (R0, R1, …, R15) and 64 floating point registers (F0, F1, …, F63). It uses a 2-byte instruction format. There are four categories of instructions: Type-1, Type-2, Type-3 and Type-4. Type-1 category consists of four instructions, each with 3 integer register operands (3Rs). Type-2 category consists of eight instructions, each with 2 floating point register operands (2Fs). Type-3 category consists of fourteen instructions, each with one integer register operand and one floating point register operand (1R+1F). Type-4 category consists of N instructions, each with a floating point register operand (1F).

The maximum value of N is ________.

 A 32 B 33 C 34 D 35
Computer-Organization       Machine-Instructions       GATE 2018
Question 1 Explanation:
Instruction size = 2−byte.
So, total number of instruction encodings = 216
There are 16 possible integer registers, so no. of bits required for an integer operand = 4
There are 64 possible floating point registers, so no. of bits required for a floating point operand = 6
Type-1 instructions:
There are 4 type-1 instructions and each takes 3 integer operands.
No. of encodings consumed by type-1 = 4 × 24 × 24 × 24 = 214.
Type-2 instructions:
There are 8 type-2 instructions and each takes 2 floating point operands.
No. of encodings consumed by Type-2 instructions = 8 × 26 x 26 = 215.
Type-3 instructions:
There are 14 type-3 instructions and each takes one integer operand and one floating point operand.
No. of encodings consumed by Type-3 instructions = 14 × 24 × 26 = 14336.
So, no. of encodings left for Type-4 = 216 − (214 + 215 + 14336) = 2048.
Since type-4 instructions take one floating point register, no. of different instructions of Type-4 = 2048 / 64 = 32.
 Question 2

A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit instruction word has an opcode, two register operands and an immediate operand. The number of bits available for the immediate operand ﬁeld is __________.

 A 16 bits B 17 bits C 18 bits D 19 bits
Computer-Organization       Machine-Instructions       GATE 2016 [Set-2]
Question 2 Explanation:
6 bits are needed for 40 distinct instructions (because, 25 < 40 < 26)
5 bits are needed for 24 general purpose registers (because, 24 < 24 < 25)
32-bit instruction word has an opcode (6 bit), two register operands (total 10 bits) and an immediate operand (x bits).
The number of bits available for the immediate operand field
⇒ x = 32 – (6 + 10) = 16 bits
 Question 3

Consider a processor with 64 registers and an instruction set of size twelve. Each instruction has ﬁve distinct ﬁelds, namely, opcode, two source register identiﬁers, one destination register r identiﬁer, and a twelve-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. If a program has 100 instructions, the amount of memory (in bytes) consumed by the program text is _________.

 A 500 bytes B 501 bytes C 502 bytes D 503 bytes
Computer-Organization       Machine-Instructions       GATE 2016 [Set-2]
Question 3 Explanation:
One instruction is divided into five parts,
(i) The opcode- As we have instruction set of size 12, an instruction opcode can be identified by 4 bits, as 24 = 16 and we cannot go any less.
(ii) & (iii) Two source register identifiers- As there are total 64 registers, they can be identified by 6 bits. As they are two i.e. 6 bit + 6 bit.
iv) One destination register identifier- Again it will be 6 bits.
v) A twelve bit immediate value- 12 bit.
Adding them all we get,
4 + 6 + 6 + 6 + 12 = 34 bit = 34/8 byte = 4.25 bytes.
Due to byte alignment total bytes per instruction = 5 bytes.
As there are 100 instructions, total size = 5*100 = 500 Bytes.
 Question 4

For computers based on three-address instruction formats, each address field can be used to specify which of the following:

(S1) A memory operand
(S2) A processor register
(S3) An implied accumulator register
 A Either S1 or S2 B Either S2 or S3 C Only S2 and S3 D All of S1, S2 and S3
Computer-Organization       Machine-Instructions       GATE 2015 [Set-1]
Question 4 Explanation:
Any implied register is never explicitly mentioned as an operand in an operation.
So as the question asks what can be specified using the address fields, implied accumulator register can't be represented in address field.
So, S3 is wrong.
Hence Option A is the correct answer.
 Question 5

Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the main memory is implemented from memory location (0100)16 and it grows upward. The stack pointer (SP) points to the top element of the stack. The current value of SP is (016E)16. The CALL instruction is of two words, the first word is the op-code and the second word is the starting address of the subroutine (one word = 2 bytes). The CALL instruction is implemented as follows:

• Store the current value of PC in the stack.
• Store the value of PSW register in the stack.
• Load the starting address of the subroutine in PC.

The content of PC just before the fetch of a CALL instruction is (5FA0)16. After execution of the CALL instruction, the value of the stack pointer is

 A (016A)16 B (016C)16 C (0170)16 D (0172)16
Computer-Organization       Machine-Instructions       GATE 2015 [Set-2]
Question 5 Explanation:
Here the memory is byte-addressable.
The CALL instruction is implemented as follows:
-Store the current value of PC in the stack
pc is 2 bytes so when we store pc in stack SP is increased by 2 so current value of SP is (016E)16+2 -Store the value of PSW register in the stack
psw is 2 bytes, so when we store psw in stack SP is increased by 2
so current value of SP is (016E)16+2+2 = (0172)16
 Question 6

A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ________.

 A 16383 B 16384 C 16385 D 16386
Computer-Organization       Machine-Instructions       GATE 2014 [Set-1]
Question 6 Explanation:
1 Word = 32 bits
Each instruction has 32 bits.
To support 45 instructions, opcode must contain 6-bits.
Register operand1 requires 6 bits, since the total registers are 64.
Register operand 2 also requires 6 bits 14-bits are left over for immediate Operand using 14-bits, we can give maximum 16383, Since 214 = 16384 (from 0 to 16383)
 Question 7

Consider a hypothetical processor with an instruction of type LW R1, 20 (R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand memory?

 A Immediate Addressing B Register Addressing C Register Indirect Scaled Addressing D Base Indexed Addressing
Computer-Organization       Machine-Instructions       GATE 2011
Question 7 Explanation:
Here 20 will act as base and content of R2 will be index.
 Question 8

Which of the following must be true for the RFE (Return From Exception) instruction on a general purpose processor?

I. It must be a trap instruction
II. It must be a privileged instruction
III. An exception cannot be allowed to occur during execution of an RFE instruction
 A I only B II only C I and II only D I, II and III only
Computer-Organization       Machine-Instructions       GATE 2008
Question 8 Explanation:
RFE is a privileged instruction that is performed explicitly by the Operating System to switch from kernel mode to user mode at the end of handling an exception. Hence it has to be a trap. We know when a trap/interrupt is in execution, till its completion all other trap/interrupts will not be allowed to execute. So option D is correct answer.
 Question 9

In a simplified computer the instructions are:

```  OP Rj,Ri - Performs Rj OP Ri and stores the result in register Ri.
OP m,Ri  - Performs val OP Ri and stores the result in Ri. val denotes the content of memory location m.
MOV m,Ri - Moves the content of memory location m to register Ri.
MOV Ri,m - Moves the content of register Ri to memory location m.```

The computer has only to registers, and OP is either ADD or SUB. Consider the following basic block:

```  t1 = a+b
t2 = c+d
t3 = e-t2
t4 = t1-t3 ```

Assume that all operands are initially in memory. The final value of the computation should be in memory. What is the minimum number of MOV instructions in the code generated for this basic block?

 A 2 B 3 C 5 D 6
Computer-Organization       Machine-Instructions       GATE 2007
Question 9 Explanation:
We can write the given four instructions using OP and MOV operations as below.
MOV a, R1
ADD b, R1
MOV c, R2
ADD d, R2
SUB e, R2
SUB R1, R2
MOV R2, m
So, from the above total no. of MOV instructions = 3
 Question 10

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

```       Instruction      Operation     Instruction size (no. of words)
MOV R1,(3000)   R1 ← m                2
LOOP: MOV R2,(R3)     R2 ← M[R3]                  1
ADD R2,R1       R2 ← R1 + R2                1
MOV (R3),R2     M[R3] ← R2                  1
INC R3          R3 ← R3 + 1                 1
DEC R1          R1 ← R1 - 1                 1
BNZ LOOP        Branch on not zero          2
HALT            Stop                        1 ```

Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal.

Assume that the memory is word addressable. The number of memory references for accessing the data in executing the program completely is:

 A 10 B 11 C 20 D 21
Computer-Organization       Machine-Instructions       GATE 2007
Question 10 Explanation:
Firstly before the loop one memory reference is,
R1 ← m
Now loop will run 10 times because R1 contain value 10, and in each iteration of the loop there are two memory reference,
R2 ← M[R3]
M[R3] ← R2
So, in total, the no. of memory references are,
2(10) + 1 = 21
 Question 11

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

```       Instruction      Operation     Instruction size (no. of words)
MOV R1,(3000)   R1 ← m                2
LOOP: MOV R2,(R3)     R2 ← M[R3]                  1
ADD R2,R1       R2 ← R1 + R2                1
MOV (R3),R2     M[R3] ← R2                  1
INC R3          R3 ← R3 + 1                 1
DEC R1          R1 ← R1 - 1                 1
BNZ LOOP        Branch on not zero          2
HALT            Stop                        1 ```

Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal.

Assume that the memory is word addressable. After the execution of this program, the content of memory location 2010 is:

 A 100 B 101 C 102 D 110
Computer-Organization       Machine-Instructions       GATE 2007
Question 11 Explanation:
Loop will execute 10 times since the value in R1 stored is 10 in first step.
Now since the value will change at memory locations from 2000 to 2009 and will not affect the memory locations 2010.
Hence, the value at memory location 2010 it will be old value, i.e., 100.
 Question 12

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

```       Instruction      Operation     Instruction size (no. of words)
MOV R1,(3000)   R1 ← m                2
LOOP: MOV R2,(R3)     R2 ← M[R3]                  1
ADD R2,R1       R2 ← R1 + R2                1
MOV (R3),R2     M[R3] ← R2                  1
INC R3          R3 ← R3 + 1                 1
DEC R1          R1 ← R1 - 1                 1
BNZ LOOP        Branch on not zero          2
HALT            Stop                        1 ```

Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal.

Assume that the memory is byte addressable and the word size is 32 bits. If an interrupt occurs during the execution of the instruction “INC R3”, what return address will be pushed on to the stack?

 A 1005 B 1020 C 1024 D 1040
Computer-Organization       Machine-Instructions       GATE 2007
Question 12 Explanation:
Memory is byte addressable, so it requires 1 word or 4 bytes to perform a each operation such that
→ Starts at memory location 1000. Interrupt occurs during the execution of information “INC R3”.
Then the value of address i.e., 1024 is pushed into the stack.
 Question 13

A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)?

 A 400 B 500 C 600 D 700
Computer-Organization       Machine-Instructions       GATE 2006
Question 13 Explanation:
The instruction is of 24 bits or 3 bytes. Now the program starts at address 300 and the next will be 303 then, 306, then 309 and so on.
So finally we can say that the values in the program counter will always be the multiple of 3.
Hence, option (C) is correct.
 Question 14

Consider a new instruction named branch-on-bit-set (mnemonic bbs). The instruction “bbs reg, pos, label” jumps to label if bit in position pos of register operand reg is one. A register is 32 bits wide and the bits are numbered 0 to 31, bit in position 0 being the least significant. Consider the following emulation of this instruction on a processor that does not have bbs implemented.

```temp ← reg & mask
Branch to label if temp is non-zero. ```

The variable temp is a temporary register. For correct emulation, the variable mask must be generated by:

 A mask ← 0×1 << pos B mask ← 0×ffffffff >> pos C mask ← pos D mask ← 0×f
Computer-Organization       Machine-Instructions       GATE 2006
Question 14 Explanation:
Using the following operation "temp→reg & mask" we are checking whether bit at position pos in register reg is 1 or not. For that mask should have 1 only in position pos. In all the other positions mask have 0s.
So for mask to have 1 only in position pos and 0s in all the other positions, we can get it by doing left shift on 1, pos number of times.
Out of the given options, in option A this left shift operation on 1 is performed pos number of times. Hence option A is the answer.
 Question 15

Consider a three word machine instruction

`ADD A[R0], @B`

The first operand (destination) "A[R0]" uses indexed addressing mode with R0 as the index register. The second operand (source) "@B" uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is

 A 3 B 4 C 5 D 6
Computer-Organization       Machine-Instructions       GATE 2005
Question 15 Explanation:
Total 4 memory cycles are required.
1 → To get 1st operand from memory address (Read).
1 → To get 2nd operand Address (Read).
1 → To get 2nd operand from the address given by previous memory (Read).
1 → To store first operand (Write).
3R + 1W = 4
 Question 16

Consider the following data path of a CPU. The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR.

The instruction "add R0, R1" has the register transfer interpretation R0 <= R0+R1. The minimum number of clock cycles needed for execution cycle of this instruction is:

 A 2 B 3 C 4 D 5
Computer-Organization       Machine-Instructions       GATE 2005
Question 16 Explanation:
1 cycle → Increment
1 cycle → Load PC to MAR
1 cycle → Fetch memory and load to PC
----------------------------------------------
3 cycles
----------------------------------------------
 Question 17

Consider the following data path of a CPU. The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR.

The instruction "call Rn, sub" is a two word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is

```      Rn <= PC + 1;
PC <= M[PC]; ```

The minimum number of CPU clock cycles needed during the execution cycle of this instruction is:

 A 2 B 3 C 4 D 5
Computer-Organization       Machine-Instructions       GATE 2005
Question 17 Explanation:
1 cycle → Increment
1 cycle → Load PC to MAR
1 cycle → Fetch memory and load to PC
----------------------------------------------
3 cycles
----------------------------------------------
 Question 18

Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.

``` Instruction 	     Operation 	      Instruction Size(in words)
MOV R1,5000; 	 ;R1 ← Memory 	         2
MOV R2(R1); 	 ;R2 ← Memory[(R1)] 	         1
ADD R2,R3; 	 ;R2 ← R2 + R3 	                 1
MOV 6000,R2; 	 ;Memory ← R2 	         2
HALT 	         ;Machine halts 	         1 ```

Consider that the memory is byte addressable with size 32 bits, and the program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be

 A 1007 B 1020 C 1024 D 1028
Computer-Organization       Machine-Instructions       GATE 2004
Question 18 Explanation:
Byte addressable with size = 32 bits (word size) = 4 bytes
→ Interrupt occurs after executing halt instruction
So, number of instructions = 2+1+1+2+1 = 7
→ Each instruction with 4 bytes, then total instruction size = 7 * 4 = 28
→ Memory start location = 1000
→ Instruction saved location = 1000 + 28 = 1028
1028 is the starting address of next instruction.
 Question 19

Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.

``` Instruction 	     Operation 	      Instruction Size(in words)
MOV R1,5000; 	 ;R1 ← Memory 	         2
MOV R2(R1); 	 ;R2 ← Memory[(R1)] 	         1
ADD R2,R3; 	 ;R2 ← R2 + R3 	                 1
MOV 6000,R2; 	 ;Memory ← R2 	         2
HALT 	         ;Machine halts 	         1 ```

Let the clock cycles required for various operations be as follows:

```Register to/ from memory transfer     : 3 clock cycles
ADD with both operands in register    : 1 clock cycle
Instruction fetch and decode          : 2 clock cycles per word  ```

The total number of clock cycles required to execute the program is

 A 29 B 24 C 23 D 20
Computer-Organization       Machine-Instructions       GATE 2004
Question 19 Explanation: Question 20

Consider the following assembly language program for a hypothetical processor. A, B, and C are 8 bit registers. The meanings of various instructions are shown as comments.

```     MOV B, # 0   	;   B ← 0
MOV C, # 8	        ;   C ← 8
Z :  CMP C, # 0	        ;   compare C with 0
JZX	        ;   jump to X if zero flag is set
SUB C, # 1	        ;   C ← C - 1
RRC A, # 1 	;   right rotate A through carry by one bit. Thus:
;   if the initial values of A and the carry flag are a7...a0 and
;   c0 respectively, their values after the execution of this
;   instruction will be c0a7...a1 and a0 respectively.
JC Y	        ;   jump to Y if carry flag is set
JMP Z	        ;   jump to Z
Y :  ADD B, # 1	        ;   B ← B + 1
JMP Z	        ;   jump to Z
X :	```

If the initial value of register A is A0 the value of register B after the program execution will be

 A the number of 0 bits in A0 B the number of 1 bits in A0 C A0 D 8
Computer-Organization       Machine-Instructions       GATE 2003
Question 20 Explanation:
B is to be increments when a is moved to carry.
The code is counting the number of 1 bits in A0.
 Question 21

Consider the following assembly language program for a hypothetical processor. A, B, and C are 8 bit registers. The meanings of various instructions are shown as comments.

```     MOV B, # 0   	;   B ← 0
MOV C, # 8	        ;   C ← 8
Z :  CMP C, # 0	        ;   compare C with 0
JZX	        ;   jump to X if zero flag is set
SUB C, # 1	        ;   C ← C - 1
RRC A, # 1 	;   right rotate A through carry by one bit. Thus:
;   if the initial values of A and the carry flag are a7...a0 and
;   c0 respectively, their values after the execution of this
;   instruction will be c0a7...a1 and a0 respectively.
JC Y	        ;   jump to Y if carry flag is set
JMP Z	        ;   jump to Z
Y :  ADD B, # 1	        ;   B ← B + 1
JMP Z	        ;   jump to Z
X :	```

Which of the following instructions when inserted at location X will ensure that the value of register A after program execution is the same as its initial value?

 A RRC A, #1 B NOP ; no operation C LRC A, #1 ; left rotate A through carry flag by one bit D ADD A, #1
Computer-Organization       Machine-Instructions       GATE 2003
Question 21 Explanation:
Initially, the 8 bits will be,
a7, a6, a5, a4, a3 , a2, a1, a0
Now right rotate it once,
C0, a7, a6, a5, a4, a3 , a2, a1, now a0 is the new carry.
Now again right rotate it,
a0C0, a7, a6, a5, a4, a3 , a2

So after 8 rotations,
a6, a5, a4, a3 , a2, a1, a0C0 and carry is a7
Now, one more rotation will restore the original value of A0.
Hence, answer is Option (A).
 Question 22

Consider the following data path of a simple non-pilelined CPU. The registers A, B, A1, A2, MDR, the bus and the ALU are 8-bit wide. SP and MAR are 16-bit registers. The MUX is of size 8 × (2:1) and the DEMUX is of size 8 × (1:2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally. The CPU instruction “push r”, where = A or B, has the specification

```     M [SP] ← r
SP ← SP - 1```

How many CPU clock cycles are needed to execute the “push r” instruction?

 A 2 B 3 C 4 D 5
Computer-Organization       Machine-Instructions       GATE 2001
Question 22 Explanation:
T1: SP → MAR, 2 cycles (as SP is 16 bits and data bus is 8 bits so needs 2 cycles to move data)
T2: 8 → MBR, 1 cycle
T3: M[MAR] ← MBR, 2 cycles (As it is a memory operation)
So, total 5 clock cycles.
 Question 23

Assume that EA = (X)+ is the effective address equal to the contents of location X, with X incremented by one word length after the effective address is calculated; EA = −(X) is the effective address equal to the contents of location X, with X decremented by one word length before the effective address is calculated; EA = (X)− is the effective address equal to the contents of location X, with X decremented by one word length after the effective address is calculated. The format of the instruction is (opcode, source, destination), which means (destination ← source op destination). Using X as a stack pointer, which of the following instructions can pop the top two elements from the stack, perform the addition operation and push the result back to the stack.

 A ADD (X)−, (X) B ADD (X), (X)− C ADD −(X), (X)+ D ADD −(X), (X)+
Computer-Organization       Machine-Instructions       GATE 2008-IT
Question 23 Explanation:
Answer is A as 998 ← 1000 + 998(These are the memory locations).
Lets say SP is 1000 initially then after it calculates the EA of source (which is 1000 as it decrements after the EA). The destination becomes 998 and this is where we want to store the result as stack is decrementing.
In case of C and D it becomes,
998 ← 998 + 998
 Question 24

Following table indicates the latencies of operations between the instruction producing the result and instruction using the result. Consider the following code segment.

```Load R1,Loc1;	 Load R1 from memory location Loc1
Load R2,Loc2;	 Load R2 from memory location Loc2
Add R1,R2,R1;	 Add R1 and R2 and save result in R1
Dec R2;	         Decrement R2
Dec R1;	         Decrement R1
Mpy R1,R2,R3;	 Multiply R1 and R2 and save result in R3
Store R3,Loc3;   Store R3 in memory location Loc3```
What is the number of cycles needed to execute the above code segment assuming each instruction takes one cycle to execute?

 A 7 B 10 C 13 D 14
Computer-Organization       Machine-Instructions       GATE 2007-IT
Question 24 Explanation:
In the given question, there are 7 instructions each of which takes 1 clock cycle to complete.
If an instruction is in execution phase then any other instructions cannot be in the execution phase. So, atleast 7 clock cycles will be taken.
Now, it is given that between two instructions latency or delay should be there based on their operation.
[Image_Link] 1) Load R1, Loc1;
Takes 1 clock cycle, simply loading R1 on Loc1.
2) Load R2, Loc2;
Takes 1 clock cycle.
3) Add R1, R2, R3;
Hence, this instruction is using the result of R1 and R2, i.e., result of Instruction 1 and Instruction 2. As Instruction 1 is load operation and Instruction 3 is ALU operation. So, there should be a delay of 1 clock cycle between Instruction 1 and Instruction 3, which is already there due to Instruction 2.
As Instruction 2 is load operation and Instruction 3 is ALU operation. So, there should be a delay of 1 clock cycle between Instruction 2 and Instruction 3.
4) Dec R2;
This instruction is dependent on Instruction 2 and there should be delay of one clock cycle between Instruction 2 and Instruction 4. As Instruction 2 is load and Instruction 4 is ALU, which is already there due to Instruction 2.
5) Dec R1;
This instruction is dependent on Instruction 3.
As Instruction 3 is ALU and Instruction 5 is also ALU, so a delay of 2 clock cycles should be there between them of which 1 clock cycle is already there due to Instruction 4. So, one clock delay between Instruction 4 and Instruction 5.
6) MPY R1, R2, R3;
This instruction uses the result of Instruction 5, as both Instruction 5 and Instruction 6 are ALU. So, there should be delay of 2 clock cycles.
7) Store R3, Loc3;
This instruction is dependent on Instruction 6 which is ALU and Instruction 7 is stored. So, there should be a delay of 2 clock cycles between them.
 Question 25
The memory locations 1000, 1001 and 1020 have data values 18, 1 and 16 respectively before the following program is executed.

```MOVI Rs, 1        ; Move immediate
LOAD Rd, 1000(Rs) ; Load from memory
ADDI Rd, 1000     ; Add immediate
STOREI 0(Rd), 20  ; Store immediate ```

Which of the statements below is TRUE after the program is executed?

 A Memory location 1000 has value 20 B Memory location 1020 has value 20 C Memory location 1021 has value 20 D Memory location 1001 has value 20
Computer-Organization       Machine-Instructions       GATE 2006-IT
Question 25 Explanation:
Rs ← 1
Rd ← 1
Rd ← 1001
Store in address 1001 ← 20.
 Question 26
A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)?
 A 400 B 500 C 600 D 700
Computer-Organization       Machine-Instructions       ISRO CS 2009
Question 26 Explanation:
C.P.U will use 24- bit instructions and instructions size(bytes) is 24/8 = 3 bytes

Program execution will start from address at 300 and from there on words every operation will takes 3- bytes and so on , So the address should be multiple of “3”. From the given options only 600 address value is valid.
 Question 27
MIMD stands for
 A Multiple instruction multiple data B multiple instruction memory data C memory instruction multiple data D multiple information memory data
Computer-Organization       Machine-Instructions       Nielit Scientist-B IT 4-12-2016
Question 27 Explanation:
In computing, MIMD (multiple instruction, multiple data) is a technique employed to achieve parallelism. Machines using MIMD have a number of processors that function asynchronously and independently. At any time, different processors may be executing different instructions on different pieces of data
 Question 28
Consider data given in the above question. What is the minimum number of page colours needed to guarantee that no two synonyms map to different sets in the processor cache of this computer?
 A 2 B 4 C 8 D 16
Computer-Organization       Machine-Instructions       Nielit Scientist-B CS 22-07-2017
Question 28 Explanation:
1 MB 16-way set associative virtually indexed physically tagged cache(VIPT).
The cache block size is 64 bytes. Question 29
The part of machine level instruction, which tells the central processor what has to be done, is
 A Operation code B Address C locator D Flip flop
Computer-Organization       Machine-Instructions       Nielit Scientist-B CS 22-07-2017
Question 29 Explanation:
An opcode (abbreviated from operation code) is the portion of a machine language instruction that specifies the operation to be performed. Beside the opcode itself, most instructions also specify the data they will process, in the form of operands.
In addition to opcodes used in the instruction set architectures of various CPUs, which are hardware devices, they can also be used in abstract computing machines as part of their byte code specifications.
A flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs
 Question 30
Which of the following is not a form of main memory?
 A Instruction cache B Instruction register C Instruction Opcode D Translation lookaside buffer
Computer-Organization       Machine-Instructions       Nielit Scientific Assistance IT 15-10-2017
Question 30 Explanation:
In computing, an opcode (abbreviated from operation code, also known as instruction syllable, instruction parcel or opstring) is the portion of a machine language instruction that specifies the operation to be performed. Beside the opcode itself, most instructions also specify the data they will process, in the form of operands. In addition to opcodes used in the instruction set architectures of various CPUs, which are hardware devices, they can also be used in abstract computing machines as part of their byte code specifications.
Note: Instruction opcode not in a form of main memory.
 Question 31
In a 10 bit computer instruction format, the size of address field is 3 bits. Thecomputer uses expanding OPcode technique and has 4 two address instructions and 16 one address instructions. The number of zero address instructions it can support is
 A 256 B 356 C 640 D 56
Computer-Organization       Machine-Instructions       Nielit Scientific Assistance IT 15-10-2017
Question 31 Explanation:
No. of possible instruction encoding =2​ 10​ =1024
No. of encoding taken by two-address instructions =4×2​ 3​ ×2​ 3​ =256
No. of encoding taken by one-address instructions =16×2​ 3​ =128
So, no. of possible zero-address instructions =1024−(256+128)=640
 Question 32
Match list I with list II and select the correct answer using the codes given below the lists. A 1 2 3 4 B 3 2 4 1 C 2 3 1 4 D 1 4 2 3
Computer-Organization       Machine-Instructions       Nielit Scientific Assistance IT 15-10-2017
Question 32 Explanation:
● A stack-organized computer does not use an address field for the instructions ADD and MUL. The PUSH and POP instructions, however, need an address field to specify the operand that communicates with the stack.
● One-address instructions use an implied accumulator (AC) register for all data manipulation.
● Two address instructions are the most common in commercial computers. Here each address field can specify either a processor register or a memory word.
● Computers with three-address instruction formats can use each address field to specify either a processor register or a memory operand.
 Question 33
Action implementing instructor’s meaning are actually carried out by____
 A Instruction fetch B Instruction decode C Instruction execution D Instruction program
Computer-Organization       Machine-Instructions       KVS 22-12-2018 Part-B
Question 33 Explanation:
→ The basic function performed by a computer is the execution of a program. The program which is to be executed is a set of instructions which are stored in memory.
→ The central processing unit (CPU) executes the instructions of the program to complete a task.
→ The major responsibility of the instruction execution is with the CPU. The instruction execution takes place in the CPU registers
 Question 34
Von neumann computer architecture is____
 A SISD B SIMD C MIMD D MISD
Computer-Organization       Machine-Instructions       KVS 22-12-2018 Part-B
Question 34 Explanation:
SISD (single instruction stream, single data stream) is a computer architecture in which a single uni-core processor, executes a single instruction stream, to operate on data stored in a single memory. This corresponds to the von Neumann architecture.
 Question 35
Match list I with list II and select the correct answer using the codes given below the lists.  A 1 2 3 4 B 3 2 4 1 C 2 3 1 4 D 1 4 2 3
Computer-Organization       Machine-Instructions       Nielit Scientific Assistance CS 15-10-2017
Question 35 Explanation:
3 address instruction:
Two operand locations and a result location are explicitly contained in the instruction word.
e.g., Y = A − B
2 address instruction:
One of the addresses is used to specify both an operand and the result location.
e.g., Y = Y + X
1 address instruction:
Two addresses are implied in the instruction and accumulator based operations.
e.g., A CC = A CC + X
0 address instructions:
They are applicable to a special memory organization called a stack. It interact with a stack using push and pop operations. All addresses are implied as in register based operations.
T = Tap(T − 1 )
 Question 36
Which of the following is not a form of main memory?
 A Instruction cache B Instruction register C Instruction Opcode D Translation lookaside buffer
Computer-Organization       Machine-Instructions       Nielit Scientific Assistance CS 15-10-2017
Question 36 Explanation:
→ The instruction opcode is the portion of a machine language instruction that specifies the operation to be performed. Beside the opcode itself, most instructions also specify the data they will process, in the form of operands. In addition to opcodes used in the instruction set architectures of various CPUs, which are hardware devices, they can also be used in abstract computing machines as part of their byte code specifications.
 Question 37

Considering every instruction and address as one word long, how many memory access are required for the following instruction, where R1, R2 and R3 are registers, and (R3) represents that R3 contains a memory address where some value (operand) is stored?

ADD R1, R2, (R3)

 A 4 B 1 C 3 D 2
Computer-Organization       Machine-Instructions       JT(IT) 2018 PART-B Computer Science
Question 37 Explanation:
We need one memory access to load the actual instruction from memory. Then R2 contains an operand value, so it doesn't require a memory access. Whereas R3 has a value which is the address of the operand, so taking that address we need to make one memory access to load the actual operand. So, this will be second memory access. The result of the addition is stored into R1. This doesn't require a memory access. So, in total there are 2 memory accesses.
 Question 38
The technology that stores only the essential instructions on a microprocessor chip and thus enhances its speed is referred to as
 A MIMD B CISC C RISC D SIMD
Computer-Organization       Machine-Instructions       KVS DEC-2017
Question 38 Explanation:
A reduced instruction set computer(or)RISC is one whose instruction set architecture (ISA) allows it to have fewer cycles per instruction (CPI) than a complex instruction set computer (CISC).
 Question 39
Which of the following is not a program instruction?
 A CMP B MOV C JMP D CALL
Computer-Organization       Machine-Instructions       KVS DEC-2017
Question 39 Explanation:
CMP The CMP instruction compares two operands. It is generally used in conditional execution. This instruction basically subtracts one operand from the other for comparing whether the operands are equal or not. It does not disturb the destination or source operands. It is used along with the conditional jump instruction for decision making.
Syntax: CMP destination, source
MOV
The MOV instruction is the most important command in the 8086 because it moves data from one location to another. It also has the widest variety of parameters; so it the assembler programmer can use MOV effectively, the rest of the commands are easier to understand.
Syntax: MOV destination,source
JMP Conditional execution often involves a transfer of control to the address of an instruction that does not follow the currently executing instruction. Transfer of control may be forward, to execute a new set of instructions or backward, to re-execute the same steps.
Syntax: JMP label
CALL
The CALL instruction interrupts the flow of a program by passing control to an internal or external subroutine. An internal subroutine is part of the calling program. An external subroutine is another program.
 Question 40
Consider the following program fragment in assembly language :
mov ax, 0h
mov cx, 0A h
doloop:
dec ax
loop doloop
What is the value of ax and cx registers after the completion of the doloop ?
 A ax=FFF5 h and cx=0 h B ax=FFF6 h and cx=0 h C ax=FFF7 h and cx=0A h D ax=FFF5 h and cx=0A h
Computer-Organization       Machine-Instructions       UGC NET CS 2017 Nov- paper-2
Question 40 Explanation:
Here ax is assigned value 0 and cx is assigned 0Ah which is equivalent to 10. Within the doloop we decrement the value of ax by 1 and the loop statement decrements cx by 1 untial cx becomes 1.
So
In 1st iteration: ax is decremented by 1, means its latest value will be -1. cx will be decremented by 1, so its latest value will be 9.
In 2nd iteration: ax will become -2. cx will become 8.
In 3rd iteration: ax will become -3. cx will become 7.
In 4th iteration: ax will become -4. cx will become 6.
In 5th iteration: ax will become -5. cx will become 5.
In 6th iteration: ax will become -6. cx will become 4.
In 7th iteration: ax will become -7. cx will become 3.
In 8th iteration: ax will become -8. cx will become 2.
In 9th iteration: ax will become -9. cx will become 1.
In 10th iteration: ax will become -10. cx will become 0.
At this stage the loop breaks as the value of cx is 0. Final value in ax is -10 which in hexadecimal equivalent to FFF6h and cx=0h
Hence option B is the answer.
 Question 41
Consider the following assembly program fragment :
stc
mov al, 11010110b
mov cl, 2
rcl al, 3
rol al, 4
shr al, cl
mul cl
The contents of the destination register ax (in hexadecimal) and the status of Carry Flag (CF) after the execution of above instructions, are:
 A ax=003CH; CF=0 B ax=001EH; CF=0 C ax=007BH; CF=1 D ax=00B7H; CF=1
Computer-Organization       Machine-Instructions       UGC NET CS 2017 Nov- paper-2
 Question 42
Consider the following assembly language instructions :
mov al, 15
mov ah, 15
xor al, al
mov cl, 3
shr ax, cl
add al, 90H
adc ah, 0
What is the value in ax register after execution of above instructions ?
 A 0270H B 0170H C 01E0H D 0370H
Computer-Organization       Machine-Instructions       UGC NET CS 2017 Jan -paper-2
Question 42 Explanation:
Step-1: mov al, 15 → move 15 to lower part of 'ax' register
mov ah, 15 → move 15 to higher part of 'ax' register
XOR al,al → Convert 15 into binary number and perform XOR operation with ‘ax’
register. The final binary value is 0000111100000000
move cl,3 → move 3 to lower part of 'cx' register.
shr ax, cl → will shift right and rotate content of 'ax' register
The 'ax' register content looks like 0000000111100000
add al, 90H → add hexadecimal 90 to al
0000000111100000
0000000010010000
---------------------------
0000001001110000
-
---------------------------
adc ah,0 → addition with carry which does not affect 'ax' register.
Step-2: Finally the content of ‘ax’ register will be 0270H.
 Question 43
The sequence of events that happen during a typical fetch operation is
 A PC ⟶ Mar ⟶ Memory ⟶ MDR ⟶ IR B PC ⟶ Memory ⟶ MDR ⟶ IR C PC ⟶ Memory ⟶ IR D PC ⟶ MAR ⟶ Memory ⟶ IR
Computer-Organization       Machine-Instructions       NIELIT Junior Teachnical Assistant_2016_march
 Question 44
What will be the output at PORT1 if the following program is executed ?
MVI B, 82H
MOV A, B
MOV C, A
MVI D, 37H
OUT PORT1
HLT
 A 37H B 82H C B9H D 00H
Computer-Organization       Machine-Instructions       UGC NET CS 2015 Dec - paper-3
Question 44 Explanation:
MOV instruction copies the data from one location to other
MVI B, 82H / Copy value 82H to register B
MOV A, B / Copy value of B (82H) to accumulator A
MOV C, A / Copy value of accumulator A (82H) to register C
MVI D, 37H / Copy value 37H to register D
OUT PORT1 /Copy value of accumulator A (82H) to PORT 1 (because still accumulator A is having 82H)
 Question 45
A computer which issues instructions in order, has only 2 registers and 3 opcodes ADD, SUB and MOV. Consider 2 different implementations of the following basic block:
Case 1 Case 2
t1=a+b; t2=c+d;
t2=c+d; t3=e-t2;
t3=e-t2; t1=a+b;
t4=t1-t2; t4=t1-t2;
Assume that all operands are initially in memory . Final value of computation also has to reside in memory. Which one is better in terms of memory accesses and by how many MOV instructions?
 A Case 2,2 B Case 2,3 C Case 1,2 D Case 1,3 E None of the above
Computer-Organization       Machine-Instructions       ISRO CS 2020
Question 45 Explanation: Case-1 is better by Case-2 by One more operation. None of the answers are correct
 Question 46
The number of instructions needed to add n numbers and store the result in memory using only one address instruction is
 A n B n+1 C n-1 D independent of n
Computer-Organization       Machine-Instructions       TNPSC-2012-Polytechnic-CS
Question 46 Explanation:
At first instruction we will load the first no. in accumulator and then from second instruction we will add remaining n-1 no. using accumulator. Till now n instruction is used. And finally we will use one more instruction to store the result back to memory. So in total n+1 instruction is required.
 Question 47
The CPU of a computer takes instruction from the memory and executes them. This process is called
 A Load cycle B Time sequences C Fetch-execute cycle D Clock cycle
Computer-Organization       Machine-Instructions       TNPSC-2012-Polytechnic-CS
Question 47 Explanation:
The process in which a CPU of a computer takes instruction from memory and executes them is called fetch-execute cycle.
There are 47 questions to complete.
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