For computers based on three-address instruction formats, each address field can be used to specify which of the following:

(S1) A memory operand
(S2) A processor register
(S3) An implied accumulator register

Consider a hypothetical processor with an instruction of type LW R1, 20 (R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand memory?

A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit instruction word has an opcode, two register operands and an immediate operand. The number of bits available for the immediate operand field is __________.

Consider a processor with 64 registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register r identifier, and a twelve-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. If a program has 100 instructions, the amount of memory (in bytes) consumed by the program text is _________.

Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the main memory is implemented from memory location (0100)₁₆ and it grows upward. The stack pointer (SP) points to the top element of the stack. The current value of SP is (016E)₁₆. The CALL instruction is of two words, the first word is the op-code and the second word is the starting address of the subroutine (one word = 2 bytes). The CALL instruction is implemented as follows:

• Store the current value of PC in the stack.
• Store the value of PSW register in the stack.
• Load the starting address of the subroutine in PC.

The content of PC just before the fetch of a CALL instruction is (5FA0)₁₆. After execution of the CALL instruction, the value of the stack pointer is

A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ________.

Which of the following must be true for the RFE (Return From Exception) instruction on a general purpose processor?

I. It must be a trap instruction
II. It must be a privileged instruction
III. An exception cannot be allowed to occur during execution of an RFE instruction

A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)?

The memory locations 1000, 1001 and 1020 have data values 18, 1 and 16 respectively before the following program is executed.

MOVI Rs, 1        ; Move immediate
LOAD Rd, 1000(Rs) ; Load from memory
ADDI Rd, 1000     ; Add immediate
STOREI 0(Rd), 20  ; Store immediate 

Which of the statements below is TRUE after the program is executed?

In a simplified computer the instructions are:

  OP Rj,Ri - Performs Rj OP Ri and stores the result in register Ri. 
  OP m,Ri  - Performs val OP Ri and stores the result in Ri. val denotes the content of memory location m.
  MOV m,Ri - Moves the content of memory location m to register Ri.
  MOV Ri,m - Moves the content of register Ri to memory location m.

The computer has only to registers, and OP is either ADD or SUB. Consider the following basic block:

  t1 = a+b
  t2 = c+d
  t3 = e-t2
  t4 = t1-t3 

Assume that all operands are initially in memory. The final value of the computation should be in memory. What is the minimum number of MOV instructions in the code generated for this basic block?

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

       Instruction      Operation     Instruction size (no. of words)
       MOV R1,(3000)   R1 ← m[3000]                2
 LOOP: MOV R2,(R3)     R2 ← M[R3]                  1
       ADD R2,R1       R2 ← R1 + R2                1
       MOV (R3),R2     M[R3] ← R2                  1
       INC R3          R3 ← R3 + 1                 1
       DEC R1          R1 ← R1 - 1                 1
       BNZ LOOP        Branch on not zero          2
       HALT            Stop                        1 

Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal.

Assume that the memory is word addressable. The number of memory references for accessing the data in executing the program completely is:

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

       Instruction      Operation     Instruction size (no. of words)
       MOV R1,(3000)   R1 ← m[3000]                2
 LOOP: MOV R2,(R3)     R2 ← M[R3]                  1
       ADD R2,R1       R2 ← R1 + R2                1
       MOV (R3),R2     M[R3] ← R2                  1
       INC R3          R3 ← R3 + 1                 1
       DEC R1          R1 ← R1 - 1                 1
       BNZ LOOP        Branch on not zero          2
       HALT            Stop                        1 

Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal.

Assume that the memory is word addressable. After the execution of this program, the content of memory location 2010 is:

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

       Instruction      Operation     Instruction size (no. of words)
       MOV R1,(3000)   R1 ← m[3000]                2
 LOOP: MOV R2,(R3)     R2 ← M[R3]                  1
       ADD R2,R1       R2 ← R1 + R2                1
       MOV (R3),R2     M[R3] ← R2                  1
       INC R3          R3 ← R3 + 1                 1
       DEC R1          R1 ← R1 - 1                 1
       BNZ LOOP        Branch on not zero          2
       HALT            Stop                        1 

Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal.

Assume that the memory is byte addressable and the word size is 32 bits. If an interrupt occurs during the execution of the instruction “INC R3”, what return address will be pushed on to the stack?