Memory-Interfacing
Question 1 |
A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to the chip select (CS) port of these memory blocks through a decoder as shown in the figure. The remaining ten input address lines from IA11–IA0 are connected to the address port of these blocks. The chip select (CS) is active high.
The input memory addresses (IA11–IA0), in decimal, for the starting locations (Addr=0) of each block (indicated as X1, X2, X3, X4 in the figure) are among the options given below. Which one of the following options is CORRECT?
The input memory addresses (IA11–IA0), in decimal, for the starting locations (Addr=0) of each block (indicated as X1, X2, X3, X4 in the figure) are among the options given below. Which one of the following options is CORRECT?
(0, 1, 2, 3) | |
(0, 1024, 2048, 3072) | |
(0, 8, 16, 24) | |
(0, 0, 0, 0) |
Question 2 |
A processor can support a maximum memory of 4GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least _________ bits.
32 | |
34 | |
31 | |
33 |
Question 2 Explanation:
Maximum Memory = 4GB = 232 bytes
Size of a word = 2 bytes
Therefore, Number of words = 232 / 2 = 231
So, we require 31 bits for the address bus of the processor.
Size of a word = 2 bytes
Therefore, Number of words = 232 / 2 = 231
So, we require 31 bits for the address bus of the processor.
Question 3 |
A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M × 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 214. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is _________.
59% | |
60% | |
61% | |
62% |
Question 3 Explanation:
Time taken to refresh one row = 50 ns
There are 214 rows, so time taken to refresh all the rows = 214 * 50ns = 0.82 milliseconds
It is given that total refresh period is 2ms. The refresh period contains the time to refresh all the rows and also the time to perform read/write operation.
So % time spent in refresh = (Time taken to refresh all rows / refresh period)*100
= (0.82 ms / 2ms)*100
= 41%
So the % of time for read/write operation = 100 - 41 = 59%
There are 214 rows, so time taken to refresh all the rows = 214 * 50ns = 0.82 milliseconds
It is given that total refresh period is 2ms. The refresh period contains the time to refresh all the rows and also the time to perform read/write operation.
So % time spent in refresh = (Time taken to refresh all rows / refresh period)*100
= (0.82 ms / 2ms)*100
= 41%
So the % of time for read/write operation = 100 - 41 = 59%
Question 4 |
How many 32K × 1 RAM chips are needed to provide a memory capacity of 256K-bytes?
8 | |
32 | |
64 | |
128 |
Question 4 Explanation:
Each chip capacity = 32K × 1- bit
Needed memory capacity = 256K - bytes = 256K*8 bits
Number of chips needed = 256K*8 / 32K×1 = 64
Needed memory capacity = 256K - bytes = 256K*8 bits
Number of chips needed = 256K*8 / 32K×1 = 64
There are 4 questions to complete.