State True or False with one line explanation
Multiplexing of address/data lines in 8085 microprocessor reduces the instruction execution time.

A single instruction to clear the lower four bits of the accumulator in 8085 assembly language?

What are x and y in the following macro definition?

 macro Add x,y
 Load y
 Mul x
 Store y
 end macro  

The following is an 8085 assembly language program:

     MVI B, OAH
     MVI A, 05H
     LXI H, IC40H
     CALL SUB
     HLT
 SUB CMP M
     RZ
     INX H
     DCR B
     JNZ SUB
     RET 

(a) What does the program do?
(b) What are the contents of registers A and B initially?
(c) What are the contents of HL register pair after the execution of the program?

A sequence of two instructions that multiplies the contents of the DE register pair by 2 and stores the result in the HL register pair (in 8085 assembly language) is:

Number of machine cycles required for RET instruction in 8085 microprocessor is

An 8052 based system has an output port with address 00H. Consider the following assembly language program.

     ORG    0100H
     MVI    A, 00H
     LXI    H, 0105H
     OUT    00H
     INR    A
     PCHL
     HLT   

(a) What does the program do with respect to the output port 00H?
(b) Show the wave forms at the three least significant bits of the port 00H.

RST 7.5 interrupt in 8085 microprocessor executes the interrupt service routine from interrupt vector location

Contents of A register after the execution of the following 8085 microprocessor program is

MVI  A, 55 H
MVI  C, 25 H
ADD  C
DAA 

The address space of 8086 CPU is

(a) Draw the schematic of an 8085 based system that can be used to measure the width of a pulse. Assume that the pulse is given as a TTL compatible signal by the source which generates it.

(b) Write the 8085 Assembly Language program to measure the width of the pulse. State all your assumption clearly.

Design a 2K x 8 (2048 locations, each 8 bit wide) memory system mapped at addresses (1000)₁₆ to (17FF)₁₆ for the 8085 processor using four 1K x 4 memory chips. Each of these chips has the following signal pins:

(i) (Chip select, data lines are in high impedance state when it is 1)
(ii) (0 for read operation)
(iii) (0 for write operation)
(iv) A₀, A₁, …A₉(input address lines. A₀ is the lest significant)
(v) D₀, D₁, D₂, D₃(bi-directional data lines. D₀ is the least significant)

To put the 8085 microprocessor in the wait state

The 8085 microprocessor responds to the present of an interrupt

A low memory can be connected to 8085 by using

A device employing INTR line for device interrupt puts the CALL instruction on the data bus while

In 8085 which of the following modifies the program counter?