 ## Microprocessor

 Question 1

Number of machine cycles required for RET instruction in 8085 microprocessor is

 A 1 B 2 C 3 D 5
Question 1 Explanation:
1 for instruction fetch.
2 for stack operation.
Total no. of cycles = 2+1 = 3
 Question 2

An 8052 based system has an output port with address 00H. Consider the following assembly language program.

```     ORG    0100H
MVI    A, 00H
LXI    H, 0105H
OUT    00H
INR    A
PCHL
HLT   ```

(a) What does the program do with respect to the output port 00H?
(b) Show the wave forms at the three least significant bits of the port 00H.

 A Theory Explanation.
 Question 3

RST 7.5 interrupt in 8085 microprocessor executes the interrupt service routine from interrupt vector location

 A 0000H B 0075H C 003CH D 0034H
Question 3 Explanation:
RST7.5 then location is = 7.5*8 = 60 (8085 is 8 bit processor)
→ 60 in hexa decimal is 003CH.
 Question 4

Contents of A register after the execution of the following 8085 microprocessor program is

```MVI  A, 55 H
MVI  C, 25 H
DAA ```
 A 7AH B 80H C 50H D 22H
Question 4 Explanation:
Note: Out of syllabus.
 Question 5

The address space of 8086 CPU is

 A one Megabyte B 256 Kilobytes C 1 K Megabytes D 64 Kilobytes
Question 5 Explanation:
Note: Out of syllabus.
 Question 6

(a) Draw the schematic of an 8085 based system that can be used to measure the width of a pulse. Assume that the pulse is given as a TTL compatible signal by the source which generates it.

(b) Write the 8085 Assembly Language program to measure the width of the pulse. State all your assumption clearly.

 A Theory Explanation.
 Question 7

Design a 2K x 8 (2048 locations, each 8 bit wide) memory system mapped at addresses (1000)16 to (17FF)16 for the 8085 processor using four 1K x 4 memory chips. Each of these chips has the following signal pins:

(i) (Chip select, data lines are in high impedance state when it is 1)
(ii) (0 for read operation)
(iii) (0 for write operation)
(iv) A0, A1, …A9(input address lines. A0 is the lest significant)
(v) D0, D1, D2, D3(bi-directional data lines. D0 is the least significant)

 A Theory Explanation.
 Question 8

To put the 8085 microprocessor in the wait state

 A lower the HOLD input B lower the READY input C raise the HOLD input D raise the READY input
Question 8 Explanation:
If ready pin is high the microprocessor will complete the operation and proceeds for the next operation. If ready pin is low the microprocessor will wait until it goes high.
 Question 9

The 8085 microprocessor responds to the present of an interrupt

 A as soon as the TRAP pin becomes ‘high’ B by checking the TRAP pin for ‘high’ status at the end of each instruction each C by checking the TRAP pin for ‘high’ status at the end of the execution of each instruction D by checking the TRAP pin for ‘high’ status at regular intervals
Question 9 Explanation:
TRAP is non maskable interrupt . TRAP is active high, level, edge triggered non maskable highest priority interrupt. When TRAP line is active microprocessor insert intervals restarts automatically at vector location of TRAP.
 Question 10

A device employing INTR line for device interrupt puts the CALL instruction on the data bus while

 A B HOLD is active C READY is active D None of the above
Question 10 Explanation:
INTR is a signal which if enabled then microprocessor has interrupt enabled it receives high INR signal & activates INTA signal, so another request can’t be accepted till CPU is busy in servicing interrupt.
 Question 11

In 8085 which of the following modifies the program counter?

 A Only PCHL instruction B Only ADD instructions C Only JMP and CALL instructions D All instructions
Question 11 Explanation:
PCHL Instruction: Which can copy the content from H& L to PC.
ADD Instruction: increments the program counter.
JMP & CALL: Change the values of PC.
 Question 12

What are the states of the Auxiliary Carry (AC) and Carry Flag (dCY) after executing the following 8085 program?

```   MVI H, 5DH
MVI L, 6BH
MOV A, H
 A AC = 0 and CY = 0 B AC = 1 and CY = 1 C AC = 1 and CY = 0 D AC = 0 and CY = 1
Question 12 Explanation:
MOV H, 5DH
⇒ H = 0101 1101
MOV L, 6BH
⇒ L = 0110 1011
MOV A, H
A = 0101 1101 Here, AC=1; CY=0
 Question 13

A single instruction to clear the lower four bits of the accumulator in 8085 assembly language?

 A XRI OFH B ANI FOH C XRI FOH D ANI OFH
Question 13 Explanation:
Here, we use the AND as a accumulator with immediate. F leaves the high nibble whatever it is, 0 clears the lower nibble.
→ The XOR's don't reliably clear random bits and ANI OF clears the upper nibble, not the lower nibble.
 Question 14

What are x and y in the following macro definition?

``` macro Add x,y
Mul x
Store y
end macro  ```
 A Variables B Identifiers C Actual parameters D Formal parameters
Question 14 Explanation:
Formal arguments (or) formal parameters is a special kind of variables used in subroutine to refer to one of pieces of data provided as input to the subroutine.
 Question 15

The following is an 8085 assembly language program:

```     MVI B, OAH
MVI A, 05H
LXI H, IC40H
CALL SUB
HLT
SUB CMP M
RZ
INX H
DCR B
JNZ SUB
RET ```

(a) What does the program do?
(b) What are the contents of registers A and B initially?
(c) What are the contents of HL register pair after the execution of the program?

 A Theory Explanation.
 Question 16

A sequence of two instructions that multiplies the contents of the DE register pair by 2 and stores the result in the HL register pair (in 8085 assembly language) is:

 Question 17

State True or False with one line explanation
Multiplexing of address/data lines in 8085 microprocessor reduces the instruction execution time.

 A True B False
Question 17 Explanation:
Note: Out of syllabus.
The major reason of multiplexing address and data bus is to reduce the number of pins for address and data and dedicate those pins for other several functions of micro-processor.
There are 17 questions to complete.

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