Microprocessor

Question 1

A device employing INTR line for device interrupt puts the CALL instruction on the data bus while

A
B
HOLD is active
C
READY is active
D
None of the above
       Computer-Organization       Microprocessor       GATE 2002
Question 1 Explanation: 
INTR is a signal which if enabled then microprocessor has interrupt enabled it receives high INR signal & activates INTA signal, so another request can’t be accepted till CPU is busy in servicing interrupt.
Question 2

In 8085 which of the following modifies the program counter?

A
Only PCHL instruction
B
Only ADD instructions
C
Only JMP and CALL instructions
D
All instructions
       Computer-Organization       Microprocessor       GATE 2002
Question 2 Explanation: 
PCHL Instruction: Which can copy the content from H& L to PC.
ADD Instruction: increments the program counter.
JMP & CALL: Change the values of PC.
Question 3

What are the states of the Auxiliary Carry (AC) and Carry Flag (dCY) after executing the following 8085 program?

   MVI H, 5DH
   MVI L, 6BH
   MOV A, H
   ADD L 
A
AC = 0 and CY = 0
B
AC = 1 and CY = 1
C
AC = 1 and CY = 0
D
AC = 0 and CY = 1
       Computer-Organization       Microprocessor       GATE 2002
Question 3 Explanation: 
MOV H, 5DH
⇒ H = 0101 1101
MOV L, 6BH
⇒ L = 0110 1011
MOV A, H
A = 0101 1101
ADD L ⇒ A+L =

Here, AC=1; CY=0
Question 4

A low memory can be connected to 8085 by using

A
INTER
B
C
HOLD
D
READY
       Computer-Organization       Microprocessor       GATE 2001
Question 4 Explanation: 
Communication is only possible when READY signal is set. So a low memory can be connected to 8085 by using READY signal.
Question 5

To put the 8085 microprocessor in the wait state

A
lower the HOLD input
B
lower the READY input
C
raise the HOLD input
D
raise the READY input
       Computer-Organization       Microprocessor       GATE 2000
Question 5 Explanation: 
If ready pin is high the microprocessor will complete the operation and proceeds for the next operation. If ready pin is low the microprocessor will wait until it goes high.
Question 6

The 8085 microprocessor responds to the present of an interrupt

A
as soon as the TRAP pin becomes ‘high’
B
by checking the TRAP pin for ‘high’ status at the end of each instruction each
C
by checking the TRAP pin for ‘high’ status at the end of the execution of each instruction
D
by checking the TRAP pin for ‘high’ status at regular intervals
       Computer-Organization       Microprocessor       GATE 2000
Question 6 Explanation: 
TRAP is non maskable interrupt . TRAP is active high, level, edge triggered non maskable highest priority interrupt. When TRAP line is active microprocessor insert intervals restarts automatically at vector location of TRAP.
Question 7

Design a 2K x 8 (2048 locations, each 8 bit wide) memory system mapped at addresses (1000)16 to (17FF)16 for the 8085 processor using four 1K x 4 memory chips. Each of these chips has the following signal pins:

    (i) (Chip select, data lines are in high impedance state when it is 1)
    (ii) (0 for read operation)
    (iii) (0 for write operation)
    (iv) A0, A1, …A9(input address lines. A0 is the lest significant)
    (v) D0, D1, D2, D3(bi-directional data lines. D0 is the least significant)

A
Theory Explanation.
       Computer-Organization       Microprocessor       GATE 1999
Question 8

The address space of 8086 CPU is

A
one Megabyte
B
256 Kilobytes
C
1 K Megabytes
D
64 Kilobytes
       Computer-Organization       Microprocessor       GATE 1998
Question 8 Explanation: 
Note: Out of syllabus.
Question 9

(a) Draw the schematic of an 8085 based system that can be used to measure the width of a pulse. Assume that the pulse is given as a TTL compatible signal by the source which generates it.

(b) Write the 8085 Assembly Language program to measure the width of the pulse. State all your assumption clearly.

A
Theory Explanation.
       Computer-Organization       Microprocessor       GATE 1998
Question 10

RST 7.5 interrupt in 8085 microprocessor executes the interrupt service routine from interrupt vector location

A
0000H
B
0075H
C
003CH
D
0034H
       Computer-Organization       Microprocessor       GATE 1997
Question 10 Explanation: 
RST7.5 then location is = 7.5*8 = 60 (8085 is 8 bit processor)
→ 60 in hexa decimal is 003CH.
Question 11

Contents of A register after the execution of the following 8085 microprocessor program is

MVI  A, 55 H
MVI  C, 25 H
ADD  C
DAA 
A
7AH
B
80H
C
50H
D
22H
       Computer-Organization       Microprocessor       GATE 1997
Question 11 Explanation: 
Note: Out of syllabus.
Question 12

Number of machine cycles required for RET instruction in 8085 microprocessor is

A
1
B
2
C
3
D
5
       Computer-Organization       Microprocessor       GATE 1996
Question 12 Explanation: 
1 for instruction fetch.
2 for stack operation.
Total no. of cycles = 2+1 = 3
Question 13

An 8052 based system has an output port with address 00H. Consider the following assembly language program.

     ORG    0100H
     MVI    A, 00H
     LXI    H, 0105H
     OUT    00H
     INR    A
     PCHL
     HLT   

(a) What does the program do with respect to the output port 00H?
(b) Show the wave forms at the three least significant bits of the port 00H.

A
Theory Explanation.
       Computer-Organization       Microprocessor       GATE 1996
Question 14

A single instruction to clear the lower four bits of the accumulator in 8085 assembly language?

A
XRI OFH
B
ANI FOH
C
XRI FOH
D
ANI OFH
       Computer-Organization       Microprocessor       GATE 1995
Question 14 Explanation: 
Here, we use the AND as a accumulator with immediate. F leaves the high nibble whatever it is, 0 clears the lower nibble.
→ The XOR's don't reliably clear random bits and ANI OF clears the upper nibble, not the lower nibble.
Question 15

What are x and y in the following macro definition?

 macro Add x,y
 Load y
 Mul x
 Store y
 end macro  
A
Variables
B
Identifiers
C
Actual parameters
D
Formal parameters
       Computer-Organization       Microprocessor       GATE 1995
Question 15 Explanation: 
Formal arguments (or) formal parameters is a special kind of variables used in subroutine to refer to one of pieces of data provided as input to the subroutine.
Question 16

The following is an 8085 assembly language program:

     MVI B, OAH
     MVI A, 05H
     LXI H, IC40H
     CALL SUB
     HLT
 SUB CMP M
     RZ
     INX H
     DCR B
     JNZ SUB
     RET 

(a) What does the program do?
(b) What are the contents of registers A and B initially?
(c) What are the contents of HL register pair after the execution of the program?

A
Theory Explanation.
       Computer-Organization       Microprocessor       GATE 1995
Question 17

A sequence of two instructions that multiplies the contents of the DE register pair by 2 and stores the result in the HL register pair (in 8085 assembly language) is:

A
XCHG and DAD B
B
XTHL and DAD H
C
PCHL and DAD D
D
XCHG and DAD H
       Computer-Organization       Microprocessor       GATE 1995
Question 18

State True or False with one line explanation
Multiplexing of address/data lines in 8085 microprocessor reduces the instruction execution time.

A
True
B
False
       Computer-Organization       Microprocessor       GATE 1994
Question 18 Explanation: 
Note: Out of syllabus.
The major reason of multiplexing address and data bus is to reduce the number of pins for address and data and dedicate those pins for other several functions of micro-processor.
Question 19

Given that the following is an 8085 program segment:
(a) Identify the function performed by it, and
(b) List the roles of the registers used and the address referred to by it.

                    LHLD                5000
                    MVI                 B, 5
     GET:           IN                  20
                    MOV                 M, A
                    INX                 H
                    DCR                 B
                    JNZ                 GET  
A
Theory Explanation.
       Computer-Organization       Microprocessor       GATE 1993
Question 20

Many microprocessors have a specified lower limit on clock frequency (apart from the maximum clock frequency limit) because ______

A
clock frequency can't go below this value.
       Computer-Organization       Microprocessor       GATE 1992
Question 20 Explanation: 
Clock frequency becomes low memory time period of clock becomes high. When this time period increases beyond the time period in which the non-volatile memory contents must be refreshed, we loose those contents. So clock frequency can't go below this value.
Question 21

Many of the advanced microprocessors prefetch instructions and store it in an instruction buffer to speed up processing. This speed up is achieved because _________

A
prefetching the instructions to be executed can save considerable amount of waiting time.
       Computer-Organization       Microprocessor       GATE 1992
Question 21 Explanation: 
Because CPU is faster than memory. Fetching the instructions from memory would require considerable amount of time while CPU is much faster. So, prefetching the instructions to be executed can save considerable amount of waiting time.
Question 22

PCHL is an instruction in 8085 which transfers the contents of the register pair HL to PC. This is not a very commonly used instruction as it changes the flow of control in rather ‘unstructured’ fashion. This instruction can be useful in implementing.

A
if ……. then ….. else ….. construct
B
while …… construct
C
case …… construct
D
call …… construct
       Computer-Organization       Microprocessor       GATE 1992
Question 22 Explanation: 
Note: Out of syllabus.
Question 23

A microprocessor is capable of addressing 1 megabyte of memory with a 20-bit address bus. The system to be designed requires 256 K bytes of RAM, 256 K bytes of EPROM, 16 I/O devices (memory mapped I/O) and 1 K byte of EERAM (electrically erasable RAM).

(a) Design a memory map (to reduce decoding logic) and show the decoding logic if the components available are:

 Type         Size         Speed
 RAM         6 K × 8     140 n sec
 EPROM       256 K × 8   150 n sec
 EERAM       256 × 8     500 n sec-read 3µsec-write 

(b) The micro processor is operating at 12.5 mHz and provides time equivalent to two clock cycles for memory read and write. Assuming control signals similar to 8085, design the extra logic required for interfacing EERAM.

A
Theory Explanation.
       Computer-Organization       Microprocessor       GATE 1992
Question 24

Using the 8087 arithmetic coprocessor with the 8087 CPU requires that the 8087 CPU is operated ________.

A
Out of syllabus.
       Computer-Organization       Microprocessor       GATE 1991
Question 25

Match the pairs in the following questions by writing the corresponding letters only. For the 8086 microprocessor:

(A) RQ/GT   (P) Used by processor for holding the bus for consecutive instruction
                cycles.
(B) LOCK    (Q) Used for extending the memory or I/O cycle times
(C) HOLD    (R) Used for getting hold of processor bus in minimum bus mode
(D) READY   (S) Used for requesting processor bus in minimum bus mode.
A
Out of syllabus.
       Computer-Organization       Microprocessor       GATE 1991
Question 26

Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: The TRAP interrupt mechanism of the 8085 microprocessor:

A
executes an instruction supplied by an external device through the INTA signal
B
executes an instruction from memory location 20H
C
executes a NOP
D
none of the above
       Computer-Organization       Microprocessor       GATE 1991
Question 26 Explanation: 
Note: Out of syllabus.
Question 27

Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: The ALE line of an 8085 microprocessor is used to:

A
latch the output of an I/O instruction into an external latch
B
deactivate the chip-select signal from memory devices
C
latch the 8 bits of address lines AD7-AD0 into an external latch
D
find the interrupt enable status of the TRAP interrupt
E
None of the above
       Computer-Organization       Microprocessor       GATE 1991
Question 27 Explanation: 
Note: Out of syllabus.
Question 28

(a) Consider an 8085 based system operating with the following specification:

Crystal frequency : 6 MHz
ROM map : 0000 through 07FF
RAM map : 1000 through 17 FF:
ROM requires one wait state.
RAM requires no wait state. 

Determine the instruction cycle time for each of the following instructions:

(i) ORI A, 22 
(ii) DCR M 

Assume the following initial conditions of the CPU registers (in hex) for each of the instructions:

 A = 55, B = AA, C = F7, D = 10, H = 10, L = FF, PC = 0200, SP = 17FO. 

(b) Developing an output port interface (draw a block schematic) for an 8085 based system with a demultiplexed address bus which incorporates a handshake protocol as per the timing diagram given in figure. The interface should include a status input port at I/O address 40H which reads the INTERRUPT and BUFFFULL signals through the most significant bit and the least significant bit, respectively. The output data port is at the same I/O address 40H and is activated by a write operation. Assume the availability of SSI and MSI level components only.
Write a short program segment which performs a 200 H byte programmed I/O data transfer to the device from memory address 3400 H,

A
Theory Explanation.
       Computer-Organization       Microprocessor       GATE 1991
Question 29
Which interrupt in 8085 Microprocessor is unmaskable?
A
RST 5.5
B
RST 7.5
C
TRAP
D
Both (a) and (b)
       Computer-Organization       Microprocessor       ISRO-2017 May
Question 29 Explanation: 
Interrupts are the signals generated by the external devices to request the microprocessor to perform a ask. There are 5 interrupt signals. Given low priority to high is
1. INTR
2. RST 5.5
3. RST 6.5
4. RST 7.5
5. TRAP
Maskable Interrupts: They can be enabled or disabled by software INTR,RST 5.5,RST 6.5 and RST 7.5
Un maskable Interrupts: TRAP
Question 30
A certain microprocessor requires 4.5 microseconds to respond to an interrupt. Assuming that the three interrupts I1, I2 and I3 require the following execution time after the interrupt is recognized:
i. I1 requires 25 microseconds
ii. I2 requires 35 microseconds
iii. I3 requires 20 microseconds
I1 has the highest priority and I3 has the lowest. What is the possible range of time for I3 to be executed assuming that it may or may not occur simultaneously with other interrupts?
A
24.5 microseconds to 39.5 microseconds
B
24.5 microseconds to 93.5 microseconds
C
4.5 microseconds to 24.5 microseconds
D
29.5 microseconds 93.5 microseconds
       Computer-Organization       Microprocessor       ISRO CS 2009
Question 30 Explanation: 
Consider case-1: I3 is executed without other interrupts:

Time interval = Interrupt processing time(I3) + Execution time(I3) = 4.5 + 20 microseconds = 24.5 microseconds

Consider case-2: I3 is executed simultaneously with other interrupts:

Time interval =( Interrupt processing time + Execution time) for I1, I2, I3 = 4.5 + 25 + 4.5 + 35 + 4.5 + 20 = 93.5 microseconds
Question 31
MOV [BX], AL type of data addressing is called ?
A
register
B
immediate
C
register indirect
D
register relative
       Computer-Organization       Microprocessor       ISRO CS 2011
Question 31 Explanation: 
Register indirect addressing means that the location of an operand is held in a register.
In register addressing mode, a register contains the operand. Depending upon the instruction, the register may be the first operand, the second operand or both.
In Immediate Addressing,an immediate operand has a constant value or an expression. When an instruction with two operands uses immediate addressing, the first operand may be a register or memory location, and the second operand is an immediate constant.
Question 32
If a microcomputer operates at 5 MHz with an 8-bit bus and a newer version operates at 20 MHz with a 32-bit bus, the maximum speed-up possible approximately will be
A
2
B
4
C
8
D
16
       Computer-Organization       Microprocessor       ISRO CS 2011
Question 32 Explanation: 
The newer version is the best as compared to old one, but the second version has both high bandwidth as well as increased CPU speed.
20/5 = 4 and 32/8 = 4
Maximum speed up possible is 4
Question 33
A processor takes 12 cycles to complete an instruction I. The corresponding pipelined processor uses 6 stages with the execution times of 3, 2, 5, 4, 6 and 2 cycles respectively. What is the asymptotic speedup assuming that a very large number of instructions are to be executed?
A
1.83
B
2
C
3
D
6
       Computer-Organization       Microprocessor       ISRO CS 2011
Question 33 Explanation: 
Step-1: Speed Up= Time without Pipeline / Time with Pipeline
Step-2: It is given that without pipeline it takes 12ns to execute one instruction. Assuming there are n-instructions, time without pipeline = (12*n) ns.
Step-3: For time with pipeline, when there are k-stages in the pipeline, time taken to execute n-instructions is = (k+n-1) clock cycles.
Step-4: There are six stages in the pipeline, so k=6.
Time with pipeline = (6+n-1) clock cycles
= (n+5) clock cycles.
Step-5: It is also given that very large number of instructions are to be executed. So in the time with pipeline, (n+5) clock cycles, we can ignore 5. So time with pipeline for running large number of instructions = n clock cycles.
Step-6: 1 clock cycle time in pipeline = max. of all stage delays
= max(3, 2, 5, 4, 6, 2)
= 6ns
Now, time with pipeline= (n*6) ns
Asymptotic speedup = (12*n) / (6*n)
= 2
Question 34
Find the memory address of the next instruction executed by the microprocessor (8086), when operated in real mode for CS=1000 and IP=E000
A
10E00
B
1E000
C
F000
D
1000E
       Computer-Organization       Microprocessor       ISRO CS 2011
Question 35
In 8086, the jump condition for the instruction JNBE is?
A
CF = 0 or ZF = 0
B
ZF = 0 and SF = 1
C
CF = 0 and ZF = 0
D
CF = 0
       Micro-Processors       Microprocessor       ISRO CS 2013
Question 35 Explanation: 
→JA/JNBE :Jump if above/ Jump if not below or equal
→Description: Jumps to the destination label mentioned in the instruction if the result of previous instruction (generally compare) causes both CF and ZF to have value equal to 0, else no action is taken.
Question 36
In 8085 microprocessor, the ISR for handling trap interrupt is at which location?
A
3CH
B
34H
C
74H
D
24H
       Micro-Processors       Microprocessor       ISRO CS 2013
Question 36 Explanation: 
→A small program or a routine that when executed services the corresponding interrupting source is called as an Interrupt Service Routine(ISR).
→TRAP is a non-maskable interrupt, having the highest priority among all interrupts.
→By default, it is enabled until it gets acknowledged.
→In case of failure, it executes as ISR and sends the data to backup memory.
→This interrupt transfers the control to the location 0024H.
Question 37
How many number of times the instruction sequence below will loop before coming out of the loop?
A1:  MOV AL, 00H
INC AL
JNZ A1
A
1
B
255
C
256
D
Will not come out of the loop
       Computer-Organization       Microprocessor       ISRO CS 2013
Question 37 Explanation: 
A1: MOV AL, 00H // Storing the value zero into the register AL, Now AL value is 00000000
INC AL // INCREMENT AL register value.
JNZ A1
The JNZ instruction transfers control to the specified address if the value in the accumulator is not 0
Step-1: AL = 0000 0000
Step-2:Next step is for increment the value of AL.
Step-3: Checking the jump condition
The above steps shall repeat until the accumulator value is not equal to zero.
→AL will keep on incrementing and after 255th iteration the value will become 1111 1111
→Again the condition is checked and incremented, now in 256th iteration AL = 1 0000 0000.
→As AL is an 8-bit register, 1 is discarded and the value becomes 0000 0000 and conditional jump to A1 occurs.
→So, total 256 iterations.
Question 38
The contents of the flag register after execution of the following program by 8085 microprocessor will be
Program
SUB A
MVI B,(01)H
DCR B
HLT
A
(54)H
B
(00)H
C
(01)H
D
(45)H
       Computer-Organization       Microprocessor       ISRO CS 2015
Question 38 Explanation: 
Question 39
The Communication between the components in a microcomputer takes place via the address and ____
A
I/O bus
B
Data bus
C
Address bus
D
Control lines
       Computer-Organization       Microprocessor       KVS 22-12-2018 Part-B
Question 39 Explanation: 
→ A data bus is a system within a computer or device, consisting of a connector or set of wires, that provides transportation for data.
→ A data bus is also called a processor bus, front side bus, frontside bus or backside bus—is a group of electrical wires used to send information (data) between two or more components.
Question 40
_____ is the first Intel x86 microprocessor with a dual core, referring to the implementation of two processors on a single chip
A
Core
B
Core 2 duo
C
Dual core
D
Centrino
       Computer-Organization       Microprocessor       KVS DEC-2013
Question 40 Explanation: 
Core:​ This is the first Intel x86 microprocessor with a dual core, referring to the implementation of two processors on a single chip.
Core 2:​ The Core 2 extends the architecture to 64 bits. The Core 2 Quad provides four processors on a single chip. More recent Core offerings have up to 10 processors per chip.
Dual-core​ refers to a CPU that includes two complete execution cores per physical processor. It has combined two processors and their caches and cache controllers onto a single integrated circuit (silicon chip).
Question 41
This was the first general purpose microprocessor. It was designed to be the CPU of a general purpose micro computer. It was faster, had a richer instruction set and a larger addressing capability. Which microprocessor are we discussing?
A
4004
B
8008
C
8080
D
All of the these
       Computer-Organization       Microprocessor       KVS DEC-2013
Question 41 Explanation: 
4004 and 8008 designed for specific purpose but 8080 microprocessor is first general purpose micro computer.
Question 42
The contents of Register (BL) and Register (AL) of 8085 microprocessor are 49H and 3AH respectively. The contents of AL, the status of carry flag (CF) and sign flag (SF) after executing ‘SUB AL, BL’ assembly language instruction, are
A
AL = 0FH; CF = 1; SF = 1
B
AL = F0H; CF = 0; SF = 0
C
AL = F1H; CF = 1; SF = 1
D
AL = 1FH; CF = 1; SF = 1
       Computer-Organization       Microprocessor       UGC NET CS 2017 Jan -paper-2
Question 42 Explanation: 
Initially BL=0100 1001 and AL=0011 1010
Step-1: We have to perform subtraction of AL and BL
AL= 0011 1010 ( Here, MSB and Second MSB bit taken borrow 1)
BL= 0111 1001
------------------
1111 0001
------------------
Step-2: Final result have to be stored in AL. AL = F1H; CF = 1; SF = 1
So, option C is the correct answer.
Question 43
The first operating system of Microprocessor is __________ .
A
ATLAS
B
CP/M
C
SAGE
D
T.H.E.
       Computer-Organization       Microprocessor       UGC NET CS 2006 June-Paper-2
Question 43 Explanation: 
The first operating system of Microprocessor is CP/M.
CP/M (Control Program/Monitor (or) Control Program for Microcomputers)
It is a mass-market operating system created in 1974 for Intel 8080/85-based microcomputers by Gary Kildall of Digital Research. Initially confined to single-tasking on 8-bit processors and no more than 64 kilobytes of memory, later versions of CP/M added multi-user variations and were migrated to 16-bit processors.
Question 44
​ In 8085 microprocessor, what is the output of following program ? LDA 8000H MVI B, 30H ADD B STA 8001H
A
Read a number from input port and store it in memory
B
Read a number from input device with address 8000H and store it in memory at location 8001H
C
Read a number from memory at location 8000H and store it in memory location 8001H
D
Load A with data from input device with address 8000H and display it on the output device with address 8001H
       Computer-Organization       Microprocessor       UGC NET CS 2018 JUNE Paper-2
Question 44 Explanation: 
→ 1st instruction "LDA 8000H" transfers data from memory location 8000H to Accumulator
→ 2nd instruction "MVI B, 30H" moves 30H to register B.
→ 3rd instruction "ADD B" adds contents of B with Accumulator and stores it back to Accumulator. So basically the contents of Accumulator are incremented by 30H.
→ 4th instruction "STA 8001H" stores the contents of Accumulator in memory location 8001H.
As none of the choices include the 'addition operation', we need to choose appropriate option from the given options.
→ Option 4 mentions about loading the content from 8000H to accumulator A. Hence option 4 is more appropriate.
Question 45
A complete microcomputer system consists of
A
Microprocessor
B
Memory
C
Peripheral equipment
D
All of the above
       Computer-Organization       Microprocessor       UGC NET CS 2012 June-Paper2
Question 45 Explanation: 
A complete microcomputer system consists of Microprocessor,Memory and Peripheral equipment.
Question 46
Intel 8086 is a
A
8 bit
B
16 bit
C
32 bit
D
64 bit
       Computer-Organization       Microprocessor       NIELIT Junior Teachnical Assistant_2016_march
Question 47
The first operating system used in microprocessor is
A
Zenix
B
DOS
C
CP/M
D
Multics
       Computer-Organization       Microprocessor       NIELIT Junior Teachnical Assistant_2016_march
Question 48
In a microprocessor, the address of next instruction to be executed is stored in
A
Stack pointer
B
Address latch
C
Program counter
D
Any general purpose register
       Computer-Organization       Microprocessor       NIELIT Technical Assistant_2016_march
Question 49
Which of the following μP is a 8 bit processor ?
A
80286
B
8085
C
80386
D
8086
       Computer-Organization       Microprocessor       NIELIT Technical Assistant_2016_march
Question 50
In 8085 microprocessor which of the following flag(s) is (are) affected by an arithmetic operation ?
A
AC flag Only
B
CY flag Only
C
Z flag Only
D
AC, CY, Z flags
       Computer-Organization       Microprocessor       UGC NET CS 2017 Nov- paper-3
Question 50 Explanation: 
AC Flag: This flag is set if thee is a carry to fifth bit from the fourth bits if two numbers.


Question 51
In 8085 microprocessor the address bus is of __________ bits.
A
4
B
8
C
16
D
32
       Computer-Organization       Microprocessor       UGC NET CS 2017 Nov- paper-3
Question 51 Explanation: 
In 8085 microprocessor the address bus is of 16 bits and data bus is 8 bits.
Question 52
In the architecture of 8085 microprocessor match the following:
A
(a)-(iv), (b)-(i), (c)-(ii)
B
(a)-(iii), (b)-(iv), (c)-(ii)
C
(a)-(ii), (b)-(iii), (c)-(i)
D
(a)-(i), (b)-(ii), (c)-(iv)
       Computer-Organization       Microprocessor       UGC NET CS 2017 Nov- paper-3
Question 52 Explanation: 
Processing unit→ ALU
Arithmetic logic unit(ALU) is a fundamental building block of many types of computing circuits, including the central processing unit (CPU) of computers, FPUs, and graphics processing units (GPUs).
Instruction unit →Timing and control
Timing and Control unit is responsible for hardwired control unit and Microprogrammed control unit
Storage and Interface unit → General purpose Register
The general purpose register can store a data (or) a memory location address.
Question 53
In 8085 microprocessor, the digit 5 indicates that the microprocessor needs:
A
–5 volts, +5 volts supply
B
+5 volts supply only
C
–5 volts supply only
D
5 MHz clock
       Computer-Organization       Microprocessor       UGC NET CS 2017 Jan- paper-3
Question 53 Explanation: 
Before 8085 microprocessors require +5V, -5V and 12V. In 8085 microprocessor need +5 volts supply only.
Question 54
In 8085, which of the following performs : load register pair immediate operation?
A
LDAX rp
B
LHLD addr
C
LXI rp, data
D
INX rp
       Computer-Organization       Microprocessor       UGC NET CS 2017 Jan- paper-3
Question 54 Explanation: 
LDAX: Load accumulator indirect( This instruction copies the contents of that memory location into the accumulator. )
LHLD: Load H and L register direct ( This instruction loads the contents of the 16- bit memory location into the H and L register pair. )
LXI: Load register pair immediate( The instruction loads 16-bit data in the register pair designated in the operand.)
INX: Increment register pair by 1.( It will increment the register value by 1.)
Question 55
8085 microprocessor has _____ hardware interrupts.
A
2
B
3
C
4
D
5
       Computer-Organization       Microprocessor       UGC NET CS 2016 July- paper-3
Question 55 Explanation: 

Question 56
Which of the following in 8085 microprocessor performs HL = HL + DE ?
A
DAD D
B
DAD H
C
DAD B
D
DAD SP
       Computer-Organization       Microprocessor       UGC NET CS 2016 July- paper-3
Question 56 Explanation: 
DAD: - Add register pair to HL register. The 16-bit contents of the specified register pair are added to the contents of the HL register and the sum is stored in the HL register. The contents of the source register pair are not altered. If the result is larger than 16 bits, the CY flag is set. No other flags are affected.
HL = HL + DE means DAD D
Question 57
8085 microprocessor has ____ bit ALU.
A
32
B
16
C
8
D
4
       Computer-Organization       Microprocessor       UGC NET CS 2016 Aug- paper-3
Question 57 Explanation: 
8085 microprocessor has 8 bit ALU. It performs arithmetic and logical operations like Addition, Subtraction, AND, OR, etc. on 8-bit data.
Question 58
Which of the following in 8085 microprocessor performs 
HL = HL + HL?
A
DAD D
B
DAD H
C
DAD B
D
DAD SP
       Computer-Organization       Microprocessor       UGC NET CS 2016 Aug- paper-3
Question 59
Which of the following 8085 microprocessor hardware interrupt has the lowest priority?
A
RST 6.5
B
RST 7.5
C
TRAP
D
INTR
       Computer-Organization       Microprocessor       UGC NET CS 2015 Dec - paper-3
Question 59 Explanation: 

DI(Disable Interrupt): DI allows the microprocessor to reject the interrupt. In DI the interrupts are disabled immediately and no flags are affected.
SIM(Set Instruction Mask): It uses flags to disable the interrupts. Here “1” indicated that the interrupt is masked and “0” indicates the the instruction is not masked.
Question 60
Consider a 32 - bit microprocessor, with a 16 - bit external data bus, driven by an 8 MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate for this microprocessor?
A
8 × 10​ 6​ bytes/sec
B
4 × 10​ 6​ bytes/sec
C
16 × 10​ 6​ bytes/sec
D
4 × 10​ 9​ bytes/sec
       Computer-Organization       Microprocessor       UGC NET CS 2015 June Paper-3
Question 60 Explanation: 
Question 61
The RST 7 instruction in 8085 microprocessor is equivalent to:
A
CALL 0010 H
B
CALL 0034 H
C
CALL 0038 H
D
CALL 003C H
       Computer-Organization       Microprocessor       UGC NET CS 2015 June Paper-3
Question 61 Explanation: 
Question 62
Which of the following affects the processing power assuming they do not influence each other.
Data bus capability
Addressing scheme
Clock speed
A
3 only
B
1 and 3 only
C
2 and 3 only
D
1, 2 and 3
       Computer-Organization       Microprocessor       ISRO CS 2020       Video-Explanation
Question 62 Explanation: 
"Though different addressing schemes take different amount of execution times that will not affect the processing power. So, out of the given components only data bus capability and clock speed affect the processing power."
Question 63
In an 8085 microprocessor system with memory mapped I/O.
A
I/O devices have 8 bit addresses
B
I/O devices are accessed using IN and OUT instructions
C
There can be maximum of 256 input devices and 256 output devices
D
Arithmetic and logic operations can be directly performed with the I/O data
       Computer-Organization       Microprocessor       TNPSC-2012-Polytechnic-CS
Question 63 Explanation: 
In a 8085 microprocessor system with memory mapped I/O then Arithmetic and logic operations can be directly performed with the I/O data. ... An arithmetic-logic unit (ALU) is the part of a computer processor (CPU) that carries out arithmetic and logic operations on the operands in computer instruction words.
Question 64
One of the main features that distinguish microprocessor from micro-computers is
A
words are usually larger in microprocessors.
B
words are shorter in microprocessors.
C
microprocessor does not contain I/O devices.
D
None of the above.
       Computer-Organization       Microprocessor       UGC NET CS 2014 June-paper-3
Question 64 Explanation: 
Microprocessor: Microprocessor is a simple central processing unit (CPU) on a single chip (remember the word ‘Single Chip’). It includes Arithmetic logic unit (ALU), control unit (CU), registers, instruction decoders, bus control circuit etc. but everything should be on a single chip.
Microcomputer: A microcomputer is the association of microprocessor and the peripheral I/O devices, support circuitry and memory (both data and program). It is not necessary to be on a single chip (remember this point, not in a single chip).
Question 65
Specify the contents of the accumulator and the status of the S, Z and CY flags when 8085 microprocessor performs addition of 87 H and 79 H.
A
11, 1, 1, 1
B
10, 0, 1, 0
C
01, 1, 0, 0
D
00, 0, 1, 1
       Computer-Organization       Microprocessor       UGC NET CS 2014 Dec - paper-3
Question 65 Explanation: 

Since MSB of 8-bit result is zero, it means the number is positive. So Sign flag will be “0”.
Since 8-bit result contain zero only so Zero flag will be “1”.
Since addition operation is resulting into a carry so Carry flag will be “1”.
Question 66
Which of the following statements with respect to the multiprocessor system are true? A) Multiprocessor system is controlled by one operating system. B) In a Multiprocessor system, multiple computers are connected by means of communication lines. C) Multiprocessor system is classified as multiple instruction streams and multiple data stream systems. Choose the correct answer from the options given below
A
(A) only
B
(A) and (B) Only
C
(A) and (C) only
D
(B) and (C) only
       Computer-Organization       Microprocessor       UGC NET JRF November 2020 Paper-2
Question 66 Explanation: 
A multiprocessor is a computer system having two or more processing units (multiple processors) each sharing main memory and peripherals, in order to simultaneously process programs.
FALSE: Multiprocessor systems are controlled by one or more operating systems. TRUE: In a Multiprocessor system, multiple computers are connected by the means of communication lines.
TRUE: Multiprocessor system is classified as multiple instruction streams and multiple data stream systems.
There are 66 questions to complete.