Microprocessor
Question 1 |
Given that the following is an 8085 program segment:
(a) Identify the function performed by it, and
(b) List the roles of the registers used and the address referred to by it.
LHLD 5000 MVI B, 5 GET: IN 20 MOV M, A INX H DCR B JNZ GET
Theory Explanation. |
Question 2 |
State True or False with one line explanation
Multiplexing of address/data lines in 8085 microprocessor reduces the instruction
execution time.
True | |
False |
The major reason of multiplexing address and data bus is to reduce the number of pins for address and data and dedicate those pins for other several functions of micro-processor.
Question 3 |
A single instruction to clear the lower four bits of the accumulator in 8085 assembly language?
XRI OFH | |
ANI FOH | |
XRI FOH | |
ANI OFH |
→ The XOR's don't reliably clear random bits and ANI OF clears the upper nibble, not the lower nibble.
Question 4 |
What are x and y in the following macro definition?
macro Add x,y Load y Mul x Store y end macro
Variables | |
Identifiers | |
Actual parameters | |
Formal parameters |
Question 5 |
The following is an 8085 assembly language program:
MVI B, OAH MVI A, 05H LXI H, IC40H CALL SUB HLT SUB CMP M RZ INX H DCR B JNZ SUB RET
(a) What does the program do?
(b) What are the contents of registers A and B initially?
(c) What are the contents of HL register pair after the execution of the program?
Theory Explanation. |
Question 6 |
A sequence of two instructions that multiplies the contents of the DE register pair by 2 and stores the result in the HL register pair (in 8085 assembly language) is:
XCHG and DAD B | |
XTHL and DAD H | |
PCHL and DAD D | |
XCHG and DAD H |
Question 7 |
Number of machine cycles required for RET instruction in 8085 microprocessor is
1 | |
2 | |
3 | |
5 |
2 for stack operation.
Total no. of cycles = 2+1 = 3
Question 8 |
An 8052 based system has an output port with address 00H. Consider the following assembly language program.
ORG 0100H MVI A, 00H LXI H, 0105H OUT 00H INR A PCHL HLT
(a) What does the program do with respect to the output port 00H?
(b) Show the wave forms at the three least significant bits of the port 00H.
Theory Explanation. |
Question 9 |
RST 7.5 interrupt in 8085 microprocessor executes the interrupt service routine from interrupt vector location
0000H | |
0075H | |
003CH | |
0034H |
→ 60 in hexa decimal is 003CH.
Question 10 |
Contents of A register after the execution of the following 8085 microprocessor program is
MVI A, 55 H MVI C, 25 H ADD C DAA
7AH | |
80H | |
50H | |
22H |
Question 11 |
The address space of 8086 CPU is
one Megabyte | |
256 Kilobytes | |
1 K Megabytes | |
64 Kilobytes |
Question 12 |
(a) Draw the schematic of an 8085 based system that can be used to measure the width of a pulse. Assume that the pulse is given as a TTL compatible signal by the source which generates it.
(b) Write the 8085 Assembly Language program to measure the width of the pulse. State all your assumption clearly.
Theory Explanation. |
Question 13 |
Design a 2K x 8 (2048 locations, each 8 bit wide) memory system mapped at addresses (1000)16 to (17FF)16 for the 8085 processor using four 1K x 4 memory chips. Each of these chips has the following signal pins:
- (i)

(ii)

(iii)

(iv) A0, A1, …A9(input address lines. A0 is the lest significant)
(v) D0, D1, D2, D3(bi-directional data lines. D0 is the least significant)
Theory Explanation. |
Question 14 |
To put the 8085 microprocessor in the wait state
lower the HOLD input | |
lower the READY input | |
raise the HOLD input | |
raise the READY input |
Question 15 |
The 8085 microprocessor responds to the present of an interrupt
as soon as the TRAP pin becomes ‘high’ | |
by checking the TRAP pin for ‘high’ status at the end of each instruction each | |
by checking the TRAP pin for ‘high’ status at the end of the execution of each instruction | |
by checking the TRAP pin for ‘high’ status at regular intervals |
Question 16 |
A low memory can be connected to 8085 by using
INTER | |
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HOLD | |
READY |
Question 17 |
A device employing INTR line for device interrupt puts the CALL instruction on the data bus while
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HOLD is active | |
READY is active | |
None of the above |