SequentialCircuits
Question 1 
Consider the sequential circuit shown in the figure, where both flipflops used are positive edgetriggered D flipflops.
The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is ______
2  
3  
4  
5 
Now lets draw characteristic table,
D_{1} = Q_{0}
D_{0} = in
Question 2 
Consider a combination of T and D flipflops connected as shown below. The output of the D flipflop is connected to the input of the T flipflop and the output of the T flipflop is connected to the input of the D flipflop.
Initially, both Q_{0} and Q_{1} are set to 1 (before the 1^{st} clock cycle). The outputs
Q_{1}Q_{0} after the 3^{rd} cycle are 11 and after the 4^{th} cycle are 00 respectively  
Q_{1}Q_{0} after the 3^{rd} cycle are 11 and after the 4^{th} cycle are 01 respectively  
Q_{1}Q_{0} after the 3^{rd} cycle are 00 and after the 4^{th} cycle are 11 respectively  
Q_{1}Q_{0} after the 3^{rd} cycle are 01 and after the 4^{th} cycle are 01 respectively 
Question 3 
The next state table of a 2bit saturating upcounter is given below.
The counter is built as a synchronous sequential circuit using T flipflops. The expressions for T_{1} and T_{0} are
By using above excitation table,
Question 4 
We want to design a synchronous counter that counts the sequence 010203 and then repeats. The minimum number of JK ﬂipﬂops required to implement this counter is __________.
4  
5  
6  
7 
There are 3 transitions from 0.
Hence ⌈log_{2}^{3}⌉ = 2 bits have to be added to the existing 2 bits to represent 4 unique states.
Question 5 
Consider a 4bit Johnson counter with an initial value of 0000. The counting sequence of this counter is
0, 1, 3, 7, 15, 14, 12, 8, 0  
0, 1, 3, 5, 7, 9, 11, 13, 15, 0  
0, 2, 4, 6, 8, 10, 12, 14, 0  
0, 8, 12, 14, 15, 7, 3, 1, 0 
The state sequence is 0,8,12,14,15,7,3,1,0.
Question 6 
A positive edgetriggered D flipflop is connected to a positive edgetriggered JK flipflop as follows. The Q output of the D flipflop is connected to both the J and K inputs of the JK flipflop, while the Q output of the JK flipflop is connected to the input of the D flipflop. Initially, the output of the D flipflop is set to logic one and the output of the JK flipflop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flipflop when the flipflops are connected to a freerunning common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the stateholding mode of the JK flipflop. Both the flipflops have nonzero propagation delays.
0110110...  
0100100...  
011101110...  
011001100... 
The characteristic equations are
Q_{DN}=D=Q_{JK}
The state table and state transition diagram are as follows:
Consider Q_{D}Q_{JK}=10 as initial state because in the options Q_{JK}=0 is the initial state of JK flipflop.
The state sequence is
0 → 1 → 1 → 0 → 1 → 1
∴ Option (a) is the answer.
Question 7 
The minimum number of JK flipflops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0,……) is ___________.
2  
3  
4  
5 
00
00
01
01
10
10
11
11
In the above sequence two flipflop's will not be sufficient. Since we are confronted with repeated sequence, we may add another bit to the above sequence.
000
100
001
101
010
110
011
111
Now and every count is unique, occurring only once.
So finally 3flip flops is required.
Question 8 
Let k = 2^{n}. A circuit is built by giving the output of an nbit binary counter as input to an nto2^{n} bit decoder. This circuit is equivalent to a
kbit binary up counter.  
kbit binary down counter.  
kbit ring counter.  
kbit Johnson counter. 
A n x 2^{n} decoder is a combinational circuit with only one output line has one and all others (2^{n}1) have zeros.
A nbit binary Counter produces outputs from 0 to 2^{n} i.e 000...00 to 111...11 and repeats.
The n x 2^{n} Decoder gets the input (000..00 to 111...11 ) from the binary counter and only one output line has one and rest have zeros.
This circuit is equivalent to a 2^{n}  bit ring counter.
Question 9 
The minimum number of D flipflops needed to design a mod258 counter is
9  
8  
512  
258 
The max Mod values is 2n.
So 2^{n} ≥ 258 ⇒ n = 9
Question 10 
Consider the following circuit involving three Dtype flipflops used in a certain type of counter configuration.
If all the flipflops were reset to O at power on, what is the total number of distinct outputs *states) represented by PQR generated by the counter?
3  
4  
5  
6 
So total no. of distinct output (states) are 4.
Question 11 
Consider the following circuit involving three Dtype flipflops used in a certain type of counter configuration.
If at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?
000  
001  
010  
011 
So, after 010 it moves to 011.
Question 12 
In the sequential circuit shown below,if the initial value of the output Q_{1}Q_{0} is 00,what are the next four values of Q_{1}Q_{0}?
11, 10, 01, 00  
10, 11, 01, 00  
10, 00, 01, 11  
11, 10, 00, 01 
The next four values of Q_{1}Q_{0} are 11, 10, 01, 00.
Question 13 
You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flipflops) will delay the phase of f by 180°?
50% of duty cycle means, the wave is 1 for half of the time and 0 for the other half of the time. It is a usual digital signal with 1 and 0.
The waveform f changes for every negative edge, that means f value alters from 1 to 0 or 0 to 1 for every negative edge of the clock.
Now the problem is that we need to find the circuit which produces a phase shift of 180, which means the output is 0 when f is 1 and output is 1 when f is 0.
Like the below image.
Now to find the answer we can choose elimination method.
F changes for negative edge, so that output too should change at negative edge. i.e if f becomes 0, then at the same time output should become 1, vice versa.
So, whenever input changes, at the same point of time output too should change. As input changes on negative edge, the output should be changed at negative edge only.
To have the above behaviour, the second D flipflop which produces the final output should be negative edge triggered. because whatever the 2nd flipflop produces, that is the output of the complete circuit.
So, we can eliminate option a, d.
Now either b or c can be answer.
How the flipflop chain works in option b and c is as below.
—> F changes at negative edge.
—> But flipflop1 responds at next positive edge.
—> After this flipflop2 responds at next negative edge.
That means flipflop2 produces the same input which is given to flipflop now after a positive edge and a negative edge, that means a delay of one clock cycle, which is 180 degrees phase shift for the waveform of f.
Option b) we are giving f’, so that the output is f’ with 180 degrees phase shift.
Option c) we are giving f, so that the output is f with 180 degrees phase shift.
Hence option C is the answer.
Question 14 
Consider the circuit in the diagram. The ⊕ operator represents ExOR. The D flipflops are initialized to zeroes (cleared).
The following data: 100110000 is supplied to the “data” terminal in nine clock cycles. After that the values of q2q1q0 are:
000  
001  
010  
101 
Question 15 
Consider the following circuit.
The flipflops are positive edge triggered D FFs. Each state is designated as a two bit string Q_{0}Q_{1}. Let the initial state be 00. The state transition sequence is:
Question 16 
In an SR latch made by crosscoupling two NAND gates, if both S and R inputs are set to 0, then it will result in
Q = 0, Q' = 1  
Q = 1, Q' = 0  
Q = 1, Q' = 1  
Indeterminate states 
Truth table for the SR latch by cross coupling two NAND gates is
So, Answer is Option (D).
Question 17 
Consider the partial implementation of a 2bit counter using T flipflops following the sequence 02310, as shown below
To complete the circuit, the input X should be
Q_{2}^{c}  
Q_{2} + Q_{1}  
(Q_{1} + Q_{2})^{c}  
Q_{1} ⊕ Q_{2} 
0  2  3  1  0
or
00  10  11  01  00
From the given sequence, we have state table as,
Now we have present state and next state, so we should use excitation table of T flipflop,
From state table,
T_{2} = Q_{2}⊙Q_{1} and T_{1} = Q_{2}⊕Q_{1}
X = T_{1} = Q_{2}⊕Q_{1}
Question 18 
A 1input, 2output synchronous sequential circuit behaves as follows:
Let z_{k}, n_{k} denote the number of 0's and 1's respectively in initial k bits of the input (z_{k} + n_{k} = k). The circuit outputs 00 until one of the following conditions holds.
• z_{k}  n_{k} = 2. In this case, the output at the kth and all subsequent clock ticks is 10. • n_{k}  z_{k} = 2. In this case, the output at the kth and all subsequent clock ticks is 01.
What is the minimum number of states required in the state transition graph of the above circuit?
5  
6  
7  
8 
q_{0} ← Number of zeros is one more than number of ones.
q_{1} ← Number of ones is one more than number of zeros.
q_{00} ← Number of zeros is two more than number of ones.
q_{11} ← Number of ones is two more than number of zeros.
Question 19 
Consider the following circuit with initial state Q_{0} = Q_{1} = 0. The D Flipflops are positive edged triggered and have set up times 20 nanosecond and hold times 0.
Consider the following timing diagrams of X and C; the clock period of C <= 40 nanosecond. Which one is the correct plot of Y?
Given clock is +edge triggered.
See the first positive edge. X is 0, and hence the output is 0, because
Y = Q_{1N} = D_{1}×Q_{0}' = 0⋅Q_{0}' = 0
At second +edge, X is 1 and Q_{0}' is also 1. So output is 1 (when second +ve edge of the clock arrives, Q_{0}' would surely be 1 because the setup time of flip flop is given as 20ns and clock period is ≥ 40ns).
At third +ve edge, X is 1 and Q_{0}' is 0, so output is 0.
Now output never changes back to 1 as Q_{0}' is always 0 and when Q_{0}' finally becomes 1, X is 0.
Hence option (A) is the correct answer.
Question 20 
Consider the circuit given below with initial state Q_{0} = 1, Q_{1} = Q_{2} = 0. The state of the circuit is given by the value 4Q_{2} + 2Q_{1} + Q_{0}
Which one of the following is the correct state sequence of the circuit?
1,3,4,6,7,5,2  
1,2,5,3,7,6,4  
1,2,7,3,5,6,4  
1,6,5,7,2,3,4 
Question 21 
A sequential circuit takes an input stream of 0’s and 1’s and produces an output stream of 0’s and 1’s. Initially it replicates the input on its output until two consecutive 0’s are encountered on the input. From then onward, it produces an output stream, which is the bitwise complement of input stream until it encounters two consecutive 1’s, whereupon the process repeats. An example of input and output stream is shown below.
The input stream: 101100 01001011 0 11 The desired output: 101100 10110100 0 11
JK masterslave flipflops are to be used to design the circuit.
(a) Give the state transition diagram.
(b) Give the minimized sumofproduct expression for J and K inputs of one of its
state flipflops.
Theory Explanation is given below. 
Question 22 
The following arrangement of masterslave flip flops
has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),
1, 0  
1, 1  
0, 0  
0, 1 
When 11 is applied to Jk flip flop it toggles the value of P so op at P will be 1.
Input to D flip flop will be 0(initial value of P) so op at Q will be 0.
Question 23 
Start and stop bits do not contain an ‘information’ but are used in serial communication for
Error detection  
Error correction  
Synchronization  
Slowing down the communications 
Question 24 
Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: Advantage of synchronous sequential circuits over asynchronous ones is:
faster operation  
ease of avoiding problems due to hazards  
lower hardware requirement  
better noise immunity
 
none of the above

Question 25 
The above circuit produces the output sequence:
1111 1111 0000 0000  
1111 0000 1111 000  
1111 0001 0011 010  
1010 1010 1010 1010 
So we can draw below table to get the output Q_{3}.
From the above table Q_{3} that is output is 1111 0001 0011 010.
So, answer is (C).
Question 26 
Consider the following state diagram and its realization by a JK flip flop The combinational circuit generates J and K in terms of x, y and Q. The Boolean expressions for J and K are:
(x⊕y)’ and x’⊕y’  
(x⊕y)’ and x⊕y  
x⊕y and (x⊕y)’  
x⊕y and x⊕y 
Excitation table of JK:
Question 27 
Which of the following input sequences for a crosscoupled RS flipflop realized with two NAND gates may lead to an oscillation?
11, 00  
01, 10  
10, 01  
00, 11 
So, 00 input cause indeterminate state which may lead to oscillation.
Question 28 
How many pulses are needed to change the contents of a 8bit up counter from 10101100 to 00100111 (rightmost bit is the LSB)?
134  
133  
124  
123 
→ First counter is move from 172 to 255 = 83 pulses
→ 255 to 0 = 1 pulse
→ 0 to 39 = 39 pulses
Total = 83 + 1 + 39 = 123 pulses
Question 29 
Which of the following input sequences will always generate a 1 at the output Z at the end of the third cycle?
000 101 111  
101 110 111  
011 101 111  
001 110 111  
None of these 
While filling done in reverse order, all operations are not satisfied.
Question 30 
A line L in a circuit is said to have a stuckat0 fault if the line permanently has a logic value 0. Similarly a line L in a circuit is said to have a stuckat1 fault if the line permanently has a logic value 1. A circuit is said to have a multiple stuckat fault if one or more lines have stuck at faults. The total number of distinct multiple stuckat faults possible in a circuit with N lines is
3^{N}  
3^{N}  1  
2^{N}  1  
2 
This is because the total possible combinations (i.e., a line may either be at fault (in 2 ways i.e., stuck at 0 or 1) or it may not be, so there are only 3 possibilities for a line) is 3^{N}. In only one combination the circuit will have all lines to be correct (i.e., not a fault). Hence, total combinations in which distinct multiple stuckatfaults possible in a circuit with N lines is 3^{N}  1.
Question 31 
The circuit shown below implements a 2input NOR gate using two 24 MUX (control signal 1 selects the upper input). What are the values of signals x, y and z?
1, 0, B  
1, 0, A  
0, 1, B  
0, 1, A 
g = Ax + Bz'
In MUX2, the equation is
f = xg + yg'
= x(Az+Bz') + y(Az+Bz')'
Function f should be equal to (A+B)'.
Just try to put the values of option (D), i.e., x=0, y=1, z=A,
f = 0(AA+BA') +1(AA+BA')'
= (A+B)'
∴ Option (D) is correct.
Question 32 
Q = 0, Q’ = 1  
Q = 1, Q’ = 0  
Q = 1, Q’ = 1  
Indeterminate states 
Question 33 
Toggle Switch  
Latch  
Stepping Switch  
SR flip flop 
There are two types of ring counters:
1. A straight ring counter, also known as a onehot counter, connects the output of the last shift register to the first shift register input and circulates a single one (or zero) bit around the ring.
2. A twisted ring counter, also called switchtail ring counter, walking ring counter, Johnson counter, or Möbius counter, connects the complement of the output of the last shift register to the input of the first register and circulates a stream of ones followed by zeros around the ring.
Note: Ring counter is analogous to Stepping Switch
Question 34 
entirely different  
identical  
complementary  
dual 
The Two functions are entirely different as:
Figure 1: The logic gates derive the following function:
F1 = ((X + Y')' + X)'
= ((X + Y')')'. X'
= (X + Y'). X'
= XX' + X'Y'
= X'Y'
Figure 2: It is simple AND gate which has 1 input already complimented.
F2 = XY'
So, these two functions are entirely different.
Question 35 
1  
0  
X  
X’ 
Question 36 
Lower hardware requirement  
Better noise immunity  
Faster operation  
None of the above 
Question 37 
JK Flipflop is faster than SR flipflop  
JK flipflop has a feedback path  
JK flipflop accepts both inputs 1  
None of them 
> JK flip flop doesn’t have a feedback path.
Question 38 
What are the values of Q_{0 }and Q_{1} after 4 clock cycles if the initial values are ?
11  
01  
10  
00 
Question 39 
What does the following logic diagram represent ?
Synchronous Counter  
Ripple Counter
 
Combinational Circuit
 
Mod 2 Counter 
→ All subsequent flipflops are clocked by the output of the preceding flipflop. Asynchronous counters are also called ripplecounters because of the way the clock pulse ripples it way through the flipflops.
→ The MOD of the ripple counter or asynchronous counter is 2^{n} if n flipflops are used.
Question 40 
1  
0  
Don't care  
none of the above 
That captured value becomes the Q output. At other times, the output Q does not change.
The D flipflop can be viewed as a memory cell, a zeroorder hold, or a delay line.
Truth Table for the Dtype Flip Flop:
Step1: D flip flop is nothing data flip flop. It will return what we are given in input.
Step2: In this question, the LSB and MSB are 1. So final output is 1.
Note: Here, we don’t know what order they are given input.
Question 41 
4  
5  
6  
8 
Question 42 
D type flipflop  
T type flipflop  
SR flip flop  
Toggle switch 
Question 43 
3  
5  
7  
8 
N<= 2 ^{n}
Hence,
For a mod 10 counter, 10< 2 ^{4} . So 4 flip flops are required.
For a mod 16 counter, 16=2^{ 4} . So again 4 flip flops are required.
For a mod 32 counter, 32=2 ^{5} . So 5 flip flops are required.
Question 44 
nT sec  
(n1)T sec  
n/Tsec  
(2n1)T sec 
The data can be shifted one position towards left or right in each clock.
Consider right shift operation.
Initially, data in LSB position is read or accessed.
After each shift the next significant bit moves to LSB position and the bit in LSB is read.
After n1 shifts i.e after T(n1) seconds, the last element moves to LSB position.
Question 45 
0  
1  
2  
3 
Question 46 
presents inputs only  
past inputs only  
both present and past inputs  
present outputs only 
Question 47 
clock input of all flipflops  
clock input of one flip flops  
J and K inputs of all flip flops  
J and K inputs of one flipflop 
Question 48 
1  
0  
Don't Care  
none of Above 
Step2: In this question, the LSB and MSB are 1. So final output is 1.
Note: Here, we don’t know what order they are given input.
Question 49 
10 flipflops  
12 flipflops  
8 flipflops  
6 flipflops 
The “MODULO” or “MODULUS” of a counter is the number of states the counter counts or sequences through before repeating itself and a ring counter can be made to output any modulo number. A “modn” ring counter will require “n” number of flipflops connected together to circulate a single data bit providing “n” different output states
So, modulus12 requires , 12 flipflops.
Question 50 
Clock input of all flip flops  
J and K input of one flip flop  
J and K input of all flip flops  
Clock input of one flip flops 
Question 51 
m+n  
m+2n  
2m+n  
2m+2n 
Question 52 
SR flip flop with inputs X=R and Y=S  
SR flip flop with inputs X=S and Y=R  
JK flip flop with inputs X=J and Y=K  
JK flip flop with X=k and Y=J 
PS=Present state
NS=Next State
Q _{n+1} =D=f(PI,PS)=f(x,y,Q_{ n} )
D=X’Z+YZ
Question 53 
R=10 ns, S=40ns  
R=40ns, S=10ns  
R=10ns, S=30ns  
R=30 ns, S=10ns 
● Synchronous Counters are so called because the clock input of all the individual flipflops within the counter are all clocked together at the same time by the same clock signal.
● In the ripple counter, each flip flop will depending upon the precede flip flop and propagation delay is 10ns.So the propagation delay of 4bit ripple counter is 4*10=40ns.
● In the synchronous counter,one clock input is enough so the propagation delay is 10ns.
Question 54 
One clock pulse  
One clock pulse for each 1 in the data  
Eight clock pulses  
One clock pulse for each 0 in the data 
Question 55 
T flip flop
 
JK flip flop  
ClockedRS flip flop  
Clocked D flip flop 
Question 56 
SR flip flop with inputs X=R and Y=S  
SR flip flop with inputs X=S and Y=R  
JK flip flop with inputs X=J and Y=K  
JK flip flop with X=k and Y=J 
PS=Present state
NS=Next State
Q _{n+1} =D=f(PI,PS)=f(x,y,Q_{ n} )
D=X’Z+YZ
Question 57 
R=10 ns, S=40ns  
R=40ns, S=10ns  
R=10ns, S=30ns  
R=30 ns, S=10ns 
→ In Ripple counter (or) Asynchronous counter each flip flop waits for its previous flip flops output.
R= bit size*propagation delay
= 4*10ns
= 40ns
→ In Synchronous counter all flip flops are triggered by same clock. It will gives output of all four flip flops at the same time.
S=10ns
Question 58 
Clock input of all flip flops  
j and K input of one flip flop  
J and K input of all flip flops  
Clock input of one flip flops 
→ All subsequent flipflops are clocked by the output of the preceding flipflop. Asynchronous counters are also called ripplecounters because of the way the clock pulse ripples it way through the flipflops.
So, answer is clock input of one flipflop.
Question 59 
no change  
low state  
high state  
toggle state 
Question 60 
R=0,S=0  
R=0,S=1  
R=1,S=0  
R=1,S=1 
→Race around condition in digital circuits occur when the final state of the output depends on how the inputs arrive.
→The 'function' is in the S=1 R=1 input, the memory situation. The state of the FF depends on which state came before the 11, if it was 01 the FF is in Q=1 state, if it was 10 the FF is in the Q=0 state. This is the classical memory effect of a FF.
Question 61 
I. J _{0} = K _{0} = 0
II. J _{0} = K _{0} = 1
III. J _{1} = K _{1} = Q _{0}
IV. J _{1} = K _{1} =Q’_{0}
V. J _{2} = K _{2} = Q _{1} Q_{ 0}
VI. J _{2} = K_{ 2} = Q’_{ 1} Q’_{ 0}
I,III,V  
I,IV,VI  
II,III,V  
II,IV,VI 
State sequence of down counter is as follows:
Question 62 
Combinational logic circuits  
Synchronous sequential logic circuits  
Asynchronous sequential logic circuits working in the fundamental mode  
Asynchronous sequential logic circuits working in the pulse mode 
→ Asynchronous circuits is called essential hazard is caused by unequal delays along two or more paths that originate from the same same input.
→ It cannot be corrected by adding redundant gates and it can only be corrected by adjusting the amount of delay in the affected path.
Question 63 
Q _{n+1} =T Q _{n} + T Q _{n}  
Q _{n+1} =T+Q _{n}  
Q _{n+1} =TQ_{ n}  
Q_{ n+1} = T Q_{ n} 
TFlipFlop Characteristic Table:
TFlipFlop Characteristic equation:
Q _{next} = TQ' + T'Q
Question 64 
JK flipflop  
Dflipflop  
T flipflop  
None of these 
Question 65 
Not option given  
Q=D  
Q=1  
Q=0  
Q _{t+1} =D 
Q t+1 = DQ' + DQ
Q t+1 =D
Question 66 
S = 0, R = 0  
S = 0, R = 1  
S = 1, R = 0  
S = 1, R = 1 
Question 67 
2  
3  
4  
10 
Question 68 
AND and OR gates  
AND gates  
NAND and NOR gates  
NAND gates 
Question 69 
faster operation  
ease of avoiding problems due to hazard  
lower hardware requirement  
better noise immunity  
None of the above 
Note: Excluded for evaluation.
Question 70 
Q_{n+1} = J.Q_{n} +K.Q_{n}  
Q_{n+1} = J.Q'_{n} +K'Q_{n}  
Q_{n+1}= Q_{n}J.K  
Q_{n+1}= (J+K)Q_{n} 
Question 71 
18  
9  
5  
4 
Let K = Number of states =18.
Number of flipflops is the smallest number which is greater than or equal to L log_{2}K
log_{2}18 = 4.1.
L=5>=4.1.
So number of flipflops needed is 5.
Question 72 
Q=1  
Q=0  
Q= D’  
Q=D 
Question 73 
Q_{N+1} = TQ_{N}  
Q_{N+1} = T+Q_{N}  
Q_{N+1} = TQ_{N}  
Q_{N+1}=T'Q_{N} 
Question 74 
18  
9  
5  
4 
Let K = Number of states =18.
Number of flipflops is the smallest number which is greater than or equal to Log K ( base 2).
Log 18 = 4.1.
L=5>=4.1.
So number of flipflops needed is 5.
Question 75 
1MHz  
10MHz  
100MHz  
4MHz 
Frequency = 1/ Time
Binary counter is ripple counter where the output one flip flop is clock input to next flip flop.
So, maximum delay(time)= 4*25ns = 100 ns.
frequency= 1/100 ns
= 10 MHz.
Question 76 
Multiplexer  
Decoder  
Counter  
Full adder 
Examples: Encoder, Decoder, Multiplexer, Demultiplexer
Sequential circuits have memory. Sequential circuits are those which are dependent on clock cycles and depends on present as well as past inputs to generate any output.
Example: Flipflops, Counters
Question 77 
Synchronous Counter  
Asynchronous counter  
Parallel counter  
None of the above 
Question 78 
5  
10  
15  
20 
Given mod values are 2 and 5
= 2*5
= 10
Question 79 
8  
9  
27  
11 
So total number of states possible is 2 ^{n} i.e. MOD 2^{ n} .
Here 2^{ n} = 272
So n = log_{ 2} 272
n = 9
Question 80 
Johnson counter is a synchronous counter  
Ripple counter is an asynchronous counter.  
Asynchronous counters are slower than synchronous counters.  
A counter may count up or count down, but cannot count both up and down. 
→Counters are of two types depending upon clock pulse applied. These counters are: Asynchronous counter and Synchronous counter.
→In Asynchronous Counter { also known as Ripple counter} different flip flops are triggered with different clock, not simultaneously!
→While in Synchronous Counter, all flip flops are triggered with same clock simultaneously ; Synchronous Counter is faster than Asynchronous counter in operation.
→Synchronous Counter : →Synchronous Counter does not produce any decoding errors.
→Synchronous Counter is also called Serial Counter.
→Synchronous Counter will operate in any desired count sequence.
→In Synchronous Counter designing as well implementation are complex due to increasing the number of states.
→Synchronous Counter examples are: Ring counter , Johnson Counter, etc.
→Asynchronous Counters :
→Asynchronous Counter produces decoding error.
→Asynchronous Counter is also called Parallel Counter.
→Asynchronous Counter will operate only in fixed count sequence (UP/DOWN).
→In Asynchronous Counter designing as well as implementation is very easy.
→Asynchronous Counter examples are: Ripple UP counter, Ripple DOWN counter, etc.
Question 81 
20 ns  
320 ns  
36 ns  
16 ns 
Question 82 
MOD7 Counter  
MOD6 Counter  
MOD8 Counter  
MOD4 Counter 
→ CLR is asynchronous input pin.
→ If CLR=1, all flipflop outputs are reset to ‘0’.
→ When counter will start counting, it will count from 0 to 5 and at 6th clock, flipflop output are cleared.
→ Hence given counter is MOD6 counter.
Question 83 
Which of the following expresses the next state in terms of X, Y, current state?
(X’ ∧ Q’) ∨ (Y’ ∧ Q)  
(X’ ∧ Q) v (Y’ ∧ Q’)  
(X ∧ Q’) v (Y ∧ Q)  
(X ∧ Q’) v (Y’ ∧ Q) 
Question 84 
Which of the following flipflops is free from race around problem?
D flipflop  
T flipflop
 
SR flipflop
 
Masterslave JK flipflop 
During high clock when ever applied input changes the output also changes. But in JK flip flop when j=k=1 , without any change in the input the output changes , this condition is called a race around condition. The circuit accepts input data when the clock signal is “HIGH”, and passes the data to the output on the fallingedge of the clock signal. In other words, the MasterSlave JK Flip flop is a “Synchronous” device as it only passes data with the timing of the clock signal.
Question 85 
How many flipflops are required mod – 16 counters?
5  
6  
3  
4 
So log_{2} 16=4.
Question 86 
In D flip flop the output state Q is related with D input in what way?
Q is dependent of D
 
Q is same as D  
Q is independent of D
 
Q is complement of D

Question 87 
A negative edge triggered flip flop transfers data from input on the:
LOW to HIGH transition of clock pulse
 
BEFORE transition of clock pulse
 
HIGH to LOW transition of clock pulse
 
WITHOUT transition of clock pulse

Question 88 
Tell the time of the day  
Tell how much time has elapsed since the system was turned on
 
Carry serial data signals  
Synchronize events in various parts of system 
Question 89 
Qtype flipflop  
RS flipflop  
JK flipflop  
T flipflop 
Note that T flipflop is 1 input flip flop and not two input flip flop.