Sequential-Circuits
Question 1 |
Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops.
The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is ______
2 | |
3 | |
4 | |
5 |
Question 1 Explanation:
Let,
Now lets draw characteristic table,
D1 = Q0
D0 = in
Now lets draw characteristic table,
D1 = Q0
D0 = in
Question 2 |
Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop.
Initially, both Q0 and Q1 are set to 1 (before the 1st clock cycle). The outputs
Q1Q0 after the 3rd cycle are 11 and after the 4th cycle are 00 respectively | |
Q1Q0 after the 3rd cycle are 11 and after the 4th cycle are 01 respectively | |
Q1Q0 after the 3rd cycle are 00 and after the 4th cycle are 11 respectively | |
Q1Q0 after the 3rd cycle are 01 and after the 4th cycle are 01 respectively |
Question 2 Explanation:
Question 3 |
The next state table of a 2-bit saturating up-counter is given below.
The counter is built as a synchronous sequential circuit using T flip-flops. The expressions for T1 and T0 are
 | |
 | |
 | |
 |
Question 3 Explanation:
By using above excitation table,
Question 4 |
We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is __________.
4 | |
5 | |
6 | |
7 |
Question 4 Explanation:
Given sequence is 0-1-0-2-0-3
There are 3 transitions from 0.
Hence ⌈log23⌉ = 2 bits have to be added to the existing 2 bits to represent 4 unique states.
There are 3 transitions from 0.
Hence ⌈log23⌉ = 2 bits have to be added to the existing 2 bits to represent 4 unique states.
Question 5 |
Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is
0, 1, 3, 7, 15, 14, 12, 8, 0 | |
0, 1, 3, 5, 7, 9, 11, 13, 15, 0 | |
0, 2, 4, 6, 8, 10, 12, 14, 0 | |
0, 8, 12, 14, 15, 7, 3, 1, 0 |
Question 5 Explanation:
In a Johnson’s counter LSB is complemented and a circular right shift operation has to be done to get the next state.
The state sequence is 0,8,12,14,15,7,3,1,0.
The state sequence is 0,8,12,14,15,7,3,1,0.
Question 6 |
A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flipflop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.
0110110... | |
0100100... | |
011101110... | |
011001100... |
Question 6 Explanation:
The circuit for the given data is
The characteristic equations are
QDN=D=QJK
The state table and state transition diagram are as follows:
Consider QDQJK=10 as initial state because in the options QJK=0 is the initial state of JK flip-flop.
The state sequence is
0 → 1 → 1 → 0 → 1 → 1
∴ Option (a) is the answer.
The characteristic equations are
QDN=D=QJK
The state table and state transition diagram are as follows:
Consider QDQJK=10 as initial state because in the options QJK=0 is the initial state of JK flip-flop.
The state sequence is
0 → 1 → 1 → 0 → 1 → 1
∴ Option (a) is the answer.
Question 7 |
The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0,……) is ___________.
2 | |
3 | |
4 | |
5 |
Question 7 Explanation:
Count sequence mentioned is
00
00
01
01
10
10
11
11
In the above sequence two flip-flop's will not be sufficient. Since we are confronted with repeated sequence, we may add another bit to the above sequence.
000
100
001
101
010
110
011
111
Now and every count is unique, occurring only once.
So finally 3-flip flops is required.
00
00
01
01
10
10
11
11
In the above sequence two flip-flop's will not be sufficient. Since we are confronted with repeated sequence, we may add another bit to the above sequence.
000
100
001
101
010
110
011
111
Now and every count is unique, occurring only once.
So finally 3-flip flops is required.
Question 8 |
Let k = 2n. A circuit is built by giving the output of an n-bit binary counter as input to an n-to-2n bit decoder. This circuit is equivalent to a
k-bit binary up counter. | |
k-bit binary down counter. | |
k-bit ring counter. | |
k-bit Johnson counter. |
Question 8 Explanation:
A ring counter is a circular shift register with only one flip-flop being set at any particular time and all others are cleared.
A n x 2n decoder is a combinational circuit with only one output line has one and all others (2n-1) have zeros.
A n-bit binary Counter produces outputs from 0 to 2n i.e 000...00 to 111...11 and repeats.
The n x 2n Decoder gets the input (000..00 to 111...11 ) from the binary counter and only one output line has one and rest have zeros.
This circuit is equivalent to a 2n - bit ring counter.
A n x 2n decoder is a combinational circuit with only one output line has one and all others (2n-1) have zeros.
A n-bit binary Counter produces outputs from 0 to 2n i.e 000...00 to 111...11 and repeats.
The n x 2n Decoder gets the input (000..00 to 111...11 ) from the binary counter and only one output line has one and rest have zeros.
This circuit is equivalent to a 2n - bit ring counter.
Question 9 |
The minimum number of D flip-flops needed to design a mod-258 counter is
9 | |
8 | |
512 | |
258 |
Question 9 Explanation:
Let n is the number of flip-flops.
The max Mod values is 2n.
So 2n ≥ 258 ⇒ n = 9
The max Mod values is 2n.
So 2n ≥ 258 ⇒ n = 9
Question 10 |
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.
If all the flip-flops were reset to O at power on, what is the total number of distinct outputs *states) represented by PQR generated by the counter?
3 | |
4 | |
5 | |
6 |
Question 10 Explanation:
So total no. of distinct output (states) are 4.
Question 11 |
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.
If at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?
000 | |
001 | |
010 | |
011 |
Question 11 Explanation:
So, after 010 it moves to 011.
Question 12 |
In the sequential circuit shown below,if the initial value of the output Q1Q0 is 00,what are the next four values of Q1Q0?
11, 10, 01, 00 | |
10, 11, 01, 00 | |
10, 00, 01, 11 | |
11, 10, 00, 01 |
Question 12 Explanation:
The next four values of Q1Q0 are 11, 10, 01, 00.
Question 13 |
You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of f by 180°?
 | |
 | |
 | |
 |
Question 13 Explanation:
Duty cycle is the period of time where the signal high, i.e. 1.
50% of duty cycle means, the wave is 1 for half of the time and 0 for the other half of the time. It is a usual digital signal with 1 and 0.
The waveform f changes for every negative edge, that means f value alters from 1 to 0 or 0 to 1 for every negative edge of the clock.
Now the problem is that we need to find the circuit which produces a phase shift of 180, which means the output is 0 when f is 1 and output is 1 when f is 0.
Like the below image.
Now to find the answer we can choose elimination method.
F changes for negative edge, so that output too should change at negative edge. i.e if f becomes 0, then at the same time output should become 1, vice versa.
So, whenever input changes, at the same point of time output too should change. As input changes on negative edge, the output should be changed at negative edge only.
To have the above behaviour, the second D flip-flop which produces the final output should be negative edge triggered. because whatever the 2nd flip-flop produces, that is the output of the complete circuit.
So, we can eliminate option a, d.
Now either b or c can be answer.
How the flip-flop chain works in option b and c is as below.
—> F changes at negative edge.
—> But flip-flop1 responds at next positive edge.
—> After this flip-flop2 responds at next negative edge.
That means flip-flop2 produces the same input which is given to flip-flop now after a positive edge and a negative edge, that means a delay of one clock cycle, which is 180 degrees phase shift for the waveform of f.
Option b) we are giving f’, so that the output is f’ with 180 degrees phase shift.
Option c) we are giving f, so that the output is f with 180 degrees phase shift.
Hence option C is the answer.
50% of duty cycle means, the wave is 1 for half of the time and 0 for the other half of the time. It is a usual digital signal with 1 and 0.
The waveform f changes for every negative edge, that means f value alters from 1 to 0 or 0 to 1 for every negative edge of the clock.
Now the problem is that we need to find the circuit which produces a phase shift of 180, which means the output is 0 when f is 1 and output is 1 when f is 0.
Like the below image.
Now to find the answer we can choose elimination method.
F changes for negative edge, so that output too should change at negative edge. i.e if f becomes 0, then at the same time output should become 1, vice versa.
So, whenever input changes, at the same point of time output too should change. As input changes on negative edge, the output should be changed at negative edge only.
To have the above behaviour, the second D flip-flop which produces the final output should be negative edge triggered. because whatever the 2nd flip-flop produces, that is the output of the complete circuit.
So, we can eliminate option a, d.
Now either b or c can be answer.
How the flip-flop chain works in option b and c is as below.
—> F changes at negative edge.
—> But flip-flop1 responds at next positive edge.
—> After this flip-flop2 responds at next negative edge.
That means flip-flop2 produces the same input which is given to flip-flop now after a positive edge and a negative edge, that means a delay of one clock cycle, which is 180 degrees phase shift for the waveform of f.
Option b) we are giving f’, so that the output is f’ with 180 degrees phase shift.
Option c) we are giving f, so that the output is f with 180 degrees phase shift.
Hence option C is the answer.
Question 14 |
Consider the circuit in the diagram. The ⊕ operator represents Ex-OR. The D flipflops are initialized to zeroes (cleared).
The following data: 100110000 is supplied to the “data” terminal in nine clock cycles. After that the values of q2q1q0 are:
000 | |
001 | |
010 | |
101 |
Question 14 Explanation:
q0N = Data, q1N = q0q22N = q1
Question 15 |
Consider the following circuit.
The flip-flops are positive edge triggered D FFs. Each state is designated as a two bit string Q0Q1. Let the initial state be 00. The state transition sequence is:
 | |
 | |
 | |
 |
Question 15 Explanation:
Question 16 |
In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in
Q = 0, Q' = 1 | |
Q = 1, Q' = 0 | |
Q = 1, Q' = 1 | |
Indeterminate states |
Question 16 Explanation:
Truth table for the SR latch by cross coupling two NAND gates is
So, Answer is Option (D).
Question 17 |
Consider the partial implementation of a 2-bit counter using T flip-flops following the sequence 0-2-3-1-0, as shown below
To complete the circuit, the input X should be
Q2c | |
Q2 + Q1 | |
(Q1 + Q2)c | |
Q1 ⊕ Q2 |
Question 17 Explanation:
Sequence given is
0 - 2 - 3 - 1 - 0
or
00 - 10 - 11 - 01 - 00
From the given sequence, we have state table as,
Now we have present state and next state, so we should use excitation table of T flip-flop,
From state table,
T2 = Q2⊙Q1 and T1 = Q2⊕Q1
X = T1 = Q2⊕Q1
0 - 2 - 3 - 1 - 0
or
00 - 10 - 11 - 01 - 00
From the given sequence, we have state table as,
Now we have present state and next state, so we should use excitation table of T flip-flop,
From state table,
T2 = Q2⊙Q1 and T1 = Q2⊕Q1
X = T1 = Q2⊕Q1
Question 18 |
A 1-input, 2-output synchronous sequential circuit behaves as follows:
Let zk, nk denote the number of 0's and 1's respectively in initial k bits of the input (zk + nk = k). The circuit outputs 00 until one of the following conditions holds.
• zk - nk = 2. In this case, the output at the k-th and all subsequent clock ticks is 10. • nk - zk = 2. In this case, the output at the k-th and all subsequent clock ticks is 01.
What is the minimum number of states required in the state transition graph of the above circuit?
5 | |
6 | |
7 | |
8 |
Question 18 Explanation:
Let q is the initial state.
q0 ← Number of zeros is one more than number of ones.
q1 ← Number of ones is one more than number of zeros.
q00 ← Number of zeros is two more than number of ones.
q11 ← Number of ones is two more than number of zeros.
q0 ← Number of zeros is one more than number of ones.
q1 ← Number of ones is one more than number of zeros.
q00 ← Number of zeros is two more than number of ones.
q11 ← Number of ones is two more than number of zeros.
Question 19 |
Consider the following circuit with initial state Q0 = Q1 = 0. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.
Consider the following timing diagrams of X and C; the clock period of C <= 40 nanosecond. Which one is the correct plot of Y?
 | |
 | |
 | |
 |
Question 19 Explanation:
Given clock is +edge triggered.
See the first positive edge. X is 0, and hence the output is 0, because
Y = Q1N = D1×Q0' = 0⋅Q0' = 0
At second +edge, X is 1 and Q0' is also 1. So output is 1 (when second +ve edge of the clock arrives, Q0' would surely be 1 because the setup time of flip flop is given as 20ns and clock period is ≥ 40ns).
At third +ve edge, X is 1 and Q0' is 0, so output is 0.
Now output never changes back to 1 as Q0' is always 0 and when Q0' finally becomes 1, X is 0.
Hence option (A) is the correct answer.
Question 20 |
Consider the circuit given below with initial state Q0 = 1, Q1 = Q2 = 0. The state of the circuit is given by the value 4Q2 + 2Q1 + Q0
Which one of the following is the correct state sequence of the circuit?
1,3,4,6,7,5,2 | |
1,2,5,3,7,6,4 | |
1,2,7,3,5,6,4 | |
1,6,5,7,2,3,4 |
Question 20 Explanation:
Question 21 |
A sequential circuit takes an input stream of 0’s and 1’s and produces an output stream of 0’s and 1’s. Initially it replicates the input on its output until two consecutive 0’s are encountered on the input. From then onward, it produces an output stream, which is the bit-wise complement of input stream until it encounters two consecutive 1’s, whereupon the process repeats. An example of input and output stream is shown below.
The input stream: 101100 01001011 0 11 The desired output: 101100 10110100 0 11
J-K master-slave flip-flops are to be used to design the circuit.
(a) Give the state transition diagram.
(b) Give the minimized sum-of-product expression for J and K inputs of one of its
state flip-flops.
Theory Explanation is given below. |
Question 21 Explanation:
Question 22 |
The following arrangement of master-slave flip flops
has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),
1, 0 | |
1, 1 | |
0, 0 | |
0, 1 |
Question 22 Explanation:
Here clocks are applied to both flip flops simultaneously.
When 11 is applied to Jk flip flop it toggles the value of P so op at P will be 1.
Input to D flip flop will be 0(initial value of P) so op at Q will be 0.
When 11 is applied to Jk flip flop it toggles the value of P so op at P will be 1.
Input to D flip flop will be 0(initial value of P) so op at Q will be 0.
Question 23 |
Design a synchronous counter to go through the following states:
1, 4, 2, 3, 1, 4, 2, 3, 1, 4,...........
Theory Explanation. |
Question 24 |
Consider the synchronous sequential circuit in the below figure.
(a) Draw a state diagram, which is implemented by the circuit. Use the following names for the states corresponding to the values of flip-flops as given below.
(b) Given that the initial state of the circuit is S4, identify the set of states, which are not reachable.
Theory Explanation. |
Question 25 |
Start and stop bits do not contain an ‘information’ but are used in serial communication for
Error detection | |
Error correction | |
Synchronization | |
Slowing down the communications |
Question 25 Explanation:
The start and stop bits are used to synchronize the serial receivers.
Question 26 |
Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: Advantage of synchronous sequential circuits over asynchronous ones is:
faster operation | |
ease of avoiding problems due to hazards | |
lower hardware requirement | |
better noise immunity
| |
none of the above
|
Question 26 Explanation:
In synchronization, there is a less chance of hazards but it can increase the delay. Then the advantage is ease of avoiding problems due to hazards.
Question 27 |
The above circuit produces the output sequence:
1111 1111 0000 0000 | |
1111 0000 1111 000 | |
1111 0001 0011 010 | |
1010 1010 1010 1010 |
Question 27 Explanation:
Let us suppose initially output of all JK flip flop is 1.
So we can draw below table to get the output Q3.
From the above table Q3 that is output is 1111 0001 0011 010.
So, answer is (C).
So we can draw below table to get the output Q3.
From the above table Q3 that is output is 1111 0001 0011 010.
So, answer is (C).
Question 28 |
Consider the following state diagram and its realization by a JK flip flop
The combinational circuit generates J and K in terms of x, y and Q.
The Boolean expressions for J and K are:
(x⊕y)’ and x’⊕y’ | |
(x⊕y)’ and x⊕y | |
x⊕y and (x⊕y)’ | |
x⊕y and x⊕y |
Question 28 Explanation:
From the given statement:
Excitation table of JK:
Excitation table of JK:
Question 29 |
Which of the following input sequences for a cross-coupled R-S flip-flop realized with two NAND gates may lead to an oscillation?
11, 00 | |
01, 10 | |
10, 01 | |
00, 11 |
Question 29 Explanation:
RS slip-flop using NAND gates.
So, 00 input cause indeterminate state which may lead to oscillation.
So, 00 input cause indeterminate state which may lead to oscillation.
Question 30 |
How many pulses are needed to change the contents of a 8-bit up counter from 10101100 to 00100111 (rightmost bit is the LSB)?
134 | |
133 | |
124 | |
123 |
Question 30 Explanation:
The 8 bit counter will be 0-255 to move from 10101100 (172) to 1000111 (39).
→ First counter is move from 172 to 255 = 83 pulses
→ 255 to 0 = 1 pulse
→ 0 to 39 = 39 pulses
Total = 83 + 1 + 39 = 123 pulses
→ First counter is move from 172 to 255 = 83 pulses
→ 255 to 0 = 1 pulse
→ 0 to 39 = 39 pulses
Total = 83 + 1 + 39 = 123 pulses
Question 31 |
Which of the following input sequences will always generate a 1 at the output Z at the end of the third cycle?
000 101 111 | |
101 110 111 | |
011 101 111 | |
001 110 111 | |
None of these |
Question 31 Explanation:
While filling done in reverse order, all operations are not satisfied.
Question 32 |
A line L in a circuit is said to have a stuck-at-0 fault if the line permanently has a logic value 0. Similarly a line L in a circuit is said to have a stuck-at-1 fault if the line permanently has a logic value 1. A circuit is said to have a multiple stuck-at fault if one or more lines have stuck at faults. The total number of distinct multiple stuck-at faults possible in a circuit with N lines is
3N | |
3N - 1 | |
2N - 1 | |
2 |
Question 32 Explanation:
Answer should be 3N-1.
This is because the total possible combinations (i.e., a line may either be at fault (in 2 ways i.e., stuck at 0 or 1) or it may not be, so there are only 3 possibilities for a line) is 3N. In only one combination the circuit will have all lines to be correct (i.e., not a fault). Hence, total combinations in which distinct multiple stuck-at-faults possible in a circuit with N lines is 3N - 1.
This is because the total possible combinations (i.e., a line may either be at fault (in 2 ways i.e., stuck at 0 or 1) or it may not be, so there are only 3 possibilities for a line) is 3N. In only one combination the circuit will have all lines to be correct (i.e., not a fault). Hence, total combinations in which distinct multiple stuck-at-faults possible in a circuit with N lines is 3N - 1.
Question 33 |
The circuit shown below implements a 2-input NOR gate using two 2-4 MUX (control signal 1 selects the upper input). What are the values of signals x, y and z?
1, 0, B | |
1, 0, A | |
0, 1, B | |
0, 1, A |
Question 33 Explanation:
In MUX1, the equation is
g = Ax + Bz'
In MUX2, the equation is
f = xg + yg'
= x(Az+Bz') + y(Az+Bz')'
Function f should be equal to (A+B)'.
Just try to put the values of option (D), i.e., x=0, y=1, z=A,
f = 0(AA+BA') +1(AA+BA')'
= (A+B)'
∴ Option (D) is correct.
g = Ax + Bz'
In MUX2, the equation is
f = xg + yg'
= x(Az+Bz') + y(Az+Bz')'
Function f should be equal to (A+B)'.
Just try to put the values of option (D), i.e., x=0, y=1, z=A,
f = 0(AA+BA') +1(AA+BA')'
= (A+B)'
∴ Option (D) is correct.
Question 34 |
Consider a 3-bit counter, designed using T flip-flops, as shown below:
Assuming the initial state of the counter given by PQR as 000, what are the next three states?
Assuming the initial state of the counter given by PQR as 000, what are the next three states?
011, 101, 000 | |
001, 010, 111 | |
001, 010, 000 | |
011, 101, 111 |
Question 34 Explanation:
The truth table will be
|
RQP |
Rn Qn Pn |
|
000 |
011 |
|
011 |
101 |
|
101 |
000 |
Therefore, the next three states are : 101, 000 and 011
Question 35 |
In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in
Q = 0, Q’ = 1 | |
Q = 1, Q’ = 0 | |
Q = 1, Q’ = 1 | |
Indeterminate states |
Question 35 Explanation:
Question 36 |
Ring counter is analogous to
Toggle Switch | |
Latch | |
Stepping Switch | |
S-R flip flop |
Question 36 Explanation:
→ A ring counter is a type of counter composed of flip-flops connected into a shift register, with the output of the last flip-flop fed to the input of the first, making a "circular" or "ring" structure.
There are two types of ring counters:
1. A straight ring counter, also known as a one-hot counter, connects the output of the last shift register to the first shift register input and circulates a single one (or zero) bit around the ring.
2. A twisted ring counter, also called switch-tail ring counter, walking ring counter, Johnson counter, or Möbius counter, connects the complement of the output of the last shift register to the input of the first register and circulates a stream of ones followed by zeros around the ring.
Note: Ring counter is analogous to Stepping Switch
There are two types of ring counters:
1. A straight ring counter, also known as a one-hot counter, connects the output of the last shift register to the first shift register input and circulates a single one (or zero) bit around the ring.
2. A twisted ring counter, also called switch-tail ring counter, walking ring counter, Johnson counter, or Möbius counter, connects the complement of the output of the last shift register to the input of the first register and circulates a stream of ones followed by zeros around the ring.
Note: Ring counter is analogous to Stepping Switch
Question 37 |
The logic operations of two combinational circuits in Figure-I and Figure-II are
entirely different | |
identical | |
complementary | |
dual |
Question 37 Explanation:
The Two functions are entirely different as:
Figure 1: The logic gates derive the following function:
F1 = ((X + Y')' + X)'
= ((X + Y')')'. X'
= (X + Y'). X'
= XX' + X'Y'
= X'Y'
Figure 2: It is simple AND gate which has 1 input already complimented.
F2 = XY'
So, these two functions are entirely different.
Question 38 |
The output Y of the given circuit
1 | |
0 | |
X | |
X’ |
Question 38 Explanation:
The above function is implemented using XOR function, and gives output as 1 only when both the inputs are different. In this function, both the inputs of the first XOR gate are set to 0. Then the output is also 0 and the further two gates are also getting 0 as both their inputs. So, the final output Y is 0.
Question 39 |
Advantages of synchronous sequential circuits over asynchronous one is
Lower hardware requirement | |
Better noise immunity | |
Faster operation | |
None of the above |
Question 39 Explanation:
Excluded for evaluation.
Question 40 |
The functional difference between SR flip-flop and JK flip-flop is that
JK Flip-flop is faster than SR flip-flop | |
JK flip-flop has a feedback path | |
JK flip-flop accepts both inputs 1 | |
None of them |
Question 40 Explanation:
-> JK flip flop accepts input J=K=1. When J=K=1, the state of the flip-flop gets complimented. But it's not a valid input in SR flip-flop.
-> JK flip flop doesn’t have a feedback path.
-> JK flip flop doesn’t have a feedback path.
Question 41 |
Consider the following sequential circuit
What are the values of Q0 and Q1 after 4 clock cycles if the initial values are ?
What are the values of Q0 and Q1 after 4 clock cycles if the initial values are ?
11 | |
01 | |
10 | |
00 |
Question 41 Explanation:
Question 42 |
What does the following logic diagram represent ?
Synchronous Counter | |
Ripple Counter
| |
Combinational Circuit
| |
Mod 2 Counter |
Question 42 Explanation:
→ A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock.
→ All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are also called ripple-counters because of the way the clock pulse ripples it way through the flip-flops.
→ The MOD of the ripple counter or asynchronous counter is 2n if n flip-flops are used.
→ All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are also called ripple-counters because of the way the clock pulse ripples it way through the flip-flops.
→ The MOD of the ripple counter or asynchronous counter is 2n if n flip-flops are used.
Question 43 |
What will be the final output of D flip-Flop if the input string is 0010011100?
1 | |
0 | |
Don't care | |
none of the above |
Question 43 Explanation:
The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock).
That captured value becomes the Q output. At other times, the output Q does not change.
The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line.
Truth Table for the D-type Flip Flop:
Step-1: D flip flop is nothing data flip flop. It will return what we are given in input.
Step-2: In this question, the LSB and MSB are 1. So final output is 1.
Note: Here, we don’t know what order they are given input.
That captured value becomes the Q output. At other times, the output Q does not change.
The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line.
Truth Table for the D-type Flip Flop:
Step-1: D flip flop is nothing data flip flop. It will return what we are given in input.
Step-2: In this question, the LSB and MSB are 1. So final output is 1.
Note: Here, we don’t know what order they are given input.
Question 44 |
How many flip-flop are needed to divide the input frequency by 64?
4 | |
5 | |
6 | |
8 |
Question 44 Explanation:
Giving an output frequency of 2 n where “n” is the number of flip flops used in the sequence. 64=26 .So the number of flip-flop required are 6.
Question 45 |
If the input J is Connected through K input of J-K, then flip-flop will behave as a
D type flip-flop | |
T type flip-flop | |
S-R flip flop | |
Toggle switch |
Question 45 Explanation:
If J=K=1,then Q n+1 = (Q n ) ’ , so that the J-K Flip-Flop is converted into a T-type Flip-Flop. This unit changes state with each clock pulse and hence it acts as a toggle switch.
Question 46 |
To build a mod-19 counter the number of flip-flop required is
3 | |
5 | |
7 | |
8 |
Question 46 Explanation:
For a mod N counter the number of flip flops required is less than or equal to 2 raised to power n where n is a positive integer.
N<= 2 n
Hence,
For a mod 10 counter, 10< 2 4 . So 4 flip flops are required.
For a mod 16 counter, 16=2 4 . So again 4 flip flops are required.
For a mod 32 counter, 32=2 5 . So 5 flip flops are required.
N<= 2 n
Hence,
For a mod 10 counter, 10< 2 4 . So 4 flip flops are required.
For a mod 16 counter, 16=2 4 . So again 4 flip flops are required.
For a mod 32 counter, 32=2 5 . So 5 flip flops are required.
Question 47 |
If a clock with time period "T" is used with n stage shift register, then output of final stage will be delayed by
nT sec | |
(n-1)T sec | |
n/Tsec | |
(2n-1)T sec |
Question 47 Explanation:
Number of stages = Number of flip-flops in register= no.of bits that can be stored in register.
The data can be shifted one position towards left or right in each clock.
Consider right shift operation.
Initially, data in LSB position is read or accessed.
After each shift the next significant bit moves to LSB position and the bit in LSB is read.
After n-1 shifts i.e after T(n-1) seconds, the last element moves to LSB position.
The data can be shifted one position towards left or right in each clock.
Consider right shift operation.
Initially, data in LSB position is read or accessed.
After each shift the next significant bit moves to LSB position and the bit in LSB is read.
After n-1 shifts i.e after T(n-1) seconds, the last element moves to LSB position.
Question 48 |
A sequential circuit outputs a ONE when an even number (>0) of one's are input; Otherwise the output is ZERO. The minimum number of states required is
0 | |
1 | |
2 | |
3 |
Question 48 Explanation:
Let S_e and S_o are the two states with S_0 is the initial state(with zero ones).
Question 49 |
The output of a sequential circuit depends on
presents inputs only | |
past inputs only | |
both present and past inputs | |
present outputs only |
Question 49 Explanation:
In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on the sequence of past inputs, the input history as well. This is in contrast to combinational logic, whose output is a function of only the present input.
Question 50 |
In a ripple counter using edge triggered JK flip-flops, the pulse input is applied to the
clock input of all flip-flops | |
clock input of one flip flops | |
J and K inputs of all flip flops | |
J and K inputs of one flip-flop |
Question 50 Explanation:
In a ripple counter using edge triggered JK flip-flops, the pulse input is applied to the clock input of one flip flops
Question 51 |
A 32 bit adder is formed by cascading 4 bit CLA adder. The gate delays (latency) for getting the sum bits is
16 | |
18 | |
17 | |
19 |
Question 51 Explanation:
Block diagram of Carry look-ahead adder(CLA) is shown in below figure. All the data inputs A and B are available and Pi and Gi are computed simultaneously for all the CLAs.
The carry propagates the through the Carry-lookahead generators. Carry-lookahead generator which produces carry takes 2 Units of time.
So time delay= (3 units for carry C1 of CLA1)+ (7 * 2 units for carries C2 to C7 of CLA2 to CLA7)+ (3 Units for carry and also sum of CLA8).
Note: For CLAs 1 to 7, it takes an extra 1 unit of time to produce Sum which overlaps with time required for carrie's of next CLAs.
The carry propagates the through the Carry-lookahead generators. Carry-lookahead generator which produces carry takes 2 Units of time.
So time delay= (3 units for carry C1 of CLA1)+ (7 * 2 units for carries C2 to C7 of CLA2 to CLA7)+ (3 Units for carry and also sum of CLA8).
Note: For CLAs 1 to 7, it takes an extra 1 unit of time to produce Sum which overlaps with time required for carrie's of next CLAs.
Question 52 |
What will be the final output of D flip-flop, if the input string is 11010011?
1 | |
0 | |
Don't Care | |
none of Above |
Question 52 Explanation:
Step-1: D flip flop is nothing data flip flop. It will return what we are given in input.
Step-2: In this question, the LSB and MSB are 1. So final output is 1.
Note: Here, we don’t know what order they are given input.
Step-2: In this question, the LSB and MSB are 1. So final output is 1.
Note: Here, we don’t know what order they are given input.
Question 53 |
A modulus -12 ring counter requires a minimum of
10 flip-flops | |
12 flip-flops | |
8 flip-flops | |
6 flip-flops |
Question 53 Explanation:
A ring counter is a type of counter composed of flip-flops connected into a shift register, with the output of the last flip-flop fed to the input of the first, making a "circular" or "ring" structure.
The “MODULO” or “MODULUS” of a counter is the number of states the counter counts or sequences through before repeating itself and a ring counter can be made to output any modulo number. A “mod-n” ring counter will require “n” number of flip-flops connected together to circulate a single data bit providing “n” different output states
So, modulus-12 requires , 12 flip-flops.
The “MODULO” or “MODULUS” of a counter is the number of states the counter counts or sequences through before repeating itself and a ring counter can be made to output any modulo number. A “mod-n” ring counter will require “n” number of flip-flops connected together to circulate a single data bit providing “n” different output states
So, modulus-12 requires , 12 flip-flops.
Question 54 |
In a ripple counter using edge-triggered JK flip-flops, the pulse input is applied to
Clock input of all flip flops | |
J and K input of one flip flop | |
J and K input of all flip flops | |
Clock input of one flip flops |
Question 54 Explanation:
In a ripple counter using edge triggered JK flip-flops, the pulse input is applied to the clock input of one flip flops.
Question 55 |
The number of columns in a state table for a sequential circuit with 'm' flip flops and 'n' input is
m+n | |
m+2n | |
2m+n | |
2m+2n |
Question 55 Explanation:
Its 2m+2n because. If there are m flip-flops, there should be 2m nodes. If there are n inputs, then each node will have 2n.
Question 56 |
A sequential circuit using D flip flop and logic gates is shown in figure, Where X and Y are the inputs and Z is the output. The circuit is
S-R flip flop with inputs X=R and Y=S | |
S-R flip flop with inputs X=S and Y=R | |
J-K flip flop with inputs X=J and Y=K | |
J-K flip flop with X=k and Y=J |
Question 56 Explanation:
Here, PI=Present Input
PS=Present state
NS=Next State
Q n+1 =D=f(PI,PS)=f(x,y,Q n )
D=X’Z+YZ
PS=Present state
NS=Next State
Q n+1 =D=f(PI,PS)=f(x,y,Q n )
D=X’Z+YZ
Question 57 |
A 4 bit ripple counter and a 4 bit synchronous counter are made using flip flops having a propagation delay of 10ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then
R=10 ns, S=40ns | |
R=40ns, S=10ns | |
R=10ns, S=30ns | |
R=30 ns, S=10ns |
Question 57 Explanation:
● A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop.
● Synchronous Counters are so called because the clock input of all the individual flip-flops within the counter are all clocked together at the same time by the same clock signal.
● In the ripple counter, each flip flop will depending upon the precede flip flop and propagation delay is 10ns.So the propagation delay of 4-bit ripple counter is 4*10=40ns.
● In the synchronous counter,one clock input is enough so the propagation delay is 10ns.
● Synchronous Counters are so called because the clock input of all the individual flip-flops within the counter are all clocked together at the same time by the same clock signal.
● In the ripple counter, each flip flop will depending upon the precede flip flop and propagation delay is 10ns.So the propagation delay of 4-bit ripple counter is 4*10=40ns.
● In the synchronous counter,one clock input is enough so the propagation delay is 10ns.
Question 58 |
To load a byte of data parallelly into a shift register with a synchronous load, there must be__
One clock pulse | |
One clock pulse for each 1 in the data | |
Eight clock pulses | |
One clock pulse for each 0 in the data |
Question 58 Explanation:
The sequential device loads the data present on its inputs and then moves or “shifts” it to its output once every clock cycle, hence the name Shift Register.
Question 59 |
Which of the following flipflops does not have a problem of race condition?
T flip flop
| |
JK flip flop | |
Clocked-RS flip flop | |
Clocked D flip flop |
Question 59 Explanation:
In JK flip flop as long as clock is high for the input conditions J&K equals to the output changes or complements its output from 1–>0 and 0–>1. This is called toggling output or uncontrolled changing or racing condition.
Question 60 |
A sequential circuit using D flip flop and logic gates is shown in figure, Where X and Y are the inputs and Z is the output. The circuit is
S-R flip flop with inputs X=R and Y=S | |
S-R flip flop with inputs X=S and Y=R | |
J-K flip flop with inputs X=J and Y=K | |
J-K flip flop with X=k and Y=J |
Question 60 Explanation:
Here, PI=Present Input
PS=Present state
NS=Next State
Q n+1 =D=f(PI,PS)=f(x,y,Q n )
D=X’Z+YZ
PS=Present state
NS=Next State
Q n+1 =D=f(PI,PS)=f(x,y,Q n )
D=X’Z+YZ
Question 61 |
A 4 bit ripple counter and a 4 bit synchronous counter are made using flip flops having a propagation delay of 10ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then
R=10 ns, S=40ns | |
R=40ns, S=10ns | |
R=10ns, S=30ns | |
R=30 ns, S=10ns |
Question 61 Explanation:
→ In synchronous counter time delay is constant while in Ripple it is additive.
→ In Ripple counter (or) Asynchronous counter each flip flop waits for its previous flip flops output.
R= bit size*propagation delay
= 4*10ns
= 40ns
→ In Synchronous counter all flip flops are triggered by same clock. It will gives output of all four flip flops at the same time.
S=10ns
→ In Ripple counter (or) Asynchronous counter each flip flop waits for its previous flip flops output.
R= bit size*propagation delay
= 4*10ns
= 40ns
→ In Synchronous counter all flip flops are triggered by same clock. It will gives output of all four flip flops at the same time.
S=10ns
Question 62 |
In a ripple counter using edge-triggered JK flip-flops, the pulse input is applied to
Clock input of all flip flops | |
j and K input of one flip flop | |
J and K input of all flip flops | |
Clock input of one flip flops |
Question 62 Explanation:
A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock.
→ All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are also called ripple-counters because of the way the clock pulse ripples it way through the flip-flops.
So, answer is clock input of one flip-flop.
→ All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are also called ripple-counters because of the way the clock pulse ripples it way through the flip-flops.
So, answer is clock input of one flip-flop.
Question 63 |
In a positive edge triggered JK flip flop, a low J and a low K produces
no change | |
low state | |
high state | |
toggle state |
Question 63 Explanation:
→ In JK Flip Flop if J=K=0 then it holds its current state. There will be no change.
Question 64 |
In RS flip-flop, which of the following values of R and S causes race condition?
R=0,S=0 | |
R=0,S=1 | |
R=1,S=0 | |
R=1,S=1 |
Question 64 Explanation:
→A race condition is a timing-related phenomenon. A standard S-R FF (two cross-coupled NAND or NOR gates) is stable for any stable input.
→Race around condition in digital circuits occur when the final state of the output depends on how the inputs arrive.
→The 'function' is in the S=1 R=1 input, the memory situation. The state of the FF depends on which state came before the 11, if it was 01 the FF is in Q=1 state, if it was 10 the FF is in the Q=0 state. This is the classical memory effect of a FF.
→Race around condition in digital circuits occur when the final state of the output depends on how the inputs arrive.
→The 'function' is in the S=1 R=1 input, the memory situation. The state of the FF depends on which state came before the 11, if it was 01 the FF is in Q=1 state, if it was 10 the FF is in the Q=0 state. This is the classical memory effect of a FF.
Question 65 |
A binary 3 bit down counter uses J-K flip-flops, FF i with inputs J i , K i and outputs Q i , i=0,1,2 respectively. The minimized expression for the input from following, is
I. J 0 = K 0 = 0
II. J 0 = K 0 = 1
III. J 1 = K 1 = Q 0
IV. J 1 = K 1 =Q’0
V. J 2 = K 2 = Q 1 Q 0
VI. J 2 = K 2 = Q’ 1 Q’ 0
I. J 0 = K 0 = 0
II. J 0 = K 0 = 1
III. J 1 = K 1 = Q 0
IV. J 1 = K 1 =Q’0
V. J 2 = K 2 = Q 1 Q 0
VI. J 2 = K 2 = Q’ 1 Q’ 0
I,III,V | |
I,IV,VI | |
II,III,V | |
II,IV,VI |
Question 65 Explanation:
In a JK flip-flop, Qn=Q(bar) iff J=K=1.
State sequence of down counter is as follows:
State sequence of down counter is as follows:
Question 66 |
Essential hazards may occur in :
Combinational logic circuits | |
Synchronous sequential logic circuits | |
Asynchronous sequential logic circuits working in the fundamental mode | |
Asynchronous sequential logic circuits working in the pulse mode |
Question 66 Explanation:
→ Essential hazards may occur in asynchronous sequential logic circuits working in the fundamental mode.
→ Asynchronous circuits is called essential hazard is caused by unequal delays along two or more paths that originate from the same same input.
→ It cannot be corrected by adding redundant gates and it can only be corrected by adjusting the amount of delay in the affected path.
→ Asynchronous circuits is called essential hazard is caused by unequal delays along two or more paths that originate from the same same input.
→ It cannot be corrected by adding redundant gates and it can only be corrected by adjusting the amount of delay in the affected path.
Question 67 |
The characteristic equation of a T flip-flop is:__[Note: The symbols used have the usual meaning]
Q n+1 = T ⊕ Q n | |
Q n+1 =T+Q n | |
Q n+1 =TQ n | |
Q n+1 = T Q n |
Question 67 Explanation:
T-Flip flop Truth Table:
T-Flip-Flop Characteristic Table:
T-Flip-Flop Characteristic equation:
Q next = TQ' + T'Q
T-Flip-Flop Characteristic Table:
T-Flip-Flop Characteristic equation:
Q next = TQ' + T'Q
Question 68 |
When an inventor is placed between both inputs of an S-R flip flop, the resulting flip flop is :
JK flip-flop | |
D-flip-flop | |
T flip-flop | |
None of these |
Question 68 Explanation:
Given question is ambiguous. It is not mentioned how the inverter is connected. Placing NOT gate in different positions gives different solutions.
Question 69 |
The characteristic equation of the D flip-flop is :
Not option given | |
Q=D | |
Q=1 | |
Q=0 | |
Q t+1 =D |
Question 69 Explanation:
D flip flop characteristic equation truth table:
Q t+1 = DQ' + DQ
Q t+1 =D
Q t+1 = DQ' + DQ
Q t+1 =D
Question 70 |
Which of the following input combination is not desirable for SR flip flop ?
S = 0, R = 0 | |
S = 0, R = 1 | |
S = 1, R = 0 | |
S = 1, R = 1 |
Question 71 |
The number of flip-flops required in a decade counter is
2 | |
3 | |
4 | |
10 |
Question 72 |
A latch is constructed using two cross-coupled
AND and OR gates | |
AND gates | |
NAND and NOR gates | |
NAND gates |
Question 72 Explanation:
Latches can be constructed either with NAND gates or NOR gates.
Ex: SR latch can be constructed by using 2 cross coupled NAND gates( or NOR gates)
Question 73 |
Advantage of synchronous sequential circuits over asynchronous ones is
faster operation | |
ease of avoiding problems due to hazard | |
lower hardware requirement | |
better noise immunity | |
None of the above |
Question 73 Explanation:
Note: Excluded for evaluation.
Question 74 |
The characteristic equation of a JK flip flop is :
Qn+1 = J.Qn +K.Qn | |
Qn+1 = J.Q'n +K'Qn | |
Qn+1= QnJ.K | |
Qn+1= (J+K)Qn |
Question 74 Explanation:
The characteristic equation of a JK flip flop is Qn+1 = J.Q'n +K'Qn
Characteristic Table:
Question 75 |
A reduced state table has 18 rows. The minimum number of Flips flops needed to implement the sequential machine is :
18 | |
9 | |
5 | |
4 |
Question 75 Explanation:
Mod value of a counter is the number of unique states.
Let K = Number of states =18.
Number of flip-flops is the smallest number which is greater than or equal to L log2K
log218 = 4.1.
L=5>=4.1.
So number of flip-flops needed is 5.
Let K = Number of states =18.
Number of flip-flops is the smallest number which is greater than or equal to L log2K
log218 = 4.1.
L=5>=4.1.
So number of flip-flops needed is 5.
Question 76 |
The characteristic equation of D flip-flop is :
Q=1 | |
Q=0 | |
Q= D’ | |
Q=D |
Question 76 Explanation:
D flip flop characteristic equation truth table:
Question 77 |
The characteristic equation of a T flip flop is given by :
QN+1 = TQN | |
QN+1 = T+QN | |
QN+1 = T ⊕ QN | |
QN+1=T'QN |
Question 77 Explanation:
T-Flip flop Truth Table:
Question 78 |
In order to build a MOD-18 counter, the minimum number of flip flops needed is equal to :
18 | |
9 | |
5 | |
4 |
Question 78 Explanation:
Mod value of a counter is the number of unique states.
Let K = Number of states =18.
Number of flip-flops is the smallest number which is greater than or equal to Log K ( base 2).
Log 18 = 4.1.
L=5>=4.1.
So number of flip-flops needed is 5.
Let K = Number of states =18.
Number of flip-flops is the smallest number which is greater than or equal to Log K ( base 2).
Log 18 = 4.1.
L=5>=4.1.
So number of flip-flops needed is 5.
Question 79 |
What is the maximum counting speed of a 4-bit binary counter which is composed of Flip-Flop with a propagation delay of 25ns ?
1MHz | |
10MHz | |
100MHz | |
4MHz |
Question 79 Explanation:
Question is about frequency of the counter.
Frequency = 1/ Time
Binary counter is ripple counter where the output one flip flop is clock input to next flip flop.
So, maximum delay(time)= 4*25ns = 100 ns.
frequency= 1/100 ns
= 10 MHz.
Frequency = 1/ Time
Binary counter is ripple counter where the output one flip flop is clock input to next flip flop.
So, maximum delay(time)= 4*25ns = 100 ns.
frequency= 1/100 ns
= 10 MHz.
Question 80 |
Which of the following is a sequential circuit?
Multiplexer | |
Decoder | |
Counter | |
Full adder |
Question 80 Explanation:
Combinational circuits have no memory. Combinational circuits are defined as the time independent circuits which do not depend upon previous inputs to generate any output are termed as combinational circuits.
Examples: Encoder, Decoder, Multiplexer, Demultiplexer
Sequential circuits have memory. Sequential circuits are those which are dependent on clock cycles and depends on present as well as past inputs to generate any output.
Example: Flip-flops, Counters
Examples: Encoder, Decoder, Multiplexer, Demultiplexer
Sequential circuits have memory. Sequential circuits are those which are dependent on clock cycles and depends on present as well as past inputs to generate any output.
Example: Flip-flops, Counters
Question 81 |
A ripple counter is a (n):
Synchronous Counter | |
Asynchronous counter | |
Parallel counter | |
None of the above |
Question 82 |
What will be the number of states when a MOD-2 counter is followed by a MOD-5 counter?
5 | |
10 | |
15 | |
20 |
Question 82 Explanation:
Here, we are multiplying the mod values.
Given mod values are 2 and 5
= 2*5
= 10
Given mod values are 2 and 5
= 2*5
= 10
Question 83 |
The number of flip-flops required to design a modulo - 272 counter is:
8 | |
9 | |
27 | |
11 |
Question 83 Explanation:
If we have “n” flip-flops then total number of combinations possible is 2 n .
So total number of states possible is 2 n i.e. MOD 2 n .
Here 2 n = 272
So n = log 2 272
n = 9
So total number of states possible is 2 n i.e. MOD 2 n .
Here 2 n = 272
So n = log 2 272
n = 9
Question 84 |
Which of the following statements is FALSE?
Johnson counter is a synchronous counter | |
Ripple counter is an asynchronous counter. | |
Asynchronous counters are slower than synchronous counters. | |
A counter may count up or count down, but cannot count both up and down. |
Question 84 Explanation:
→A counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock.
→Counters are of two types depending upon clock pulse applied. These counters are: Asynchronous counter and Synchronous counter.
→In Asynchronous Counter { also known as Ripple counter} different flip flops are triggered with different clock, not simultaneously!
→While in Synchronous Counter, all flip flops are triggered with same clock simultaneously ; Synchronous Counter is faster than Asynchronous counter in operation.
→Synchronous Counter :- →Synchronous Counter does not produce any decoding errors.
→Synchronous Counter is also called Serial Counter.
→Synchronous Counter will operate in any desired count sequence.
→In Synchronous Counter designing as well implementation are complex due to increasing the number of states.
→Synchronous Counter examples are: Ring counter , Johnson Counter, etc.
→Asynchronous Counters :-
→Asynchronous Counter produces decoding error.
→Asynchronous Counter is also called Parallel Counter.
→Asynchronous Counter will operate only in fixed count sequence (UP/DOWN).
→In Asynchronous Counter designing as well as implementation is very easy.
→Asynchronous Counter examples are: Ripple UP counter, Ripple DOWN counter, etc.
→Counters are of two types depending upon clock pulse applied. These counters are: Asynchronous counter and Synchronous counter.
→In Asynchronous Counter { also known as Ripple counter} different flip flops are triggered with different clock, not simultaneously!
→While in Synchronous Counter, all flip flops are triggered with same clock simultaneously ; Synchronous Counter is faster than Asynchronous counter in operation.
→Synchronous Counter :- →Synchronous Counter does not produce any decoding errors.
→Synchronous Counter is also called Serial Counter.
→Synchronous Counter will operate in any desired count sequence.
→In Synchronous Counter designing as well implementation are complex due to increasing the number of states.
→Synchronous Counter examples are: Ring counter , Johnson Counter, etc.
→Asynchronous Counters :-
→Asynchronous Counter produces decoding error.
→Asynchronous Counter is also called Parallel Counter.
→Asynchronous Counter will operate only in fixed count sequence (UP/DOWN).
→In Asynchronous Counter designing as well as implementation is very easy.
→Asynchronous Counter examples are: Ripple UP counter, Ripple DOWN counter, etc.
Question 85 |
A flip-flop has a 20-nano second delay from the time its CP input goes from 1 to 0 to the time uses these flip-flops?
20 ns | |
320 ns | |
36 ns | |
16 ns |
Question 85 Explanation:
Delay for one flip-flop = 20ns
Since in question they are asking about the number of flip-flops(i.e.n>1).
So the delay for n- flip flops will be a multiple of 20 and “n” will be greater than 1.
If you will see the given options then option (B) is correct because 320 is a multiple of 20(i.e. 20* 16 = 320) and n =16(i.e. n>1)
Question 86 |
The counter implemented by the following circuit diagram where inputs to the NAND gate are the outputs of the B and C flip-flops, is:
MOD-7 Counter | |
MOD-6 Counter | |
MOD-8 Counter | |
MOD-4 Counter |
Question 86 Explanation:
→ In question, CLR is given as Input.
→ CLR is asynchronous input pin.
→ If CLR=1, all flip-flop outputs are reset to ‘0’.
→ When counter will start counting, it will count from 0 to 5 and at 6th clock, flip-flop output are cleared.
→ Hence given counter is MOD6 counter.
→ CLR is asynchronous input pin.
→ If CLR=1, all flip-flop outputs are reset to ‘0’.
→ When counter will start counting, it will count from 0 to 5 and at 6th clock, flip-flop output are cleared.
→ Hence given counter is MOD6 counter.
Question 87 |
A new flip flop with inputs X and Y, has the following property
Which of the following expresses the next state in terms of X, Y, current state?
Which of the following expresses the next state in terms of X, Y, current state?
(X’ ∧ Q’) ∨ (Y’ ∧ Q) | |
(X’ ∧ Q) v (Y’ ∧ Q’) | |
(X ∧ Q’) v (Y ∧ Q) | |
(X ∧ Q’) v (Y’ ∧ Q) |
Question 87 Explanation:
Question 88 |
Which of the following flip-flops is free from race around problem?
D flip-flop | |
T flip-flop
| |
S-R flip-flop
| |
Master-slave J-K flip-flop |
Question 88 Explanation:
Master slave JK flip-flops is free from race around condition.
During high clock when ever applied input changes the output also changes. But in JK flip flop when j=k=1 , without any change in the input the output changes , this condition is called a race around condition. The circuit accepts input data when the clock signal is “HIGH”, and passes the data to the output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip flop is a “Synchronous” device as it only passes data with the timing of the clock signal.
During high clock when ever applied input changes the output also changes. But in JK flip flop when j=k=1 , without any change in the input the output changes , this condition is called a race around condition. The circuit accepts input data when the clock signal is “HIGH”, and passes the data to the output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip flop is a “Synchronous” device as it only passes data with the timing of the clock signal.
Question 89 |
How many flip-flops are required mod – 16 counters?
5 | |
6 | |
3 | |
4 |
Question 89 Explanation:
No. of flip flops required for the mod N counter is log2 N.
So log2 16=4.
So log2 16=4.
Question 90 |
In D flip flop the out-put state Q is related with D input in what way?
Q is dependent of D
| |
Q is same as D | |
Q is independent of D
| |
Q is complement of D
|
Question 91 |
A negative edge triggered flip flop transfers data from input on the:
LOW to HIGH transition of clock pulse
| |
BEFORE transition of clock pulse
| |
HIGH to LOW transition of clock pulse
| |
WITHOUT transition of clock pulse
|
Question 91 Explanation:
A negative edge triggered flip flop transfers data from input on the high to transition of clock pulse.
Question 92 |
The clock signals are used in sequential logic circuits to
Tell the time of the day | |
Tell how much time has elapsed since the system was turned on
| |
Carry serial data signals | |
Synchronize events in various parts of system |
Question 92 Explanation:
The clock signals are used in sequential logic circuit for synchronization.
Question 93 |
For which of the following flip-flops, the output is clearly defined for all combinations of two inputs?
Q-type flip-flop | |
R-S flip-flop | |
J-K flip-flop | |
T flip-flop |
Question 93 Explanation:
or R-S flip flop the output is not defined for input R=1,S=1. But for J-K flip flop output is defined for all combinations of two inputs.
Note that T flip-flop is 1 input flip flop and not two input flip flop.
Note that T flip-flop is 1 input flip flop and not two input flip flop.
Question 94 |
The output of a sequential circuit depends on
present input only | |
past input only | |
both present and past input | |
past output only
| |
None of the above |
Question 94 Explanation:
Question 95 |
Which of the following flip-flops is free from race condition ?
T flip-flop | |
SR flip-flop | |
Master-slave JK flip-flop | |
None of the above |
Question 95 Explanation:
Master-slave JK flip-flop is free from race condition.
There are 95 questions to complete.
