Consider the synchronous sequential circuit in the below figure.

(a) Draw a state diagram, which is implemented by the circuit. Use the following names for the states corresponding to the values of flip-flops as given below.

(b) Given that the initial state of the circuit is S₄, identify the set of states, which are not reachable.

Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop.

Initially, both Q₀ and Q₁ are set to 1 (before the 1^st clock cycle). The outputs

Design a synchronous counter to go through the following states:

  1, 4, 2, 3, 1, 4, 2, 3, 1, 4,........... 

The following arrangement of master-slave flip flops

has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),

Consider the following circuit with initial state Q₀ = Q₁ = 0. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.

Consider the following timing diagrams of X and C; the clock period of C <= 40 nanosecond. Which one is the correct plot of Y?

Consider the circuit given below with initial state Q₀ = 1, Q₁ = Q₂ = 0. The state of the circuit is given by the value 4Q₂ + 2Q₁ + Q₀

Which one of the following is the correct state sequence of the circuit?

A sequential circuit takes an input stream of 0’s and 1’s and produces an output stream of 0’s and 1’s. Initially it replicates the input on its output until two consecutive 0’s are encountered on the input. From then onward, it produces an output stream, which is the bit-wise complement of input stream until it encounters two consecutive 1’s, whereupon the process repeats. An example of input and output stream is shown below.

The input stream: 101100 01001011 0 11
The desired output: 101100 10110100 0 11 

J-K master-slave flip-flops are to be used to design the circuit.
(a) Give the state transition diagram.
(b) Give the minimized sum-of-product expression for J and K inputs of one of its state flip-flops.

A 1-input, 2-output synchronous sequential circuit behaves as follows:

Let z_k, n_k denote the number of 0's and 1's respectively in initial k bits of the input (z_k + n_k = k). The circuit outputs 00 until one of the following conditions holds.

•   zk - nk = 2. In this case, the output at the k-th and all subsequent clock ticks is 10.
•   nk - zk = 2. In this case, the output at the k-th and all subsequent clock ticks is 01. 

What is the minimum number of states required in the state transition graph of the above circuit?

In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in

Consider the partial implementation of a 2-bit counter using T flip-flops following the sequence 0-2-3-1-0, as shown below

To complete the circuit, the input X should be

Start and stop bits do not contain an ‘information’ but are used in serial communication for

How many pulses are needed to change the contents of a 8-bit up counter from 10101100 to 00100111 (rightmost bit is the LSB)?

Which of the following input sequences will always generate a 1 at the output Z at the end of the third cycle?

A line L in a circuit is said to have a stuck-at-0 fault if the line permanently has a logic value 0. Similarly a line L in a circuit is said to have a stuck-at-1 fault if the line permanently has a logic value 1. A circuit is said to have a multiple stuck-at fault if one or more lines have stuck at faults. The total number of distinct multiple stuck-at faults possible in a circuit with N lines is

The circuit shown below implements a 2-input NOR gate using two 2-4 MUX (control signal 1 selects the upper input). What are the values of signals x, y and z?

Which of the following input sequences for a cross-coupled R-S flip-flop realized with two NAND gates may lead to an oscillation?

Consider the following state diagram and its realization by a JK flip flop The combinational circuit generates J and K in terms of x, y and Q. The Boolean expressions for J and K are:

The above circuit produces the output sequence:

Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: Advantage of synchronous sequential circuits over asynchronous ones is:

Consider the following circuit.

The flip-flops are positive edge triggered D FFs. Each state is designated as a two bit string Q₀Q₁. Let the initial state be 00. The state transition sequence is:

You are given a free running clock with a duty cycle of 50% and a digital waveform f  which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of f  by 180°?

Consider the circuit in the diagram. The ⊕ operator represents Ex-OR. The D flipflops are initialized to zeroes (cleared).

The following data: 100110000 is supplied to the “data” terminal in nine clock cycles. After that the values of q2q1q0 are:

The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0,……) is ___________.

Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops.

The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is ______