Sequential-Circuits

Question 1
Consider a 3-bit counter, designed using T flip-flops, as shown below: Assuming the initial state of the counter given by PQR as 000, what are the next three states?
A
011, 101, 000
B
001, 010, 111
C
001, 010, 000
D
011, 101, 111
Question 1 Explanation: 

The truth table will be

RQP

Rn Qn Pn

000

011

011

101

101

000

 

Therefore, the next three states are : 101, 000 and 011

Question 2

Consider the synchronous sequential circuit in the below figure.

(a) Draw a state diagram, which is implemented by the circuit. Use the following names for the states corresponding to the values of flip-flops as given below.

(b) Given that the initial state of the circuit is S4, identify the set of states, which are not reachable.

A
Theory Explanation.
Question 3

Design a synchronous counter to go through the following states:

  1, 4, 2, 3, 1, 4, 2, 3, 1, 4,........... 

A
Theory Explanation.
Question 4

The following arrangement of master-slave flip flops

has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),

A
1, 0
B
1, 1
C
0, 0
D
0, 1
Question 4 Explanation: 
Here clocks are applied to both flip flops simultaneously.
When 11 is applied to Jk flip flop it toggles the value of P so op at P will be 1.
Input to D flip flop will be 0(initial value of P) so op at Q will be 0.
Question 5

Consider the following circuit with initial state Q0 = Q1 = 0. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.

Consider the following timing diagrams of X and C; the clock period of C <= 40 nanosecond. Which one is the correct plot of Y?

A
B
C
D
Question 5 Explanation: 

Given clock is +edge triggered.
See the first positive edge. X is 0, and hence the output is 0, because
Y = Q1N = D1×Q0' = 0⋅Q0' = 0
At second +edge, X is 1 and Q0' is also 1. So output is 1 (when second +ve edge of the clock arrives, Q0' would surely be 1 because the setup time of flip flop is given as 20ns and clock period is ≥ 40ns).
At third +ve edge, X is 1 and Q0' is 0, so output is 0.
Now output never changes back to 1 as Q0' is always 0 and when Q0' finally becomes 1, X is 0.
Hence option (A) is the correct answer.
Question 6

Consider the circuit given below with initial state Q0 = 1, Q1 = Q2 = 0. The state of the circuit is given by the value 4Q2 + 2Q1 + Q0

Which one of the following is the correct state sequence of the circuit?

A
1,3,4,6,7,5,2
B
1,2,5,3,7,6,4
C
1,2,7,3,5,6,4
D
1,6,5,7,2,3,4
Question 6 Explanation: 
Question 7

A sequential circuit takes an input stream of 0’s and 1’s and produces an output stream of 0’s and 1’s. Initially it replicates the input on its output until two consecutive 0’s are encountered on the input. From then onward, it produces an output stream, which is the bit-wise complement of input stream until it encounters two consecutive 1’s, whereupon the process repeats. An example of input and output stream is shown below.

The input stream: 101100 01001011 0 11
The desired output: 101100 10110100 0 11 

J-K master-slave flip-flops are to be used to design the circuit.
(a) Give the state transition diagram.
(b) Give the minimized sum-of-product expression for J and K inputs of one of its state flip-flops.

A
Theory Explanation is given below.
Question 7 Explanation: 

Question 8

A 1-input, 2-output synchronous sequential circuit behaves as follows:

Let zk, nk denote the number of 0's and 1's respectively in initial k bits of the input (zk + nk = k). The circuit outputs 00 until one of the following conditions holds.

•   zk - nk = 2. In this case, the output at the k-th and all subsequent clock ticks is 10.
•   nk - zk = 2. In this case, the output at the k-th and all subsequent clock ticks is 01. 

What is the minimum number of states required in the state transition graph of the above circuit?

A
5
B
6
C
7
D
8
Question 8 Explanation: 
Let q is the initial state.

q0 ← Number of zeros is one more than number of ones.
q1 ← Number of ones is one more than number of zeros.
q00 ← Number of zeros is two more than number of ones.
q11 ← Number of ones is two more than number of zeros.
Question 9

In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in

A
Q = 0, Q' = 1
B
Q = 1, Q' = 0
C
Q = 1, Q' = 1
D
Indeterminate states
Question 9 Explanation: 

Truth table for the SR latch by cross coupling two NAND gates is

So, Answer is Option (D).
Question 10

Consider the partial implementation of a 2-bit counter using T flip-flops following the sequence 0-2-3-1-0, as shown below

To complete the circuit, the input X should be

A
Q2c
B
Q2 + Q1
C
(Q1 + Q2)c
D
Q1 ⊕ Q2
Question 10 Explanation: 
Sequence given is
0 - 2 - 3 - 1 - 0
or
00 - 10 - 11 - 01 - 00
From the given sequence, we have state table as,

Now we have present state and next state, so we should use excitation table of T flip-flop,

From state table,
T2 = Q2⊙Q1 and T1 = Q2⊕Q1
X = T1 = Q2⊕Q1
Question 11

How many pulses are needed to change the contents of a 8-bit up counter from 10101100 to 00100111 (rightmost bit is the LSB)?

A
134
B
133
C
124
D
123
Question 11 Explanation: 
The 8 bit counter will be 0-255 to move from 10101100 (172) to 1000111 (39).
→ First counter is move from 172 to 255 = 83 pulses
→ 255 to 0 = 1 pulse
→ 0 to 39 = 39 pulses
Total = 83 + 1 + 39 = 123 pulses
Question 12

Which of the following input sequences will always generate a 1 at the output Z at the end of the third cycle?

A
000
101
111
B
101
110
111
C
011
101
111
D
001
110
111
E
None of these
Question 12 Explanation: 

While filling done in reverse order, all operations are not satisfied.
Question 13

A line L in a circuit is said to have a stuck-at-0 fault if the line permanently has a logic value 0. Similarly a line L in a circuit is said to have a stuck-at-1 fault if the line permanently has a logic value 1. A circuit is said to have a multiple stuck-at fault if one or more lines have stuck at faults. The total number of distinct multiple stuck-at faults possible in a circuit with N lines is

A
3N
B
3N - 1
C
2N - 1
D
2
Question 13 Explanation: 
Answer should be 3N-1.
This is because the total possible combinations (i.e., a line may either be at fault (in 2 ways i.e., stuck at 0 or 1) or it may not be, so there are only 3 possibilities for a line) is 3N. In only one combination the circuit will have all lines to be correct (i.e., not a fault). Hence, total combinations in which distinct multiple stuck-at-faults possible in a circuit with N lines is 3N - 1.
Question 14

The circuit shown below implements a 2-input NOR gate using two 2-4 MUX (control signal 1 selects the upper input). What are the values of signals x, y and z?

A
1, 0, B
B
1, 0, A
C
0, 1, B
D
0, 1, A
Question 14 Explanation: 
In MUX1, the equation is
g = Ax + Bz'
In MUX2, the equation is
f = xg + yg'
= x(Az+Bz') + y(Az+Bz')'
Function f should be equal to (A+B)'.
Just try to put the values of option (D), i.e., x=0, y=1, z=A,
f = 0(AA+BA') +1(AA+BA')'
= (A+B)'
∴ Option (D) is correct.
Question 15

Which of the following input sequences for a cross-coupled R-S flip-flop realized with two NAND gates may lead to an oscillation?

A
11, 00
B
01, 10
C
10, 01
D
00, 11
Question 15 Explanation: 
RS slip-flop using NAND gates.
So, 00 input cause indeterminate state which may lead to oscillation.
Question 16

Consider the following state diagram and its realization by a JK flip flop The combinational circuit generates J and K in terms of x, y and Q. The Boolean expressions for J and K are:

A
(x⊕y)’ and x’⊕y’
B
(x⊕y)’ and x⊕y
C
x⊕y and (x⊕y)’
D
x⊕y and x⊕y
Question 16 Explanation: 
From the given statement:

Excitation table of JK:
Question 17

The above circuit produces the output sequence:

A
1111 1111 0000 0000
B
1111 0000 1111 000
C
1111 0001 0011 010
D
1010 1010 1010 1010
Question 17 Explanation: 
Let us suppose initially output of all JK flip flop is 1.
So we can draw below table to get the output Q3.

From the above table Q3 that is output is 1111 0001 0011 010.
So, answer is (C).
Question 18

Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: Advantage of synchronous sequential circuits over asynchronous ones is:

A
faster operation
B
ease of avoiding problems due to hazards
C
lower hardware requirement
D
better noise immunity
E
none of the above
Question 18 Explanation: 
In synchronization, there is a less chance of hazards but it can increase the delay. Then the advantage is ease of avoiding problems due to hazards.
Question 19

Start and stop bits do not contain an ‘information’ but are used in serial communication for

A
Error detection
B
Error correction
C
Synchronization
D
Slowing down the communications
Question 19 Explanation: 
The start and stop bits are used to synchronize the serial receivers.
Question 20

Consider the following circuit.

The flip-flops are positive edge triggered D FFs. Each state is designated as a two bit string Q0Q1. Let the initial state be 00. The state transition sequence is:

A
B
C
D
Question 20 Explanation: 
Question 21

You are given a free running clock with a duty cycle of 50% and a digital waveform f  which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of f  by 180°?

A
B
C
D
Question 21 Explanation: 
Duty cycle is the period of time where the signal high, i.e. 1.
50% of duty cycle means, the wave is 1 for half of the time and 0 for the other half of the time. It is a usual digital signal with 1 and 0.
The waveform f changes for every negative edge, that means f value alters from 1 to 0 or 0 to 1 for every negative edge of the clock.
Now the problem is that we need to find the circuit which produces a phase shift of 180, which means the output is 0 when f is 1 and output is 1 when f is 0.
Like the below image.

Now to find the answer we can choose elimination method.
F changes for negative edge, so that output too should change at negative edge. i.e if f becomes 0, then at the same time output should become 1, vice versa.
So, whenever input changes, at the same point of time output too should change. As input changes on negative edge, the output should be changed at negative edge only.
To have the above behaviour, the second D flip-flop which produces the final output should be negative edge triggered. because whatever the 2nd flip-flop produces, that is the output of the complete circuit.
So, we can eliminate option a, d.
Now either b or c can be answer.
How the flip-flop chain works in option b and c is as below.
—> F changes at negative edge.
—> But flip-flop1 responds at next positive edge.
—> After this flip-flop2 responds at next negative edge.
That means flip-flop2 produces the same input which is given to flip-flop now after a positive edge and a negative edge, that means a delay of one clock cycle, which is 180 degrees phase shift for the waveform of f.
Option b) we are giving f’, so that the output is f’ with 180 degrees phase shift.
Option c) we are giving f, so that the output is f with 180 degrees phase shift.
Hence option C is the answer.
Question 22

Consider the circuit in the diagram. The ⊕ operator represents Ex-OR. The D flipflops are initialized to zeroes (cleared).

The following data: 100110000 is supplied to the “data” terminal in nine clock cycles. After that the values of q2q1q0 are:

A
000
B
001
C
010
D
101
Question 22 Explanation: 
q0N = Data, q1N = q0q22N = q1
Question 23

The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0,……) is ___________.

A
2
B
3
C
4
D
5
Question 23 Explanation: 
Count sequence mentioned is
00
00
01
01
10
10
11
11
In the above sequence two flip-flop's will not be sufficient. Since we are confronted with repeated sequence, we may add another bit to the above sequence.
000
100
001
101
010
110
011
111
Now and every count is unique, occurring only once.
So finally 3-flip flops is required.
Question 24

Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is

A
0, 1, 3, 7, 15, 14, 12, 8, 0
B
0, 1, 3, 5, 7, 9, 11, 13, 15, 0
C
0, 2, 4, 6, 8, 10, 12, 14, 0
D
0, 8, 12, 14, 15, 7, 3, 1, 0
Question 24 Explanation: 
In a Johnson’s counter LSB is complemented and a circular right shift operation has to be done to get the next state.

The state sequence is 0,8,12,14,15,7,3,1,0.
There are 24 questions to complete.

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