Statement-I is true as daisy chaining is used to assign priorities in attending interrupts.
Statement-II is false as vectored interrupt doesn’t involve polling but non-vectored interrupt involves polling.
Statement-III is true as polling means that CPU periodically checks the status bits to know if any device needs attention.
Statement-IV is false as during DMA only one of the CPU or DMA can be bus master at a time.

Memory parity errors can be caused by failing hardware or outside elements disrupting how computer memory functions.
Fixing parity errors involves removing the outside cause or failing hardware.
A memory parity error means that one or more stored data values carries a different value when it's recalled than when it was stored.
According to Cisco, parity errors are a type of data corruption.
Parity errors offset the charge value and can bring back invalid or incorrect commands for the computer.

Register indirect: It is specified implicitly in the definition of instruction. Register indirect addressing mode, the operands are stored in the memory. The address of the corresponding memory location is given in a register which is specified in the instruction.
Index mode: The address of the operand is obtained by adding to the contents of the general register (called index register) a constant value. The number of the index register and the constant value are included in the instruction code.