Interruption
Question 1 |
Consider the following statements.
- I. Daisy chaining is used to assign priorities in attending interrupts.
II. When a device raises a vectored interrupt, the CPU does polling to identify the source of the interrupt.
III. In polling, the CPU periodically checks the status bits to know if any device needs its attention.
IV. During DMA, both the CPU and DMA controller can be bus masters at the same time.
Which of the above statements is/are TRUE?
I and IV only | |
I and II only
| |
III only | |
I and III only
|
Question 1 Explanation:
Statement-I is true as daisy chaining is used to assign priorities in attending interrupts.
Statement-II is false as vectored interrupt doesn’t involve polling but non-vectored interrupt involves polling.
Statement-III is true as polling means that CPU periodically checks the status bits to know if any device needs attention.
Statement-IV is false as during DMA only one of the CPU or DMA can be bus master at a time.
Statement-II is false as vectored interrupt doesn’t involve polling but non-vectored interrupt involves polling.
Statement-III is true as polling means that CPU periodically checks the status bits to know if any device needs attention.
Statement-IV is false as during DMA only one of the CPU or DMA can be bus master at a time.
Question 2 |
Interrupt generated due to which of the following operations does not belong to program-related interrupt category?
Division by zero | |
Attempt to execute an illegal machine instruction | |
Memory parity error | |
Reference outside a user’s allowed memory space |
Question 2 Explanation:
Memory parity errors can be caused by failing hardware or outside elements disrupting how computer memory functions.
Fixing parity errors involves removing the outside cause or failing hardware.
A memory parity error means that one or more stored data values carries a different value when it's recalled than when it was stored.
According to Cisco, parity errors are a type of data corruption.
Parity errors offset the charge value and can bring back invalid or incorrect commands for the computer.
Fixing parity errors involves removing the outside cause or failing hardware.
A memory parity error means that one or more stored data values carries a different value when it's recalled than when it was stored.
According to Cisco, parity errors are a type of data corruption.
Parity errors offset the charge value and can bring back invalid or incorrect commands for the computer.
Question 3 |
Which of the following is true with respect to interrupts?
Unless enabled, a CPU will not be able to process interrupts | |
Loop instructions can not be interrupted till they complete | |
A processor checks for interrupts before executing a new instruction | |
Only level-triggered interrupts are possible on microprocessor |
Question 3 Explanation:
True, unless the interrupt is enabled,even if there will be an interrupt ,the CPU will not be able to process interrupts.
False ,because loop may contain more than one instruction.And the rule is that single instruction cannot be interrupted till they complete.
False, because a processor checks for the interrupts before fetching new instructions.
False.even edge triggered interrupts are possible.
False ,because loop may contain more than one instruction.And the rule is that single instruction cannot be interrupted till they complete.
False, because a processor checks for the interrupts before fetching new instructions.
False.even edge triggered interrupts are possible.
There are 3 questions to complete.