Memory-Hierarchy
Question 1 |
A computer system has a three level memory hierarchy, with access time and hit ratios as shown below:
(a) What should be the minimum sizes of level 1 and 2 memories to achieve an average access time of less than 100 nsec?
(b) What is the average access time achieved using the chosen sizes of level 1 and level 2 memories?
Theory Explanation. |
Question 2 |
Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a write through cache. Which of the following statements is/are FALSE?
Each cache block in WB and WT has a dirty bit. | |
Every write hit in WB leads to a data transfer from cache to main memory. | |
Eviction of a block from WT will not lead to data transfer from cache to main memory | |
A read miss in WB will never lead to eviction of a dirty block from WB. |
Question 2 Explanation:
Option A: The given statement is false as cache blocks in WT will not have a dirty bit. Only the cache blocks in WB will have dirty bits associated with them.
Option B: Every write hit in WB need not lead to data transfer from cache to main memory, rather only when that particular block is being evicted there will be transfer from cache to main memory. There can be several write hits in WB before the block is evicted and all those writes will be propagated to the main memory at once. Hence the given statement is false.
Option C: The given statement is true because in WT the writes happen in parallel both in cache and main memory so at the eviction of a block in WT it will not lead to data transfer from cache to main memory.
Option D: A read miss in WB will fetch a new block from main memory and can lead to eviction of a dirty block. Hence the given statement is false.
Option B: Every write hit in WB need not lead to data transfer from cache to main memory, rather only when that particular block is being evicted there will be transfer from cache to main memory. There can be several write hits in WB before the block is evicted and all those writes will be propagated to the main memory at once. Hence the given statement is false.
Option C: The given statement is true because in WT the writes happen in parallel both in cache and main memory so at the eviction of a block in WT it will not lead to data transfer from cache to main memory.
Option D: A read miss in WB will fetch a new block from main memory and can lead to eviction of a dirty block. Hence the given statement is false.
There are 2 questions to complete.