###### Digital-Logic-Design

October 14, 2023###### Digital-Logic-Design

October 15, 2023# Digital-Logic-Design

Question 530 |

**Which of the following expression removes static hazard from a two level AND – OR gate implementation of xy +zx’** xy +zx’ | |

xy + zx’+ wxy | |

xy +zx’ +yz | |

xy + zx’ +wz |

**Question 530 Explanation:**

**→ A static hazard occurs if a circuit produces incorrect output value momentarily before stabilizing to its correct value.**

→ Generally Hazard occurs due to different delays in different paths of the circuit.

→ In the expression xy +zx’ the variable x is in true form in one term(xy) and in complement in other term(zx’).

→ Delay occurs due to the presence of NOT gate. If input xyz=111 then output is 1. If input xyz=011 then output stays momentarily in state 0 then settles in state 1.

→ Adding the term yz(select y from xy and z from zx’) eliminates the hazard.→ Generally Hazard occurs due to different delays in different paths of the circuit.

→ In the expression xy +zx’ the variable x is in true form in one term(xy) and in complement in other term(zx’).

→ Delay occurs due to the presence of NOT gate. If input xyz=111 then output is 1. If input xyz=011 then output stays momentarily in state 0 then settles in state 1.

→ Adding the term yz(select y from xy and z from zx’) eliminates the hazard.

Correct Answer: C

**Question 530 Explanation:**

**→ A static hazard occurs if a circuit produces incorrect output value momentarily before stabilizing to its correct value.**

→ Generally Hazard occurs due to different delays in different paths of the circuit.

→ In the expression xy +zx’ the variable x is in true form in one term(xy) and in complement in other term(zx’).

→ Delay occurs due to the presence of NOT gate. If input xyz=111 then output is 1. If input xyz=011 then output stays momentarily in state 0 then settles in state 1.

→ Adding the term yz(select y from xy and z from zx’) eliminates the hazard.→ Generally Hazard occurs due to different delays in different paths of the circuit.

→ In the expression xy +zx’ the variable x is in true form in one term(xy) and in complement in other term(zx’).

→ Delay occurs due to the presence of NOT gate. If input xyz=111 then output is 1. If input xyz=011 then output stays momentarily in state 0 then settles in state 1.

→ Adding the term yz(select y from xy and z from zx’) eliminates the hazard.

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