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Question 6366 – Software-quality
March 5, 2024
Question 17259 – NTA UGC NET JUNE 2023 Paper-1
March 5, 2024
Question 6366 – Software-quality
March 5, 2024
Question 17259 – NTA UGC NET JUNE 2023 Paper-1
March 5, 2024

Question 8690 – Computer-Organization

Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency.

    P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns.
    P2: Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns.
    P3: Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns.
    P4: Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 ns.

Which processor has the highest peak clock frequency?

Correct Answer: C

Question 55 Explanation: 
Clock period (CP) = max stage delay + overhead
So CPP1 = Max(1,2,2,1) = 2ns
CPP2 = Max(1,1.5,1.5,1.5) = 1.5ns
CPP3 = Max(0.5,1,1,0.6,1) = 1ns
CPP4 = Max(0.5,0.5,1,1,1.1)=1.1ns

As frequency ∝ 1/C.P, so least clock period will give the highest peak clock frequency.
So, fP3 = 1/1ns = 1GHz
A
P1
B
P2
C
P3
D
P4
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