## ISRO CS 2009

 Question 1
If G is a graph with e edges and n vertices, the sum of the degrees of all vertices in G is
 A e B e/2 C e2 D 2 e
Engineering-Mathematics       Graph-Theory
Question 1 Explanation:

Handshaking theorem states that the sum of degrees of the vertices of a graph is twice the number of edges.

If G=(V,E) be a graph with E edges,then-

Σ degG(V) = 2E

This theorem applies even if multiple edges and loops are present.

Since the given graph is undirected, every edge contributes as twice in sum of degrees. So the sum of degrees is 2e.
 Question 2
In networking, UTP stands for
 A Unshielded T-connector port B Unshielded twisted pair C Unshielded terminating pair D Unshielded transmission process
Computer-Networks       UTP
Question 2 Explanation:
Unshielded twisted pair (UTP) is a ubiquitous type of copper cabling used in telephone wiring and local area networks (LANs).
There are five types of UTP cables -- identified with the prefix CAT, as in category -- each supporting a different amount of bandwidth.g a different amount of bandwidth.
 Question 3
The address resolution protocol (ARP) is used for
 A Finding the IP address from the DNS B Finding the IP address of the default gateway C Finding the IP address that corresponds to a MAC address D Finding the MAC address that corresponds to an IP address
Computer-Networks       ARP
Question 3 Explanation:
The Address Resolution Protocol (ARP) is a communication protocol used for discovering the link layer address, such as a MAC address, associated with a given internet layer address, typically an IPv4 address.
 Question 4
Which of the following is a MAC address?
 A 192.166.200.50 B 00056A:01A01A5CCA7FF60 C 568, Airport Road D 01:A5:BB:A7:FF:60
Computer-Networks       MAC
Question 4 Explanation:
A media access control address (MAC address) of a device is a unique identifier assigned to a network interface controller (NIC).
MAC addresses are recognizable as six groups of two hexadecimal digits, separated by hyphens, colons, or no separator.
Option (A) is example for IP address
Option (B) and (C ) are not examples for any address representation in computer
01:A5:BB:A7:FF:60 is the MAC address which consists of six groups of two hexadecimal digits, separated by hyphens, colons, or no separator.
 Question 5
What is the primary purpose of a VLAN?
 A Demonstrating the proper layout for a network B Simulating a network C To create a virtual private network D Segmenting a network inside a switch or device
Computer-Networks       VLAN
Question 5 Explanation:
1. A virtual local area network (VLAN) is a logical group of workstations, servers and network devices that appear to be on the same LAN despite their geographical distribution. A VLAN allows a network of computers and users to communicate in a simulated environment as if they exist in a single LAN and are sharing a single broadcast and multicast domain.
2. Higher-end switches allow the functionality and implementation of VLANs.
3. VLANs address issues such as scalability, security, and network management. Network architects set up VLANs to provide network segmentation
 Question 6
SHA-1 is a
 A encryption algorithm B decryption algorithm C key exchange algorithm D message digest function
Computer-Networks       SHA-1
Question 6 Explanation:
SHA-1 produces a 160-bit hash value or message digests from the inputted data (data that requires encryption), which resembles the hash value of the MD5 algorithm.
 Question 7
Advanced Encryption Standard (AES) is based on
 A Asymmetric key algorithm B Symmetric key algorithm C Public key algorithm D Key exchange
Computer-Networks       AES
Question 7 Explanation:
The Advanced Encryption Standard, or AES, is a symmetric block cipher chosen by the U.S. government to protect classified information.
AES is Symmetric key algorithm
 Question 8
The primary purpose of an operating system is
 A To make most efficient use of the computer hardware B To allow people to use the computer C To keep systems programmers employed D To make computers easier to use
Operating-Systems       Process-Threads
Question 8 Explanation:
Explanation: An operating system has three main functions:
(1) manage the computer’s resources, such as the central processing unit, memory, and other input – output sources
(2) establish a user interface, and
(3) execute and provide services for applications software.
OS provides an interface between the user and the hardware and thus making the computer easy to use for the user but the primary function of OS is to manage the hardware in the most efficient way.
 Question 9
Which is the correct definition of a valid process transition in an operating system?
 A Wake up: ready → running B Dispatch: ready → running C Block: ready → running D Timer runout: ready → running
Operating-Systems       Process-Threads
Question 9 Explanation:
From the below process state diagram, we can easily that the option (B) is correct. Question 10
The correct matching of the following pairs is
(A) Disk check           (1) Round robin
(B) Batch processing     (2) Scan
(C) Time sharing         (3) LIFO
(D) Stack operation      (4) FIFO
 A A B C D 3 4 2 1 B A B C D 4 3 2 1 C A B C D 3 4 1 2 D A B C D 2 4 1 3
Operating-Systems       CPU-Scheduling
Question 10 Explanation:
Scan is disk scheduling algorithm
In the round robin algorithm, each process will execute for particular time quantum,So it is the example for time sharing,
Stack is last in first out(LIFO)
In the batching processing, whatever process arrives first, it execute that process. So it First in First out(FIFO)
 Question 11
A page fault
 A Occurs when a program accesses an available page on memory B is an error in a specific page C is a reference to a page belonging to another program D occurs when a program accesses a page not currently in memory
Operating-Systems       CPU-Scheduling
Question 11 Explanation:
A page fault is a type of exception raised by computer hardware when a running program accesses a memory page that is not currently mapped by the memory management unit (MMU) into the virtual address space of a process
 Question 12
The infix expression A+(B–C)*D is correctly represented in prefix notation as
 A A+B−C∗D B +A∗−BCD C ABC−D∗+ D A+BC−D∗
Data-Structures       Prefix-Postfix-Expression
Question 12 Explanation:

Given Expression = A + (B – C)* D

Prefix Notation:

A + (- B C) * D

A + (* - B C D)

+ A * - B C D
 Question 13
If the pdf of a Poisson distribution is given by f(x) = (e-22x)/x!, then its mean is
 A 2x B 2 C -2 D 1
Engineering-Mathematics       Poisson-Distribution
Question 13 Explanation:
Given the function f(x) = (e-22x)/x!

Poisson Formula. Suppose we conduct a Poisson experiment, in which the average number of successes within a given region is μ.

Then, the Poisson probability is: P(x; μ) = (e) (μx) / x!

where x is the actual number of successes that result from the experiment, and e is approximately equal to 2.71828.

From the given function the “μ” value is 2 which is the mean.
 Question 14
If the mean of a normal frequency distribution of 1000 items is 25 and its standard deviation is 2.5, then its maximum ordinate is
 A (1000/√2π).e-25 B 1000/√2π C (1000/√2π ).e-2.5 D 400/√2π
Engineering-Mathematics       Normal-Distribution
Question 14 Explanation: Question 15
Consider a system having “n” resources of same type. These resources are shared by 3 processes, A, B, C. These have peak demands of 3, 4, and 6 respectively. For what value of “n” deadlock won’t occur
 A 15 B 9 C 10 D 11
Operating-Systems       Deadlock
Question 15 Explanation:
Number of min resources required = (3-1) + (4-1) + (6-1) + 1 = 11
 Question 16
Consider a set of 5 processes whose arrival time, CPU time needed and the priority are given below: (smaller the number, higher the priority)
If the CPU scheduling policy is priority scheduling without preemption, the average waiting time will be
 A 12.8 ms B 11.8 ms C 10.8 ms D 9.8 ms
Operating-Systems       CPU-Scheduling
Question 16 Explanation:
Following is the Gantt diagram: Average Waiting Time = (30 + 3 + 3 + 18)/ 5 = 10.8
 Question 17
The range of integers that can be represented by n bit 2’s complement number system is:
 A -2n-1 to (2n-1 – 1) B -(2n-1 – 1)to (2n-1 – 1) C -2n-1 to (2n-1 ) D -(2n-1 + 1)to (2n-1 – 1)
Digital-Logic-Design       Number-system
Question 17 Explanation:
The range of integers that can be represented by n bit 2’s complement number system is -2n-1 to (2n-1 – 1).
 Question 18
Which of the following is/are true of the auto-increment addressing mode?
I. It is useful in creating self-relocating code
II. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation
III. The amount of increment depends on the size of the data item accessed
 A I only B II only C III only D ) II only
Computer-Organization       Addressing-Modes
Question 18 Explanation:
After determining the effective address, the value in the base register is incremented by the size of the data item that is to be accessed.
For example, (A7)+ would access the content of the address register A7, then increase the address pointer of A7 by 1 (usually 1 word). Within a loop, this addressing mode can be used to step through all the elements of an array or vector.
 Question 19
In which addressing mode, the effective address of the operand is generated by adding a constant value to the content of a register?
 A Absolute mode B Indirect mode C Immediate mode D Index mode
Computer-Organization       Addressing-Modes
Question 19 Explanation:
1. An absolute address is represented by the contents of a register. This addressing mode is absolute in the sense that it is not specified relative to the current instruction address.

2. Indirect addressing is a scheme in which the address specifies which memory word or register contains not the operand but the address of the operand.

Immediate Operand:

The simplest way for an instruction to specify an operand is for the address part of the instruction actually to contain the operand itself rather than an address or other information describing where the operand is. Such an operand is called an immediate operand because it is automatically fetched from memory at the same time the instruction itself is fetched. It is immediately available for use.

Index mode:

The address of the operand is obtained by adding to the contents of the general register (called index register) a constant value. The number of the index register and the constant value are included in the instruction code
 Question 20
A certain microprocessor requires 4.5 microseconds to respond to an interrupt. Assuming that the three interrupts I1, I2 and I3 require the following execution time after the interrupt is recognized:
i. I1 requires 25 microseconds
ii. I2 requires 35 microseconds
iii. I3 requires 20 microseconds
I1 has the highest priority and I3 has the lowest. What is the possible range of time for I3 to be executed assuming that it may or may not occur simultaneously with other interrupts?
 A 24.5 microseconds to 39.5 microseconds B 24.5 microseconds to 93.5 microseconds C 4.5 microseconds to 24.5 microseconds D 29.5 microseconds 93.5 microseconds
Computer-Organization       Microprocessor
Question 20 Explanation:
Consider case-1: I3 is executed without other interrupts:

Time interval = Interrupt processing time(I3) + Execution time(I3) = 4.5 + 20 microseconds = 24.5 microseconds

Consider case-2: I3 is executed simultaneously with other interrupts:

Time interval =( Interrupt processing time + Execution time) for I1, I2, I3 = 4.5 + 25 + 4.5 + 35 + 4.5 + 20 = 93.5 microseconds
 Question 21
The process of organizing the memory into two banks to allow 8 and 16-bit data operation is called
 A Bank switching B Indexed mapping C Two-way memory interleaving D Memory segmentation
Computer-Organization       Memory-Interfacing
Question 21 Explanation:
Interleaved memory is a design made to compensate for the relatively slow speed of dynamic random-access memory (DRAM) or core memory, by spreading memory addresses evenly across memory banks.
Contiguous memory reads and writes are using each memory bank in turn, resulting in higher memory throughputs due to reduced waiting for memory banks to become ready for desired operations.
Two-Way Interleaved : Two memory blocks are accessed at same time for writing and reading operations
 Question 22
Suppose the numbers 7, 5, 1, 8, 3, 6, 0, 9, 4, 2 are inserted in that order into an initially empty binary search tree. The binary search tree uses the usual ordering on natural numbers. What is the inorder traversal sequence of the resultant tree?
 A 7 5 1 0 3 2 4 6 8 9 B 0 2 4 3 1 6 5 9 8 7 C 0 1 2 3 4 5 6 7 8 9 D 9 8 6 4 2 3 0 1 5 7
Data-Structures       Binary-search-tree
Question 22 Explanation:
Binary search trees (BST), sometimes called ordered or sorted binary trees, are a particular type of container: data structures that store "items" (such as numbers, names etc.) in memory.

The in-order traversal of BST will gives the elements in the sorted order( ascending order)
 Question 23
A data structure is required for storing a set of integers such that each of the following operations can be done in O(log n) time, where n is the number of elements in the set.
I. Deletion of the smallest element
II. Insertion of an element if it is not already present in the set
Which of the following data structures can be used for this purpose?
 A A heap can be used but not a balanced binary search tree B A balanced binary search tree can be used but not a heap C Both balanced binary search tree and heap can be used D Neither balanced search tree nor heap can be used
Data-Structures       Binary-search-tree
Question 23 Explanation:
Heap is a balanced binary tree (or almost complete binary tree), insertion complexity for heap is O(logn). We can get smallest element from the min heap in O(logn) time. But we can’t insert an element if it is not already present in O(logn) time .

A self-balancing binary search tree containing n items allows the lookup, insertion, and removal of an item in O(log n) worst-case time. Since it’s a self balancing BST, we can easily find out minimum element in O(logn) time which is always the leftmost element.
 Question 24
The following numbers are inserted into an empty binary search tree in the given order: 10, 1, 3, 5, 15, 12, 16. What is the height of the binary search tree (the height is the maximum distance of a leaf node from the root)?
 A 2 B 3 C 4 D 6
Data-Structures       Binary-search-tree
Question 24 Explanation: So, height of the tree is defined maximum distance of a leaf node from the root.The root node is “10” and lead node is “5”.The maximum distance is 3
 Question 25
Assume that the operators +, −, × are left associative and ^ is right associative. The order of precedence (from highest to lowest) is ^, ×, +, −. The postfix expression corresponding to the infix expression is a + b × c − d ^ e ^ f
 A abc x + def ^ ^ − B abc x + de ^ f ^ − C ab + c × d − e^f^ D − + a × b c^^ def
Data-Structures       Prefix-Postfix-Expression
Question 25 Explanation:

The operators in the expression are +,x,- ^

First we will convert e^f ad ef^ (as highest precedence and right associativity) and later

d ^( e f ^ ) to def^^ and so on , you can find the same thing from the below steps.

The postfix expression:

a + b × c − ( d ^( e ^ f))

a + b × c − ( d ^( e f ^ ))

a + b × c − ( d e f ^ ^)

(a + (b × c)) − d e f ^ ^

(a + (b c x)) − d e f ^ ^

(a (b c x) +) − d e f ^ ^

(a b c x +) - (d e f ^ ^)

(a b c x +) - (d e f ^ ^)

a b c x + d e f ^ ^ -
 Question 26
A one dimensional array A has indices 1….75. Each element is a string and takes up three memory words. The array is stored at location 1120 decimal. The starting address of A is
 A 1267 B 1164 C 1264 D 1169
Data-Structures       Arrays
Question 26 Explanation:
Given data is each string takes up three memory words which is nothing but size is 3.
Base or starting address of the array is 1120.
The address of the 49th element = base address of array + number of elements before current element * size of element
= 1120 + 48 * 3 = 1264
 Question 27
The five items: A, B, C, D, and E are pushed in a stack, one after other starting from A. The stack is popped four items and each element is inserted in a queue. The two elements are deleted from the queue and pushed back on the stack. Now one item is popped from the stack. The popped item is
 A A B B C C D D
Data-Structures       Queues-and-Stacks
Question 27 Explanation: Question 28
A full binary tree with n leaves contains:
 A n nodes B log2 n nodes C 2n-1 D 2n
Data-Structures       Binary-Trees
Question 28 Explanation:
A Binary Tree is full if every node has 0 or 2 children. So, in such case, the binary tree with n leaves contains a total of 2*n-1 nodes. Question 29
The expression 1 * 2 ^ 3 * 4 ^ 5 * 6 will be evaluated as
 A 3230 B 16230 C 49152 D 173458
Data-Structures       Prefix-Postfix-Expression
Question 29 Explanation:
The expression consists of the following operators *, ^
Between * and ^ , operator ‘^’ is highest precedence so it will execute first.
The expression consists of more than one ‘^’ operator is presented then it will follow right to left associativity.
Multiplication operator associativity is left to right.
1 * 2 ^ 3 * 4 ^ 5 * 6 = 1 * (2 ^ 3)* (4 ^ 5) * 6
= 1 * 8 * 1024 * 6
= 49152
 Question 30
The feature in object-oriented programming that allows the same operation to be carried out differently, depending on the object, is:
 A Inheritance B Polymorphism C Over functioning D Overriding
Java       OOp-concepts
Question 30 Explanation:
In object-oriented programming, inheritance is the mechanism of basing an object or class upon another object (prototype-based inheritance) or class (class-based inheritance), retaining similar implementation.

In any object-oriented programming language,Overriding is a feature that allows a subclass or child class to provide a specific implementation of a method that is already provided by one of its superclasses or parent classes

Polymorphism is the provision of a single interface to entities of different types or the use of a single symbol to represent multiple different types
 Question 31
The micro instructions stored in the control memory of a processor have a width of 26 bits. Each micro instruction is divided into three fields. a micro operation field of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX. How many bits are there in the X and Y fields, and what is the size of the control memory in number of words
 A 10, 3, 1024 B 8, 5, 256 C 5, 8, 2048 D 10, 3, 512
Computer-Organization       Microprogrammed-Control-Unit
Question 31 Explanation:
The number of bits in Control memory =26.
From the given data each instruction divided into op field (13)+X(next address field)+Y(MUX)
8(23) status bits in the inputs of the MUX then three bits in the MUX select field.
No. of bits in control memory next address field=26-13-3 =10
size of the control memory in number of words is 210=1024 words
 Question 32
A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)?
 A 400 B 500 C 600 D 700
Computer-Organization       Machine-Instructions
Question 32 Explanation:
C.P.U will use 24- bit instructions and instructions size(bytes) is 24/8 = 3 bytes

Program execution will start from address at 300 and from there on words every operation will takes 3- bytes and so on , So the address should be multiple of “3”. From the given options only 600 address value is valid.
 Question 33
Consider a disk pack with 16 surfaces, 128 tracks per surface and 256 sectors per track. 512 bytes of data are stored in a bit serial manner in a sector. The capacity of the disk pack and the number of bits required to specify a particular sector in the disk are respectively
 A 256 Mbyte, 19 bits B 256 Mbyte, 28 bit C 512 Mbyte, 20 bits D 64 Gbyte, 28 bits
Computer-Organization       Disk-scheduling
Question 33 Explanation:
Number of surfaces =16
Tracks per surface=128
Sectors per track=256
Data which will store per sector=512 bytes
Capacity of the disk = 16 surfaces X 128 tracks X 256 sectors X 512 bytes = 256 Mbytes.
The number of bits required to access a sector =Total number of sectors.
= 16 surfaces X 128 tracks X 256 sectors
=24x27x28=219
 Question 34
A processor that has carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2’s complement numbers 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be
 A 1, 1, 0 B 1, 0, 0 C 0, 1, 0 D 1, 0, 1
Digital-Logic-Design       Number-system
Question 34 Explanation: Question 35
The two numbers given below are multiplied using the Booth’s algorithm Multiplicand: 0101 1010 1110 1110 Multiplier: 0111 0111 1011 1101 How many additions/subtractions are required for the multiplication of the above two numbers?
 A 6 B 8 C 10 D 12
Digital-Logic-Design       Booth\'s-algorithm
Question 35 Explanation: Question 36
The addition of 4-bit, two’s complement, binary numbers 1101 and 0100 results in
 A 0001 and an overflow B 1001 and no overflow C 0001 and no overflow D 1001 and an overflow
Digital-Logic-Design       Number-Systems
Question 36 Explanation:
Number one is 0100 (4-Decimal value)
Another number is 1101(-3 is decimal value)
Adding of -3 and 4, the result is 1 and there is no overflow
 Question 37
Which of the following statements about relative addressing mode is FALSE?
 A It enables reduced instruction size B It allows indexing of array element with same instruction C It enables easy relocation of data D It enables faster address calculation than absolute addressing
Computer-Organization       Addressing-Modes
Question 37 Explanation:
Relative address means an address specified by indicating its distance from another address, called the base address.
In absolute addressing, you specify the actual address (called the absolute address) of a memory location.
 Question 38
Substitution of values for names (whose values are constants) is done in
 A Local optimization B Loop optimization C Constant folding D Strength reduction
Compiler-design       Code-Optimization
Question 38 Explanation:
Expressions with constant operands can be evaluated at compile time, thus improving run-time performance and reducing code size by avoiding evaluation at compile-time.
Example:
In the code fragment below, the expression (3 + 5) can be evaluated at compile time and replaced with the constant 8.

int f (void)
{
return 3 + 5;
}

Below is the code fragment after constant folding.

int f (void)
{
return 8;
}
 Question 39
The cubic polynomial y(x) which takes the following values:
y(0) = 1,
y(1) = 0,
y(2) = 1,
y(3) = 10 is
 A x3 +2 x2 + 1 B x3 + 3x2 + 1 C x3 + 1 D x3 – 2 x2 + 1
Engineering-Mathematics       Functions
Question 39 Explanation:
Substitute the values of x (0,1,2 and 3) in the options and check which option gives the corresponding y(x) values. The function x3 – 2 x2 + 1 gives the required values.
x = 0: y(x) = 1
x = 1: y(x) = 0
x = 2: y(x) = 8 - 8 + 1 = 1
x = 3: y(x) = 27 - 18 + 1 = 10
 Question 40
x = a cos(t), y = b sin(t) is the parametric form of
 A Ellipse B Hyperbola C Circle D Parabola
Engineering-Mathematics       Calculus
Question 40 Explanation:
An ellipse can be defined as the locus of all points that satisfy the equations
x = a cos t
y = b sin t
where:
x,y are the coordinates of any point on the ellipse,
a, b are the radius on the x and y axes respectively,
t is the parameter, which ranges from 0 to 2π radians
 Question 41
The value of x at which y is minimum for y = x2 − 3x + 1 is
 A -3/2 B 3/2 C 0 D -5/4
Engineering-Mathematics       Calculus
Question 41 Explanation:
Given function is y = x2 – 3x + 1
To find the minimum value, calculate the derivative until at what point given function is minimum value.
Applying First order derivative to the function y is y’ = 2x – 3
Again applying derivative of y ’is y” = 2 (Since y” > 0, it has a minimum value)
So the minima value at that point is (2x – 3) = 0 and x = 3/2
 Question 42
A graph in which all nodes are of equal degree, is known as
 A Multigraph B Non regular graph C Regular graph D Complete graph
Engineering-Mathematics       Graph-Theory
Question 42 Explanation: Question 43
In a graph G there is one and only one path between every pair of vertices then G is a
 A Path B Walk C Tree D Circuit
Engineering-Mathematics       Graph-Theory
Question 43 Explanation:
A graph is a tree if and only if there is exactly one path between every pair of its vertices.

Let G be a graph and let there be exactly one path between every pair of vertices in G. So G is connected. Now G has no cycles, because if G contains a cycle, say between vertices u and v, then there are two distinct paths between u and v, which is a contradiction. Thus G is connected and is without cycles, therefore it is a tree.

A tree is a minimally connected graph i.e. removing a single edge will disconnect the graph. A tree with n vertices has n−1 edges and only one path exists between every pair of vertices.
 Question 44
A simple graph ( a graph without parallel edge or loops) with n vertices and k components can have at most
 A n edges B n-k edges C (n − k)(n − k + 1) edges D (n − k)(n − k + 1)/2 edges
Engineering-Mathematics       Graph-Theory
Question 44 Explanation:
Let G be a graph with k components. Let ni be the number of vertices in the ith component, where 1 ≤ i ≤ k. Then, the number of edges in G is equal to sum of the edges in each of its components.

So, G has maximum number of edges if each component is a complete graph.

Hence, the maximum possible number of edges in the graph G is: And in every case, (n − k)(n − k + 1)/2 will be greater than or equal to the above expression.

So, at maximum, there can be (n − k)(n − k + 1)/2 edges in a simple graph with n vertices and k components.
 Question 45
Consider the polynomial, p(x) = a0 + a1X + a2X2 + a3X3 where ai ≠ 0, ∀i . The minimum number of multiplications needed to evaluate p on an input X is:
 A 3 B 4 C 6 D 9
Engineering-Mathematics       Functions
Question 45 Explanation:
P(X)=a0+a1+a2X2+a3X3
=a0+X(a1+X(a2+a3X))
↓ ↓ ↓
③ ② ①
Here, minimum 3 multiplication needed
 Question 46
A square matrix A is called orthogonal if A’A =
 A I B A C -A D -I
Engineering-Mathematics       Linear-Algebra
Question 46 Explanation:
An orthogonal matrix is a square matrix whose columns and rows are orthogonal unit vectors (i.e., orthonormal vectors), i.e. AAT=ATA =I (Identity matrix)
This leads to the equivalent characterization: a matrix Q is orthogonal if its transpose is equal to its inverse: AT=A-1
 Question 47
If two adjacent rows of a determinant are interchanged, the value of the determinant
 A becomes zero B remains unaltered C becomes infinitive D becomes negative of its original value
Engineering-Mathematics       Ls
Question 47 Explanation:
If any two rows (or columns) of a determinant are interchanged, then sign of determinant changes.
The value of the determinant remains unchanged if both rows and columns are interchanged.
 Question 48
If A, B, C are any three matrices, then A’+ B’+ C’ is equal to
 A a null matrix B A+B+C C (A+B+C)’ D -(A+B+C)
Engineering-Mathematics       Linear-Algebra
Question 48 Explanation: Question 49
Activities which ensure that the software that has been built, is traceable to customer requirement is covered as part of
 A Verification B Validation C Maintenance D Modeling
Software-Engineering       Software-testing
Question 49 Explanation:
Verification is the process of evaluating products of a development phase to find out whether they meet the specified requirements.
Validation is the process of evaluating software at the end of the development process to determine whether software meets the customer expectations and requirements.
 Question 50
A testing method which is normally used as the acceptance test for a software system, is
 A Regression Testing B Integration Testing C Unit Testing D System Testing
Software-Engineering       Software-testing
Question 50 Explanation:
System testing is the type of testing to check the behaviour of a complete and fully where to buy generic modafinil integrated software product based on the software requirements specification (SRS) document. The main focus of this testing is to evaluate Business / Functional / End-user requirements.
Regression testing is type of testing carried out to ensure that changes made in the fixes or any enhancement changes are not impacting the previously working functionality. It is executed after enhancement or defect fixes in the software or its environment.
A Unit testing is a Level of Testing where smallest part of individual unit / component (called unit) is tested to determine if they are fit for use
 Question 51
The ‘command’ used to change contents of one database using the contents of another database by linking them on a common key field?
 A Replace B Join C Change D Update
Database-Management-System       DML-commands
Question 51 Explanation:
1. The REPLACE() function replaces all occurrences of a substring within a string, with a new substring.

2. The UPDATE statement is used to modify the existing records in a table.

3.An SQL join clause - corresponding to a join operation in relational algebra - combines columns from one or more tables in a relational database. It creates a set that can be saved as a table or used as it is. A JOIN is a means for combining columns from one (self-join) or more tables by using values common to each. ANSI-standard SQL specifies five types of JOIN: INNER, LEFT OUTER, RIGHT OUTER, FULL OUTER and CROSS. As a special case, a table (base table, view, or joined table) can JOIN to itself in a self-join.

4.There is no change command in SQL
 Question 52
A locked database file can be
 A Accessed by only one user B Modified by users with the correct password C Used to hide sensitive information D Updated by more than one user
Database-Management-System       Transactions
Question 52 Explanation:
File locking is a data management feature that restricts other users from changing a specific file.
This allows only one user or process access to this file at any given time.
This is to prevent the problem of interceding updates on the same files.
 Question 53
Which of the following contains complete record of all activity that affected the contents of a database during a certain period of time?
 A Transaction log B Query language C Report writer D Data manipulation language
Database-Management-System       Transactions
Question 53 Explanation:
The transaction log is an integral part of database.
Every database has a transaction log that is stored within the log file that is separate from the data file.
A transaction log basically records all database modifications. When a user issues an INSERT, for example, it is logged in the transaction log.
This enables the database to roll back or restore the transaction if a failure were to occur and prevents data corruption.
 Question 54
Purpose of ‘Foreign Key’ in a table is to ensure
 A Null Integrity B Referential Integrity C Domain Integrity D Null and Domain Integrity
Database-Management-System       ER-Model
Question 54 Explanation:
A foreign key is a field (or collection of fields) in one table that uniquely identifies a row of another table or the same table.
In simpler words, the foreign key is defined in a second table, but it refers to the primary key or a unique key in the first table.
For example, a table called Employees has a primary key called employee_id.
Another table called Employee Details has a foreign key which references employee_id in order to uniquely identify the relationship between the two tables.
 Question 55
Which of the following scenarios may lead to an irrecoverable error in a database system?
 A A transaction writes a data item after it is read by an uncommitted transaction B A transaction reads a data item after it is read by an uncommitted transaction C A transaction reads a data item after it is written by a committed transaction D A transaction reads a data item after it is written by an uncommitted transaction
Database-Management-System       ACID-properties
Question 55 Explanation:
Irrecoverable error occurs when a transaction reads a data item after it is written by uncommitted transaction.
An irrecoverable error is an error that remains an error, no matter how many times you try to perform the same action. In the integration space, that could mean trying to access a database table that does not exist, which would cause the JDBC driver to throw back a SQLException
 Question 56
Use of IPSEC in tunnel mode results in
 A IP packet with same header B IP packet with new header C IP packet without header D No changes in IP packet
Computer-Networks       Network-Security
Question 56 Explanation:
IPSec can be used to create VPN Tunnels to end-to-end IP Traffic (also called as IPSec Transport mode) or site-to-site IPSec Tunnels (between two VPN Gateways, also known as IPSec Tunnel mode).
IPSec Tunnel mode: In IPSec Tunnel mode, the original IP packet (IP header and the Data payload) is encapsulated within another packet.
In IPSec tunnel mode the original IP Datagram from is encapsulated with an AH (provides no confidentiality by encryption) or ESP (provides encryption) header and an additional IP header. The IP addresses of the newly added outer IP header are that of the VPN Gateways.
The traffic between the two VPN Gateways appears to be from the two gateways (in a new IP datagram), with the original IP datagram is encrypted (in case of ESP) inside IPSec packet.
 Question 57
Special software to create a job queue is called a
 A Driver B Spooler C Interpreter D Linkage editor
Operating-Systems       Process-Threads
Question 57 Explanation:
Spooling is a specialized form of multi-programming for the purpose of copying data between different devices.
A dedicated program, the spooler, maintains an orderly sequence of jobs for the peripheral and feeds it data at its own rate
Conversely, for slow input peripherals, such as a card reader, a spooler can maintain a sequence of computational jobs waiting for data, starting each job when all of the relevant input is available
 Question 58
Process is:
 A A program in high level language kept on disk B Contents of main memory C A program in execution D A job in secondary memory
Operating-Systems       Process-Threads
Question 58 Explanation:
A process is the instance of a computer program that is being executed by one or many threads. It contains the program code and its activity.
Depending on the operating system (OS), a process may be made up of multiple threads of execution that execute instructions concurrently
 Question 59
On receiving an interrupt from an I/O device,the CPU
 A Halts for a predetermined time B Branches off to the interrupt service routine after completion of the current instruction C Branches off to the interrupt service routine immediately D Hands over control of address bus and data bus to the interrupting device
Computer-Organization       I/O-handling
Question 59 Explanation:
1. The CPU then performs a state save, and transfers control to the interrupt handler routine at a fixed address in memory. ( The CPU catches the interrupt and dispatches the interrupt handler)
2. The interrupt handler determines the cause of the interrupt, performs the necessary processing, performs a state restore, and executes a return from interrupt instruction to return control to the CPU. ( The interrupt handler clears the interrupt by servicing the device. )
 Question 60
Compared to CISC processors,RISC processors contain:
 A More registers and smaller instruction set B larger instruction set C less registers and smaller instruction set D more transistor elements
Computer-Organization       RISC-and-CISC
Question 60 Explanation:
A reduced instruction set computer, or RISC , is one whose instruction set architecture (ISA) allows it to have fewer cycles per instruction (CPI) than a complex instruction set computer (CISC).
In RISC architecture, the instruction set of the computer is simplified to reduce the execution time. It uses small and highly optimized set of instructions which are generally register to register operations
 Question 61
The switching expression corresponding to F(A,B,C,D)= Σ(1,4,5,9,11,12) is:
 A BC’D’ + A’C’D + AB’D B ABC’ + ACD + B’C’D C ACD’ + A’BC’ + AC’D’ D A’BD + ACD’ + BCD’
Digital-Logic-Design       K-Map
Question 61 Explanation:
The K-Map for the boolean function of four variables can be drawn as: Question 62
The shift operator E is defined as E[f(xi)] = f(xi + h) and E'[f(xi)] = f(xi – h) then △ (forward difference) in terms of E is
 A E-1 B E C 1 – E-1 D 1 – E
Engineering-Mathematics       Functions
Question 62 Explanation: Question 63
The formula: is called
 A Simpson rule B Trapezoidal rule C Romberg’s rule D Gregory’s formula
Engineering-Mathematics       Calculus
Question 63 Explanation:
The above formula is for trapezoidal rule. Question 64
The image A Newton’s backward formula B Gauss forward formula C Gauss backward formula D Stirling’s formula
Engineering-Mathematics       Calculus
Question 64 Explanation:
The above formula is NEWTON’S GREGORY BACKWARD INTERPOLATION FORMULA Question 65 A 2 B 3 C 4 D 5
Engineering-Mathematics
Question 65 Explanation:
From the given data is determinant = 3
The determinant of 2x2 matrix is (ad-bc), If the elements are a,b,c and d.
From the given matrix, a=3,b=3,c=x and d=5 then ad-bc =15-3x
15-3x=3 ⇒ 3x=12 ⇒ x=4
 Question 66 A 779 B 679 C 0 D 256
Engineering-Mathematics       Linear-Algebra
Question 66 Explanation:
Determinant of any symmetric matrix is zero
 Question 67
Let f(x) be the continuous probability density function of a random variable x, the probability that a < x ≤ b, is
 A f (b − a) B f (b) − f (a) C D Engineering-Mathematics       Probability
Question 67 Explanation:
A non-discrete random variable X is said to be absolutely continuous, or simply continuous, if its distribution function may be represented as Question 68
Consider three CPU-intensive processes, which require 10, 20 and 30 time units and arrive at times 0, 2 and 6, respectively. How many context switches are needed if the operating system implements a shortest remaining time first scheduling algorithm? Do not count the context switches at time zero and at the end.
 A 1 B 2 C 3 D 4
Operating-Systems       CPU-Scheduling
Question 68 Explanation: Question 69
The subnet mask for a particular network is 255.255.31.0. Which of the following pairs of IP addresses could belong to this network?
 A 172.57.88.62 and 172.56.87.23 B 10.35.28.2 and 10.35.29.4 C 191.203.31.87 and 191.234.31.88 D 128.8.129.43 and 128.8.161.55
Computer-Networks       IP-address
Question 69 Explanation:
To find whether hosts belong to same network or not , we have to find their net id, if net id is same then hosts belong to same network and net id can be find by ANDing subnet mask and IP address.
128.8.129.43 (Bitwise AND) 255.255.31.0 = 128.8.1.0
128.8.161.55 (Bitwise AND) 255.255.31.0 = 128.8.1.0
 Question 70
Using a larger block size in a fixed block size file system leads to
 A better disk throughput but poorer disk space utilization B better disk throughput and better disk space utilization C poorer disk throughput but better disk space utilization D poorer disk throughput and poorer disk space utilization
Operating-Systems       Disk-scheduling
Question 70 Explanation:
→ While using a larger block size means that contains less number of blocks then that results better throughput.
→ This can be implemented in a fixed block size then the space utilization is not upto the mark. So the statement results better disk throughput but poorer disk space utilization
 Question 71
Which of the following statements about synchronous and asynchronous I/O is NOT true?
 A An ISR is invoked on completion of I/O in synchronous I/O but not in asynchronous I/O B In both synchronous and asynchronous I/O, an ISR (Interrupt Service Routine) is invoked after completion of the I/O C A process making a synchronous I/O call waits until I/O is complete, but a process making an asynchronous I/O call does not wait for completion of the I/O D In the case of synchronous I/O, the process waiting for the completion of I/O is woken up by the ISR that is invoked after the completion of I/O
Computer-Organization       I/O-Management
Question 71 Explanation:
→ Synchronous I/O mean that some flow of execution (such as a process or thread) is waiting for the operation to complete.
Asynchronous I/O means that nothing is waiting for the operation to complete and the completion of the operation itself causes something to happen.
→ Synchronous I/O -- some execution vehicle (like a process or thread) that initiates the I/O also waits for the I/O to complete (and perhaps completes it). When the I/O completes, that same execution vehicle goes on to do something else, perhaps using the results of the I/O.
→ Asynchronous I/O -- no execution vehicle waits for the I/O to complete. When the I/O completes, whatever execution vehicle happens to complete the I/O may arrange for later things to happen.
Option B is not true, because both synchronous and asynchronous I/O, an ISR (Interrupt Service Routine) is not invoked after completion of the I/O.
 Question 72
Let G be an arbitrary graph with n nodes and k components. If a vertex is removed from G, the number of components in the resultant graph must necessarily lie down between
 A k and n B k-1 and k+1 C k-1 and n-1 D k+1 and n-k
Engineering-Mathematics       Graph-Theory
Question 72 Explanation:
→ While a vertex is removed from a graph then that can be itself be forms a new component. The minimum number of components is k-1.
→ If a vertex is removed then it results that all the components are also be disconnected. So removal can create (n-1) components
 Question 73
Consider the following code written in a pass-by-reference language like FORTRAN and these statements about the code.
subroutine swap(ix,iy)
it = ix
L1 : ix = iy
L2 : iy = it
end
ia = 3
ib = 8
call swap (ia, ib+5)
print *, ia, ib
end
S1: The compiler will generate code to allocate a temporary nameless cell, initialize it to 13, and pass the address of the cell to swap
S2: On execution the code will generate a runtime error on line L1
S3: On execution the code will generate a runtime error on line L2
S4: The program will print 13 and 8
S5: The program will print 13 and -2
Exactly the following set of statement(s) is correct:
 A S1 and S2 B S1 and S4 C S3 D S1 and S5
Programming-in-c++       Programming
Question 73 Explanation:
Swap operation perform between the ia and temporary nameless cell, therefore the value of ib is remains unchanged.
Swap (8, 13)
⇒ ia will returns value with 13.
⇒ ib is unchanged, because here we using pass by reference value.
➝ Temporary nameless is initialized to 13.
➝ There is No runtime error.
 Question 74
When a process is rolled back as a result of deadlock the difficulty which arises is
 A Starvation B System throughput C Low device utilization D Cycle stealing
Operating-Systems       Deadlock
Question 74 Explanation:

→ When a process is rolled back as a result of deadlock the difficulty which arises is starvation.
→ Resource starvation is a problem encountered in concurrent computing where a process is perpetually denied necessary resources to process its work.
→ Starvation may be caused by errors in a scheduling or mutual exclusion algorithm, but can also be caused by resource leaks, and can be intentionally caused via a denial-of-service attack such as a fork bomb
 Question 75
Consider a pipelined processor with the following four stages:
IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute
WB: Write Back
The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
ADD   R2, R1, R0 R2 ← R1 + R0
MUL   R4, R3, R2    R4 ← R3 * R2
SUB   R6, R5, R4    R6 ← R5 - R4
 A 7 B 8 C 10 D 14
Computer-Organization       Pipelining
Question 75 Explanation:
Since operand forwarding is there, by default we consider the operand forwarding from EX stage to EX stage. Question 76
The use of multiple register windows with overlap causes a reduction in the number of memory accesses for
1. Function locals and parameters
2. Register saves and restores
III. Instruction fetches
 A I only B II only C III only D I, II and III
Computer-Organization       Pipelining
Question 76 Explanation:
→ I is true because when we make a function call there are some input registers and some output registers. If function F() is calling function G(), we can make the caller function F()'s output registers the same as the called procedure G()'s input registers this is done using overlapping register windows.This will reduce the memory accesses so that F()'s output need not be put into memory for G() to access again from memory.
→ II is false as register saves and restores would still be required for each and every variable.
→ III is also false as instruction fetch is not affected by memory access using multiple register windows.
 Question 77
Consider the following boolean function of four variables, f (w, x, y,z) = Σ(1, 3, 4, 6, 9, 11, 12, 14], the function is
 A Independent of one variable B Independent of two variables C Independent of three variables D Dependent on all variables
Digital-Logic-Design       Boolean-Function
Question 77 Explanation: w and y are not needed to represent the function f. So f is independent of two variables.
 Question 78
A root of equation f(x) = 0 can be computed to any degree of accuracy if a ‘good’ initial approximation x0 is chosen for which
 A f (x0) > 0 B f (x0) f (x0)” > 0 C f (x0) f (x0)” < 0 D f (x0)” > 0
Engineering-Mathematics       Functions
 Question 79
Which of the following statement is correct
 A △(UkVk) = Uk△Vk + Vk△Uk B △(UkVk) = Uk+1△Vk + Vk+1△Uk C △(UkVk) = Vk+1△Uk + Uk△Vk D △(UkVk) = Uk+1△Vk + Vk△Uk
Engineering-Mathematics       Calculus
There are 79 questions to complete.
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