Higher-Education-and-Politics
August 23, 2023Operating-Systems
August 24, 2023ISRO CS 2020
Question 3 |
Minimum number of NAND gates required to implement the following binary equation
![](data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAIsAAAAeCAYAAAAcsu0PAAAAAXNSR0IArs4c6QAAAARnQU1BAACxjwv8YQUAAAAJcEhZcwAADsMAAA7DAcdvqGQAAALlSURBVHhe7ZbbrcIwDIY7I9JZCHUVGKUMwgNj5CSxoa1jx05TKir5k/JASxxf/tgdguMYcbE4ZlwsjhkXi2PGxeKY+QmxDMOgrj3h7EvLmXGxKMuZ8Ww4ZlwsjhkXi2OmFMtjhHl9nfAB4XkLl9r7KlMYh0u4PfHn6XiF298Qxgf+LBDie+dssWQbvYCPy7M+6+8W3xJSvbnnDGxned0v2XgZEDpiNE6ZrkO43Nt2vu7jV8WVfCqSWhN0LvwYZVHCxQf2ib2uC6eBNWJsgy+l79a6CGPorU5iGLvOpluR9/JJFqkUZk/gcsznsAVewCaXiy8/E+z05LKKLBbxnTHP8jcLqn9OSmqxkhM6uQBNe/E8Qxdrt72m2I+xi4VkhFH6UCtaYgqTWSiQC5uwlHNZAcMerbtUP3DhxoHhnIxCfehYKiq3PoVuCRaYrnH8pPO/LhbGt1pHyNA9XHztMcu02FLEIlyEXGsl11WxUDFsDlxN/prkeDorB2AQQZdYaJcoOioHuYlcfFp3amJHsUi2aB4YFLFEspGOYkToN0GVmOQRiyCLwNrRdMC39r1L39j4esWC+1e+LZYs5o1iyefVL7QuFjSuzbMadrGUIrCcu72zkA4RybYMvub/obD4+Fq6gcaOnUUSsUHcnWKx3XCrWKbrUtlg25KgzWLhbhMmTROp2lm0oqnvl+woFmnc/EpnYWc6Jf5nnQx7graKJReZjh0cu/VzoSCfnEjx1eI2nfNmL7FU3mV/6hf6GLEoweai0QAMSu+DiQsLqH+30Hjk+GCskTiwe20RuI4sCPCFFwR7cQgHiQUdLQIA2zC25oRCUPPqPZsCY2N9xmdZCsjcwmp3e4twsWxdYgsoFnJeXqIYSKcUMIhlJwxt7iwkYRSJPXN8udPpvh8nlgib5LNRSexZ47P6fahYoltx7HzzO+TbQLuWR8gJ40sdUf1GAw4Wi3NmXCyOGReLY8bF4phxsThGQvgHY2ta+VohOw8AAAAASUVORK5CYII=)
4 | |
5 | |
3 | |
6 |
Question 3 Explanation:
AND-OR (or SOP)realization is easily convertible into NAND-NAND realization.
NOT-OR is equivalent to NAND.
Y = (A’+B’) (C+D)
Y = (A’+B’)C + (A’+B’)D
Let X= (A’+B’) , Y= C, and Z= D
One NAND gate is needed for implementing X= (A’ + B’).
Y= XY + XZ
Y= [(XY)’ (XZ)’]’
Three NAND gates are needed for [(XY)’ (XZ)’]’.
Total Four NAND gates are required to implement thY = (A’+B’) (C+D).
NOT-OR is equivalent to NAND.
Y = (A’+B’) (C+D)
Y = (A’+B’)C + (A’+B’)D
Let X= (A’+B’) , Y= C, and Z= D
One NAND gate is needed for implementing X= (A’ + B’).
Y= XY + XZ
Y= [(XY)’ (XZ)’]’
Three NAND gates are needed for [(XY)’ (XZ)’]’.
Total Four NAND gates are required to implement thY = (A’+B’) (C+D).
Correct Answer: A
Question 3 Explanation:
AND-OR (or SOP)realization is easily convertible into NAND-NAND realization.
NOT-OR is equivalent to NAND.
Y = (A’+B’) (C+D)
Y = (A’+B’)C + (A’+B’)D
Let X= (A’+B’) , Y= C, and Z= D
One NAND gate is needed for implementing X= (A’ + B’).
Y= XY + XZ
Y= [(XY)’ (XZ)’]’
Three NAND gates are needed for [(XY)’ (XZ)’]’.
Total Four NAND gates are required to implement thY = (A’+B’) (C+D).
NOT-OR is equivalent to NAND.
Y = (A’+B’) (C+D)
Y = (A’+B’)C + (A’+B’)D
Let X= (A’+B’) , Y= C, and Z= D
One NAND gate is needed for implementing X= (A’ + B’).
Y= XY + XZ
Y= [(XY)’ (XZ)’]’
Three NAND gates are needed for [(XY)’ (XZ)’]’.
Total Four NAND gates are required to implement thY = (A’+B’) (C+D).
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