AC Flag: This flag is set if thee is a carry to fifth bit from the fourth bits if two numbers.

In 8085 microprocessor the address bus is of 16 bits and data bus is 8 bits.

Processing unit→ ALU
Arithmetic logic unit(ALU) is a fundamental building block of many types of computing circuits, including the central processing unit (CPU) of computers, FPUs, and graphics processing units (GPUs).
Instruction unit →Timing and control
Timing and Control unit is responsible for hardwired control unit and Microprogrammed control unit
Storage and Interface unit → General purpose Register
The general purpose register can store a data (or) a memory location address.

Index mode:
The address of the operand is obtained by adding to the contents of the general register (called index register) a constant value. The number of the index register and the constant value are included in the instruction code.
→ Index Mode is used to access an array whose elements are in successive memory locations (or) contiguous memory locations.

FALSE: In memory - mapped I/O, the CPU can manipulate I/O data residing in interface registers that are used to manipulate memory words.
TRUE: The isolated I/O method isolates memory and I/O addresses so that memory address range is not affected by interface address assignment.
FALSE: In asynchronous serial transfer of data the two units share a different clock.
FALSE: In synchronous serial transmission of data the two units have common clocks.

Given data, -- Micro-ops field F₁ = 7 distinct micro operations
-- Micro-ops field F₂ = 7 distinct micro operations
-- Micro-ops field F₃ = 7 distinct micro operations
-- Condition field(CD) = 4 status bits
-- Branch Field(BR) = 4 options
-- Address space =128 memory locations
-- Size of micro operation=?
Given microinstruction format

If a schedule is conflict serializable then no cycle in precedence graph should be present.
But BFS and DFS are also possible for cyclic graphs.
And topological sort is not possible for cyclic graph.
Moreover option (D) is also wrong because in a transaction with more indices might come before lower one.

1NF : A relation is in 1NF if it does not contain multi-value attributes and composite attributes.
2NF: A relation is in 2NF is there is no partial dependency exist in the relation. i.e.
primary_key → non-key attribute
prime_attribute → non-key attribute.
3NF : A relation is in 3NF if there is no transitive dependency or we can say that a relation is in 3NF if either LHS of a functional dependency is a super key or the RHS of the functional dependency is a prime key attribute.
4NF : A relation is in 4NF if there is no multivalued dependency exist in the relation.
Hence the correct answer is option (C)
NOTE: A prime key attribute is a attribute which is the part of primary key attributes. For example: If ABC is the the primary key then A,B,C, AB, AC, BC are the prime key attributes.

The attribute D is not part of any FD's. So, D can be a candidate key or it may be part of the candidate key.
Now D+ = {D}.
Hence we have to add A,B,C,E,F,G,H to D and check which of them are Candidate keys of size 2.
AD+ = {ABCDEFGH}
BD+ = {ABCDEFGH}
ED+ = {ABCDEFGH}
FD+= {ABCDEFGH}
But CD+, GD+ and HD+ does not give all the attributes hence CD, GD and HD are not candidate keys.
Here Candidate keys are AD, BD, ED and FD.
A → BC, B → CFH and F → EG etc are partial dependencies.
So given relation is in 1NF, but not in 2NF.

Option(A): Cartesian product with a empty table will result in zero tuple because we can't have any ordered pair with a empty table. Hence option(A) is incorrect option.
Option(B):

(A, B) (B, C) - common attribute is (B) and due to B→C, B is a key for (B, C) and hence ABC can be losslessly decomposed into (A, B)and (B, C).
(A, B, C) (B, D) - common attributes is B and B→D is a FD (via B→C, C→D), and hence, B is a key for (B, D). So, decomposition of (A, B, C, D) into (A, B, C) (B, D) is lossless.
Thus the given decomposition is lossless.
The given decomposition is also dependency preserving as the dependencies A→B is present in (A, B), B→C is present in (B, C), D→B is present in (B, D) and C→D is indirectly present via C→B in (B, C) and B→D in (B, D).

Memory tube display components:
1. Connector Pins
2. Electron Gun
3. Base
4. Focusing System
5. Control Grid Voltage
6. X/Y Deflect
7. Phosphor
8. Collector
9. Ground
Note: Liquid crystal is not a component of memory tube display
.