DigitalLogicDesign
Question 1 
In 16bit 2's complement representation, the decimal number 28 is:
1111 1111 1110 0100  
1111 1111 0001 1100  
0000 0000 1110 0100  
1000 0000 1110 0100 
1’s complement = 1111 1111 1110 0011
2’s complement = 1’s complement + 1
2’s complement = 1111 1111 1110 0100 = (28)
Question 2 
Two numbers are chosen independently and uniformly at random from the set {1, 2, ..., 13}. The probability (rounded off to 3 decimal places) that their 4bit (unsigned) binary representations have the same most significant bit is ______.
0.502  
0.461  
0.402  
0.561 
1  0001
2  0010
3  0011
4  0100
5  0101
6  0110
7  0111
8  1000
9  1001
10  1010
11  1011
12  1100
13  1101
The probability that their 4bit binary representations have the same most significant bit is
= P(MSB is 0) + P(MSB is 1)
= (7×7)/(13×13) + (6×6)/(13×13)
= (49+36)/169
= 85/169
= 0.502
Question 3 
Consider Z = X  Y, where X, Y and Z are all in signmagnitude form. X and Y are each represented in n bits. To avoid overflow, the representation of Z would require a minimum of:
n bits  
n + 2 bits  
n  1 bits  
n + 1 bits 
To store overflow/carry bit there should be extra space to accommodate it.
Hence, Z should be n+1 bits.
Question 4 
Which one of the following is NOT a valid identity?
(x + y) ⊕ z = x ⊕ (y + z)  
(x ⊕ y) ⊕ z = x ⊕ (y ⊕ z)  
x ⊕ y = x + y, if xy = 0  
x ⊕ y = (xy + x'y')' 
(x+y) ⊕ z = (1+1)⊕ 0 = 1 ⊕ 0 = 1
x ⊕ (y+z) = 1⊕(1+0) = 1 ⊕ 1 = 0
So,
(x+y) ⊕ z ≠ x ⊕ (y+z)
Question 5 
What is the minimum number of 2input NOR gates required to implement a 4variable function function expressed in sumofminterms form as f = Σ(0, 2, 5, 7, 8, 10, 13, 15)? Assume that all the inputs and their complements are available.
2  
4  
7  
1  
3(Option not given) 
Question 6 
Consider three 4variable functions f_{1}, f_{2} and f_{3}, which are expressed in sumofminterms as
f_{1} = Σ(0, 2, 5, 8, 14), f_{2} = Σ(2, 3, 6, 8, 14, 15), f_{3} = Σ(2, 7, 11, 14)
For the following circuit with one AND gate and one XOR gate, the output function f can be expressed as:
Σ (2, 14)  
Σ (7, 8, 11)  
Σ (2, 7, 8, 11, 14)  
Σ (0, 2, 3, 5, 6, 7, 8, 11, 14, 15) 
f3 = ∑(2,7,11,14)
f1*f2 ⊕ f3 = ∑(2,8,14) ⊕ ∑(2,7,11,14)
= ∑(8,7,11)
(Note: Choose the terms which are not common)
Question 7 
Let ⊕ and ⊙ denote the Exclusive OR and Exclusive NOR operations, respectively. Which one of the following is NOT CORRECT?
Question 8 
Consider the sequential circuit shown in the figure, where both flipflops used are positive edgetriggered D flipflops.
The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is ______
2  
3  
4  
5 
Now lets draw characteristic table,
D_{1} = Q_{0}
D_{0} = in
Question 9 
Consider the unsigned 8bit fixed point binary number representation below,

b_{7}b_{6}b_{5}b_{4}b_{3} ⋅ b_{2}b_{1}b_{0}
where the position of the binary point is between b_{3} and b_{2} . Assume b_{7} is the most significant bit. Some of the decimal numbers listed below cannot be represented exactly in the above representation:

(i) 31.500 (ii) 0.875 (iii) 12.100 (iv) 3.001
Which one of the following statements is true?
None of (i), (ii), (iii), (iv) can be exactly represented
 
Only (ii) cannot be exactly represented  
Only (iii) and (iv) cannot be exactly represented  
Only (i) and (ii) cannot be exactly represented 
= 16 + 8 + 4 + 2 + 1 + 0.5
= (31.5)_{10}
(ii) (0.875)_{10} = (00000.111)_{2}
= 2^{1} + 2^{2} + 2^{3}
= 0.5 + 0.25 + 0.125
= (0.875)_{10}
(iii) (12.100)_{10}
It is not possible to represent (12.100)_{10}
(iv) (3.001)_{10} It is not possible to represent (3.001)_{10}
Question 10 
Consider the minterm list form of a Boolean function F given below.
 F(P, Q, R, S) = Σm(0, 2, 5, 7, 9, 11) + d(3, 8, 10, 12, 14)
Here, m denotes a minterm and d denotes a don’t care term. The number of essential prime implicants of the function F is _______.
3  
4  
5 
There are 3 prime implicant i.e., P’QS, Q’S’ and PQ’ and all are essential.
Because 0 and 2 are correct by only Q’S’, 5 and 7 are covered by only P’QS and 8 and 9 are covered by only PQ’.
Question 11 
The nbit fixedpoint representation of an unsigned real number X uses f bits for the fraction part. Let i = nf. The range of decimal values for X in this representation is
2^{f} to 2^{i}  
2^{f} to (2^{i}  2^{f})  
0 to 2^{i}  
0 to (2^{i}  2^{f }) 
Number of bits in fraction part → fbits
Number of bits in integer part → (n – f) bits
Minimum value:
000…0.000…0 = 0
Maximum value:
= (2^{ nf }  1) + (1  2 ^{f}
= (2^{nf}  2 ^{f})
= (2^{i}  2 ^{ f })
Question 12 
When two 8bit numbers A_{7}...A_{0} and B_{7}...B_{0} in 2’s complement representation (with A_{0} and B_{0} as the least significant bits) are added using a ripplecarry adder, the sum bits obtained are S_{7}...S_{0} and the carry bits are C_{7}...C_{0}. An overflow is said to have occurred if
the carry bit C_{7} is 1  
all the carry bits (C_{7},…,C_{0}) are 1  
i.e., A_{7} = B_{7}
⇾ Overflow can be detected by checking carry into the sign bits (C_{in}) and carry out of the sign bits (C_{out}).
⇾ Overflow occurs iff A_{7} = B_{7} and C_{in} ≠ C_{out}
These conditions are equivalent to
Consider
Here A_{7} = B_{7} = 1 and S_{7} = 0
This happens only if C_{in} = 0
Carry out C_{out}=1 when
Similarly, in case of
C_{in}=1 and C_{out} will be 0.
Question 13 
Consider the Karnaugh map given below, where X represents “don’t care” and blank represents 0.
Assume for all inputs , the respective complements are also available. The above logic is implemented using 2input NOR gates only. The minimum number of gates required is _________.
1  
2  
3  
4 
As all variables and their complements are available we can implement the function with only one NOR Gate.
Question 14 
Consider a combination of T and D flipflops connected as shown below. The output of the D flipflop is connected to the input of the T flipflop and the output of the T flipflop is connected to the input of the D flipflop.
Initially, both Q_{0} and Q_{1} are set to 1 (before the 1^{st} clock cycle). The outputs
Q_{1}Q_{0} after the 3^{rd} cycle are 11 and after the 4^{th} cycle are 00 respectively  
Q_{1}Q_{0} after the 3^{rd} cycle are 11 and after the 4^{th} cycle are 01 respectively  
Q_{1}Q_{0} after the 3^{rd} cycle are 00 and after the 4^{th} cycle are 11 respectively  
Q_{1}Q_{0} after the 3^{rd} cycle are 01 and after the 4^{th} cycle are 01 respectively 
Question 15 
The representation of the value of a 16bit unsigned integer X in hexadecimal number system is BCA9. The representation of the value of X in octal number system is
136251  
736251  
571247  
136252 
Each hexadecimal digit is equal to a 4bit binary number. So convert
X = (BCA9)_{16} to binary
Divide the binary data into groups 3 bits each because each octal digit is represented by 3bit binary number.
X = (001 011 110 010 101 001)_{2}
Note: Two zeroes added at host significant position to make number bits of a multiple of 3 (16 + 2 = 18)
X = (136251)_{8}
Question 16 
Given the following binary number in 32bit (single precision) IEEE754 format:
The decimal value closest to this floatingpoint number is
1.45 × 10^{1}  
1.45 × 10^{1}  
2.27 × 10^{1}  
2.27 × 10^{1} 
For singleprecision floatingpoint representation decimal value is equal to (1)^{5} × 1.M × 2^{(E127)}
S = 0
E = (01111100)_{2} = (124).
So E – 127 =  3
1.M = 1.11011010…0
= 2^{0} + 2^{(1)} + 2^{(1)} + 2^{(4)} + 2^{(5)} + 2^{(7)}
= 1+0.5+0.25+0.06+0.03+0.007
≈ 1.847
(1)^{5} × 1.M × 2^{(E127)}
= 1^{0} × 1.847 × 2^{3}
≈ 0.231
≈ 2.3 × 10^{1}
Question 17 
Consider a quadratic equation x^{2}  13x + 36 = 0 with coefficients in a base b. The solutions of this equation in the same base b are x = 5 and x = 6. Then b=________.
8  
9  
10  
11 
Generally if a, b are roots.
(x  a)(x  b) = 0
x^{2}  (a + b)x + ab = 0
Given that x=5, x=6 are roots of (1)
So, a + b = 13
ab=36 (with same base ‘b’)
i.e., (5)_{b} + (6)_{b} = (13)_{b}
Convert them into decimal value
5_{b} = 5_{10}
6_{10} = 6_{10}
13_{b} = b+3
11 = b+3
b = 8
Now check with ab = 36
5_{b} × 6_{b} = 36_{b}
Convert them into decimals
5_{b} × 6_{b} = (b×3) + 6_{10}
30 = b × 3 + 6
24 = b × 3
b = 8
∴ The required base = 8
Question 18 
If w, x, y, z are Boolean variables, then which one of the following is INCORRECT?
wx + w(x + y) + x(x + y) = x + wy  
(w + y)(wxy + wyz) = wxy + wyz 
wx + w(x + y) + x(x + y)
= (wx + wx) + wy + (x + xy)
= wx + wy + x(1 + y)
= wx + wy + x
= (w + 1)x + wy
= x + wy
OptionB:
OptionC:
OptionD:
(w + y)(wxy + wyz) = wxy + wyz + wxy + wyz = wxy + wyz
Question 19 
Given f(w,x,y,z) = Σ_{m}(0,1,2,3,7,8,10) + Σ_{d}(5,6,11,15), where d represents the don’tcare condition in Karnaugh maps. Which of the following is a minimum productofsums (POS) form of f(w,x,y,z)?
KMap for the function f is
Consider maxterms in Kmap to represent function in productofsums (POS) form
f(w,x,y,z) = (w' + z')(x' + z)
Question 20 
Consider a binary code that consists of only four valid code words as given below:
Let the minimum Hamming distance of the code be p and the maximum number of erroneous bits that can be corrected by the code be q. Then the values of p and q are
p=3 and q=1  
p=3 and q=2  
p=4 and q=1  
p=4 and q=2 
Minimum Distance = p = 3
Error bits that can be corrected = (p1)/2 = (31)/2 = 1
∴ p=3 and q=1
Question 21 
The next state table of a 2bit saturating upcounter is given below.
The counter is built as a synchronous sequential circuit using T flipflops. The expressions for T_{1} and T_{0} are
By using above excitation table,
Question 22 
Consider the Boolean operator with the following properties:
Then x#y is equivalent to
ExOR satisfies all the properties. Hence,
Question 23 
The 16bit 2’s complement representation of an integer is 1111 1111 1111 0101; its decimal representation is __________.
11  
12  
13  
14 
It is a negative number because MSB is 1.
Magnitude of 1111 1111 1111 0101 is 2’s complement of 1111 1111 1111 0101.
1111 1111 1111 0101
0000 0000 0000 1010 : 1’s Complement
0000 0000 0000 1011 : 2’s complement
= (11)_{10}
Hence, 1111 1111 1111 0101 = 11
Question 24 
We want to design a synchronous counter that counts the sequence 010203 and then repeats. The minimum number of JK ﬂipﬂops required to implement this counter is __________.
4  
5  
6  
7 
There are 3 transitions from 0.
Hence ⌈log_{2}^{3}⌉ = 2 bits have to be added to the existing 2 bits to represent 4 unique states.
Question 25 
Consider the two cascaded 2to1 multiplexers as shown in the ﬁgure.
The minimal sum of products form of the output X is
Now
Question 26 
Consider a carry lookahead adder for adding two nbit integers, built using gates of fanin at most two. The time to perform addition using this adder is __________.
Θ(1)  
Θ(log(n))  
Θ(√n)  
Θ(n) 
Where n is number of bits added
and k is fanin of the gates.
As we are adding nbit numbers and fanin is at most 2,
the solution is θ(log_{2} (n)).
Question 27 
Consider an eightbit ripplecarry adder for computing the sum of A and B, where A and B are integers represented in 2’s complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is _________.
1  
2  
3  
4 
If we do 2's complement of 1 = 0000 0001, we get 1 = "1111 1111"
So, if B = 1, every carry bit is 1.
Question 28 
Let, x_{1}⊕x_{2}⊕x_{3}⊕x_{4} = 0 where x_{1}, x_{2}, x_{3}, x_{4} are Boolean variables, and ⊕ is the XOR operator. Which one of the following must always be TRUE?
x_{1}x_{2}x_{3}x_{4} = 0  
x_{1}x_{3}+x_{2} = 0  
x_{1} + x_{2} + x_{3} + x_{4} = 0 
x_{1} ⊕ x_{2} ⊕ x_{3} ⊕ x_{4} = 0 (1)
A) x_{1}x_{2}x_{3} x_{4} = 0
Put x_{1} = 1, x_{2} = 1, x_{3} = 1, x_{4} = 1
The given equation will be zero, i.e.,
1 ⊕ 1 ⊕ 1 ⊕ 1 = 0
But,
x_{1}x_{2}x_{3} x_{4} ≠ 0
So, false.
B) x_{1}x_{3} + x_{2} = 0
Put x_{1} = 1, x_{2} = 1, x_{3} = 0 , x_{4} = 0
The given equation will be zero, i.e.,
1 ⊕ 1 ⊕ 0 ⊕ 0 = 0
But,
x_{1}x_{3} + x_{2} ≠ 0
So, false.
D) x_{1} + x_{2} + x_{3} + x_{4} = 0
Let x_{1}=1, x_{2}=1, x_{3}=0, x_{4}=0
The given equation will be zero, i.e.,
1 ⊕ 1 ⊕ 0 ⊕ 0 = 0
But,
x_{1} + x_{2} + x_{3} + x_{4} ≠ 0
So, false.
(i) True.
Question 29 
Let X be the number of distinct 16bit integers in 2’s complement representation. Let Y be the number of distinct 16bit integers in sign magnitude representation.
Then XY is _________.
1  
2  
3  
4 
Since range is  2^{15} to 2^{15}  1
Y = 2^{16}  1
Here, +0 and 0 are represented separately.
X  Y = 2^{16}  (2^{16}  1)
= 1
Question 30 
Consider a 4bit Johnson counter with an initial value of 0000. The counting sequence of this counter is
0, 1, 3, 7, 15, 14, 12, 8, 0  
0, 1, 3, 5, 7, 9, 11, 13, 15, 0  
0, 2, 4, 6, 8, 10, 12, 14, 0  
0, 8, 12, 14, 15, 7, 3, 1, 0 
The state sequence is 0,8,12,14,15,7,3,1,0.
Question 31 
The binary operator ≠ is defined by the following truth table
Which one of the following is true about the binary operator ≠?
Both commutative and associative  
Commutative but not associative  
Not commutative but associative  
Neither commutative nor associative 
Question 32 
A positive edgetriggered D flipflop is connected to a positive edgetriggered JK flipflop as follows. The Q output of the D flipflop is connected to both the J and K inputs of the JK flipflop, while the Q output of the JK flipflop is connected to the input of the D flipflop. Initially, the output of the D flipflop is set to logic one and the output of the JK flipflop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flipflop when the flipflops are connected to a freerunning common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the stateholding mode of the JK flipflop. Both the flipflops have nonzero propagation delays.
0110110...  
0100100...  
011101110...  
011001100... 
The characteristic equations are
Q_{DN}=D=Q_{JK}
The state table and state transition diagram are as follows:
Consider Q_{D}Q_{JK}=10 as initial state because in the options Q_{JK}=0 is the initial state of JK flipflop.
The state sequence is
0 → 1 → 1 → 0 → 1 → 1
∴ Option (a) is the answer.
Question 33 
The minimum number of JK flipflops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0,……) is ___________.
2  
3  
4  
5 
00
00
01
01
10
10
11
11
In the above sequence two flipflop's will not be sufficient. Since we are confronted with repeated sequence, we may add another bit to the above sequence.
000
100
001
101
010
110
011
111
Now and every count is unique, occurring only once.
So finally 3flip flops is required.
Question 34 
The number of minterms after minimizing the following Boolean expression is ______.
[D′ + AB′ + A′C + AC′D + A′C′D]′
1  
2  
3  
4 
[D' + AB' + A'C + AC'D + A'C'D]'
[D' + AB' + A'C + C'D (A + A')']' (since A+A' = 1)
[AB' + A'C + (D' + C') (D' + D)]' (since D' + D =1)
[AB' + A'C + D' + C']'
[AB' + (A' + C') (C + C') + D']'
[AB' + A' + C' + D']'
[(A + A') (A' + B') + C' + D']'
[A' + B' + C' + D']'
Apply demorgan's law,
ABCD
Question 35 
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4bit ripplecarry binary adder is implemented by using four full adders. The total propagation time of this 4bit binary adder in microseconds is ____________.
19.1  
19.2  
18.1  
18.2 
Here, each Full Adder is taking 4.8 microseconds. Given adder is a 4 Bit Ripple Carry Adder. So it takes 4*4.8 = 19.2 microseconds.
Question 36 
The total number of prime implicants of the function f(w,x,y,z) = Σ(0, 2, 4, 5, 6, 10) is ______.
3  
4  
2  
1 
Total 3 prime implicants are there.
Question 37 
Consider the following Boolean expression for F:
F(P, Q, R, S) = PQ + P'QR + P'QR'S
The minimal sumofproducts form of F is
= Q(P+P’R) + P’QR’S
= Q(P+R) + P’QR’S
= QP + QR + P’QR’S
= QP + Q(R + P’R’S)
= QP + Q( R + P’S)
= QP + QR + QP’S
= Q(P+P’S) + QR
= Q(P+S)+ QR
= QP + QS + QR
Question 38 
The base (or radix) of the number system such that the following equation holds is_________.
312/20 = 13.1
5  
6  
7  
8 
(3r^{2} + r + 2) / 2r= (r+3+1/r)
(3r^{2} + r + 2) / 2r= (r^{2}+3r+1) / r
(3r^{2} + r + 2) = (2r^{2}+6r+2)
r^{2} 5r = 0
Therefor r = 5
Question 39 
Consider a 4to1 multiplexer with two select lines S1 and S0, given below
The minimal sumofproducts form of the Boolean expression for the output F of the multiplexer is
= P’Q + PQ’R + PQR’
= Q(P’ + P R’) + PQ’R
= Q(P’ + R’) + PQ’R
= P’Q + QR’ + PQ’R
Question 40 
The dual of a Boolean function F(x_{1}, x_{2}, ..., x_{n}, +, ⋅, '), written as F^{D}, is the same expression as that of F with + and ⋅ swapped. F is said to be selfdual if F = F^{D}. The number of selfdual functions with n Boolean variables is
2^{n}  
2^{(n1)}  
2^{(2n )}  
2^{(2(n1) )} 
Number of mutually exclusive pairs of minterms = 2^{n1}.
There are 2 choices for each pair i.e., we can choose one of the two minterms from each pair of minterms for the function.
Therefore number of functions = 2 x 2 x …. 2^{n1} times.
= 2^{(2(n1)) }
Question 41 
Let k = 2^{n}. A circuit is built by giving the output of an nbit binary counter as input to an nto2^{n} bit decoder. This circuit is equivalent to a
kbit binary up counter.  
kbit binary down counter.  
kbit ring counter.  
kbit Johnson counter. 
A n x 2^{n} decoder is a combinational circuit with only one output line has one and all others (2^{n}1) have zeros.
A nbit binary Counter produces outputs from 0 to 2^{n} i.e 000...00 to 111...11 and repeats.
The n x 2^{n} Decoder gets the input (000..00 to 111...11 ) from the binary counter and only one output line has one and rest have zeros.
This circuit is equivalent to a 2^{n}  bit ring counter.
Question 42 
Consider the equation (123)_{5} = (x8)_{y} with x and y as unknown. The number of possible solutions is __________.
3  
5  
6  
7 
(123)_{5} = (x8)_{y}
In R.H.S. since y is base so y should be greater than x and 8, i.e.,
y > x
y > 8
Now, to solve let's change all the above bases number into base 10 number,
5^{2} × 1 +2 × 5 + 3 = y × x + 8
38 = xy + 8
xy = 30
⇒ yx = 30
So the possible combinations are
(1,30), (2,15), (3,10), (5,6)
But we will reject (5,6) because it violates the condition (y > 8).
So, total solutions possible is 3.
Question 43 
Consider the following minterm expression for F:
F(P,Q,R,S) = Σ0,2,5,7,8,10,13,15
The minterms 2, 7, 8 and 13 are 'do not care' terms. The minimal sumofproducts form for F is:
Question 44 
Consider the following combinational function block involving four Boolean variables x, y, a, b where x, a, b are inputs and y is the output.
f (x, y, a, b) { if (x is 1) y = a; else y = b; }
Which one of the following digital logic blocks is the most suitable for implementing this function?
Full adder  
Priority encoder  
Multiplexor  
Flipflop 
x is the select line, I_{0} is 'b' and I_{1} is a.
The output line, y = xa + x’b
Question 45 
The above synchronous sequential circuit built using JK flipflops is initialized with Q2Q1Q0 = 000. The state sequence for this circuit for the next 3 clock cycles is
001, 010, 011  
111, 110, 101  
100, 110, 111  
100, 011, 001 
Question 46 
Let ⊕ denote the Exclusive OR (XOR) operation. Let ‘1’ and ‘0’ denote the binary constants. Consider the following Boolean expression for F over two variables P and Q:
F(P,Q) = ((1⊕P)⊕(P⊕Q))⊕((P⊕Q)⊕(Q⊕0))
The equivalent expression for F is
P+Q  
P⨁Q  
⊕ is associative i.e P ⊕ (Q ⊕ R) = (P⊕Q) ⊕ R.
P ⊕ P = 0, 1 ⊕ P = P’ and 0 ⊕ Q = Q
(1 ⊕ P) ⊕ ((P ⊕ Q) ⊕ (P ⊕ Q)) ⊕ (Q ⊕ 0)
= P’⊕ (0) ⊕ Q
= P’ ⊕ Q
= (P ⊕ Q)’
Question 47 
The smallest integer that can be represented by an 8bit number in 2’s complement form is
256  
128  
127  
0 
The smallest 8bit 2’s complement number is 1000 0000.
MSB is 1. So it is a negative number.
To know the magnitude again take 2’s complement of 1000 0000.
1000 0000
0111 1111 ← 1’s complement
1000 0000 ← 2’s complement (1’s complement +1)
= 128
128 is 1000 0000 in 2’s complement representation.
Question 48 
In the following truth table, V = 1 if and only if the input is valid.
What function does the truth table represent?
Priority encoder  
Decoder  
Multiplexer  
Demultiplexer 
Question 49 
Which one of the following expressions does NOT represent exclusive NOR of x and y?
xy+x'y'  
x⊕y'  
x'⊕y  
x'⊕y' 
x’ ⊕ y’ = xy’ + x’y = x⊕y. Hence option D is correct.
Question 50 
The truth table
represents the Boolean function
X  
X + Y  
X ⊕ Y  
Y 
Question 51 
The decimal value 0.5 in IEEE single precision floating point representation has
fraction bits of 000…000 and exponent value of 0  
fraction bits of 000…000 and exponent value of −1  
fraction bits of 100…000 and exponent value of 0  
no exact representation 
So, value of the exponent = 1
and
fraction is 000…000 (Implicit representation)
Question 52 
The amount of ROM needed to implement a 4 bit multiplier is
64 bits  
128 bits  
1 Kbits  
2 Kbits 
Hence option D is the answer.
Question 53 
What is the minimal form of the karnaugh map shown below? Assume that X denotes a don't care term
Question 54 
The simplified SOP (sum of product) form of the boolean expression
Question 55 
The minimum number of D flipflops needed to design a mod258 counter is
9  
8  
512  
258 
The max Mod values is 2n.
So 2^{n} ≥ 258 ⇒ n = 9
Question 56 
Which one of the following circuits is NOT equivalent to a 2input XNOR (exclusive NOR) gate?
Question 57 
Consider the following circuit involving three Dtype flipflops used in a certain type of counter configuration.
If all the flipflops were reset to O at power on, what is the total number of distinct outputs *states) represented by PQR generated by the counter?
3  
4  
5  
6 
So total no. of distinct output (states) are 4.
Question 58 
Consider the following circuit involving three Dtype flipflops used in a certain type of counter configuration.
If at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?
000  
001  
010  
011 
So, after 010 it moves to 011.
Question 59 
The minterm expansion of is
m_{2}+m_{4}+m_{6}+m_{7}  
m_{0}+m_{1}+m_{3}+m_{5}  
m_{0}+m_{1}+m_{6}+m_{7}  
m_{2}+m_{3}+m_{4}+m_{5} 
= PQR + PQR' + PQR' + P'QR' + PQR' + PQ'R'
= PQR + PQR' + P'QR' + PQ'R'
= m_{7} + m_{6} + m_{2} + m_{4}
Question 60 
A main memory unit with a capacity of 4 megabytes is built using 1M 1bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is
100 nanoseconds  
100*2^{10} nanoseconds  
100*2^{20} nanoseconds  
3200*2^{20} nanoseconds 
Required capacity = 4MB
Number of chips needed = 4M*8 bits / 1M x 1bit = 32 (1M x 1bit)/(1M x 1bit) = 32
Irrespective of the number of chips, all chips can be refreshed in parallel.
And all the cells in a row are refreshed in parallel too. So, the total time for refresh will be number of rows times the refresh time of one row.
Here we have 1K rows in a chip and refresh time of single row is 100ns.
So total time required = 1K × 100
= 100 × 2^{10} nanoseconds
Question 61 
P is a 16bit signed integer. The 2's complement representation of P is (F87B)_{16}. The 2's complement representation of 8*P is
(C3D8)_{16}  
(187B)_{16}  
(F878)_{16}  
(987B)_{16} 
(F87B)_{16}=(1111 1000 0111 1011)_{2}. (It is a negative number which is in 2's complement form)
P = 1111 1000 0111 1011 (2's complement form)
8 * P = 2^{3}* P = 1100 0011 1101 1000. ( NOTE: Left shift k times is equivalent to Multiplication by 2^{k})
Hence, 1100 0011 1101 1000 is 2's complement representation of 8P.
1100 0011 1101 1000 = (C3D8)_{16}.
Question 62 
The Boolean expression for the output 'f' of the multiplexer shown below is
P⊕Q⊕R  
P+Q+R  
= (P’Q’ + PQ)R + (P’Q+PQ’)R’
= (P⊕Q)’R + (P⊕Q)R’
= (P⊕Q⊕R)
Question 63 
What is the Boolean expression for the output f of the combinational logic circuit of NOR gates given below?
= (P’Q’ + Q’R’)( P’R’ + Q’R’)
= (P’Q’P’R’ + P’Q’Q’R’ + Q’R’P’R’ + Q’R’Q’R’)
= (P’Q’R’ + P’Q’R’ + P’Q’R’ + Q’R’)
= (P’Q’R’ + Q’R’)
= (Q’R’)
= (Q+R)’
Question 64 
In the sequential circuit shown below,if the initial value of the output Q_{1}Q_{0} is 00,what are the next four values of Q_{1}Q_{0}?
11, 10, 01, 00  
10, 11, 01, 00  
10, 00, 01, 11  
11, 10, 00, 01 
The next four values of Q_{1}Q_{0} are 11, 10, 01, 00.
Question 65 
(1217)_{8} is equivalent to
(1217)_{16}
 
(028F)_{16}  
(2297)_{10}  
(0B17)_{16} 
Divide the bits into groups, each containing 4 bits.
= (0010 1000 1111)_{2}
= (28F)_{16}
Question 66 
What is the minimum number of gates required to implement the Boolean function (AB+C) if we have to use only 2input NOR gates?
2  
3  
4  
5 
AB+C
= (A+C)(B+C) ← Distribution of + over
= ((A+C)’+(B+C)’)’
1^{st} NOR (A+C)’. Let X = (A+C)’
2^{nd} NOR (B+C)’. Let Y = (B+C)’
3^{rd} NOR (X+Y)’
Question 67 
How many 32K × 1 RAM chips are needed to provide a memory capacity of 256Kbytes?
8  
32  
64  
128 
Needed memory capacity = 256K  bytes = 256K*8 bits
Number of chips needed = 256K*8 / 32K×1 = 64
Question 68 
In the IEEE floating point representation, the hexadecimal value 0×00000000 corresponds to
the normalized value 2^{  127}  
the normalized value 2^{  126}  
the normalized value + 0  
the special value + 0 
Question 69 
In the Karnaugh map shown below, X denotes a don’t care term. What is the minimal form of the function represented by the Karnaugh map?
Question 70 
Let r denote number system radix. The only value(s) of r that satisfy the equation is/are
decimal 10  
decimal 11  
decimal 10 and 11  
any value > 2 
(r^{2} + 2r + 1)^{1/2} = r + 1
(r + 1)^{2} * 1/2 = r + 1
r + 1 = r + 1 Any value of r will satisfy the above equation. But the radix should be greater than 2 because the 121 has 2. So r > 2 is correct.
Question 71 
If P, Q, R are Boolean variables, then
Simplifies to
Question 72 
What is the maximum number of different Boolean functions involving n Boolean variables?
n^{2}  
2^{n}  
2^{2n}  
2^{n2} 
Number of variables= n
Number of input combinations is 2^{n}.
Each “boolean” function has two possible outputs i.e 0 and 1.
Number of boolean functions possible is 2^{2n}.
Formula: The number of mary functions possible with n kary variables is m^{kn}.
Question 73 
How many 3to8 line decoders with an enable input are needed to construct a 6to64 line decoder without using any other logic gates?
7  
8  
9  
10 
So, we can say that
8 lines covered by  1 decoder
1 line covered by  1/8 decoder
64 lines covered by  64/8 = 8 decoders
8 lines covered by  8/8 = 1 decoder
Hence total no. of decoder needed is,
8 + 1 = 9 decoders.
Question 74 
Consider the following Boolean function of four variables:
f(w,x,y,z) = ∑(1,3,4,6,9,11,12,14)The function is:
independent of one variable.  
independent of two variables.  
independent of three variables.  
dependent on all the variables. 
w and y are not needed to represent the function f. So f is independent of two variables.
Question 75 
Let f(w, x, y, z) = ∑(0, 4, 5, 7, 8, 9, 13, 15). Which of the following expressions are NOT equivalent to f?
 (P) x'y'z' + w'xy' + wy'z + xz
(Q) w'y'z' + wx'y' + xz
(R) w'y'z' + wx'y' + xyz + xy'z
(S) x'y'z' + wx'y' + w'y
P only
 
Q and S  
R and S  
S only 
(P), (Q), (R) cover all the minterms and are equivalent to f(w,x,y,z) = Σ(0,4,5,7,8,9,13,15).
(S) covers the minterms m_{0}, m_{8}, m_{9}, m_{2}, m_{3}, m_{6}, m_{7}.
(S) is not covering the minterms m_{4}, m_{5}, m_{13}, m_{15}.
Question 76 
Define the connective * for the Boolean variables X and Y as: X * Y = XY + X'Y'. Let Z = X * Y.
Consider the following expressions P, Q and R.
P: X = Y⋆Z Q: Y = X⋆Z R: X⋆Y⋆Z = 1
Which of the following is TRUE?
Only P and Q are valid.  
Only Q and R are valid.
 
Only P and R are valid.  
All P, Q, R are valid. 
= Y(XY + X’Y’) + Y’(XY+X’Y’)’
= XY+Y’(X ⊕ Y)
= XY+Y’(XY’+X’Y)
= XY+XY’
= X(Y+Y’) = X
Q: X*Z = (XZ + X’Z’)
= X(XY + X’Y’) + X’(XY + X’Y’)’
= XY+X’(X’Y+XY’)
= XY+X’Y
= (X+X’)Y = Y
R: X* Y*Z
= X*X Since P: Y*Z= X
= XX + X’X’
= 1
Question 77 
Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed?
2^{n} line to 1 line  
2^{n+1} line to 1 line  
2^{n1} line to 1 line
 
2^{n2} line to 1 line 
A 2^{n} X 1 multiplexer can implement any function of n variables. As n variables are given to select lines, so that true and complement forms of all variables get generated inside the MUX.
As one inverter is available, we can generate complement of one variable outside of the Multiplexer. And remaining (n1) variables are given to select lines. With this we have true and complement form of all n variables.
So, the answer is 2^{n1} X 1 MUX.
Question 78 
In a lookahead carry generator, the carry generate function G_{i} and the carry propagate function P_{i} for inputs A_{i} and B_{i} are given by:
P_{i} = A_{i} ⨁ B_{i} and G_{i} = A_{i}B_{i}
The expressions for the sum bit S_{i} and the carry bit C_{i+1} of the lookahead carry adder are given by:
S_{i} = P_{i} ⨁ C_{i} and C_{i+1} = G_{i} + P_{i}C_{i} , where C_{0} is the input carry.
Consider a twolevel logic implementation of the lookahead carry generator. Assume that all P_{i} and G_{i} are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the lookahead carry generator for a 4bit adder with S3, S2, S1, S0 and C4 as its outputs are respectively:
6, 3  
10, 4  
6, 4  
10, 5 
Question 79 
The control signal functions of a 4bit binary counter are given below (where X is “don’t care”) The counter is connected as follows:
The counter is connected as follows:
Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through the following sequence:
0, 3, 4  
0, 3, 4, 5  
0, 1, 2, 3, 4  
0, 1, 2, 3, 4, 5 
Here, initial state is 0000. It goes through 0001,0010,0011,0100 and 0101. When the state is 5(0101) it immediately resets to initial state 0. Here, state 5 is not considered as valid state.
So valid states are 0,1,2,3, and 4 and hence it is a Mod5 counter.
Question 80 
Which of the following is TRUE about formulae in Conjunctive Normal Form?
For any formula, there is a truth assignment for which at least half the clauses evaluate to true.  
For any formula, there is a truth assignment for which all the clauses evaluate to true.
 
There is a formula such that for each truth assignment, at most onefourth of the clauses evaluate to true.
 
None of the above. 
Formula: a ∧ b
Truth table:
Conjunctive normal form : (a ∨ b) ∧ (a ∨ ~b) ∧ (~a ∨ b)
Similarly,
For n=1TRUE=1, FALSE=1 (1/2 ARE TRUE)
For n=2TRUE=3, FALSE=1 (3/4 ARE TRUE)
For n=3TRUE=7, FALSE=1 (7/8 ARE TRUE)
(12^{n}) are TRUE.
Looking at options,
Question 81 
You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flipflops) will delay the phase of f by 180°?
50% of duty cycle means, the wave is 1 for half of the time and 0 for the other half of the time. It is a usual digital signal with 1 and 0.
The waveform f changes for every negative edge, that means f value alters from 1 to 0 or 0 to 1 for every negative edge of the clock.
Now the problem is that we need to find the circuit which produces a phase shift of 180, which means the output is 0 when f is 1 and output is 1 when f is 0.
Like the below image.
Now to find the answer we can choose elimination method.
F changes for negative edge, so that output too should change at negative edge. i.e if f becomes 0, then at the same time output should become 1, vice versa.
So, whenever input changes, at the same point of time output too should change. As input changes on negative edge, the output should be changed at negative edge only.
To have the above behaviour, the second D flipflop which produces the final output should be negative edge triggered. because whatever the 2nd flipflop produces, that is the output of the complete circuit.
So, we can eliminate option a, d.
Now either b or c can be answer.
How the flipflop chain works in option b and c is as below.
—> F changes at negative edge.
—> But flipflop1 responds at next positive edge.
—> After this flipflop2 responds at next negative edge.
That means flipflop2 produces the same input which is given to flipflop now after a positive edge and a negative edge, that means a delay of one clock cycle, which is 180 degrees phase shift for the waveform of f.
Option b) we are giving f’, so that the output is f’ with 180 degrees phase shift.
Option c) we are giving f, so that the output is f with 180 degrees phase shift.
Hence option C is the answer.
Question 82 
Consider the circuit above. Which one of the following options correctly represents f(x,y,z)?
= xy + zy’ + y’z’x
= x(y+y’z’) + zy’
= x(y+z’) + y’z
= xy + xz’ + y’z
Question 83 
Given two three bit numbers a_{2}a_{1}a_{0} and b_{2}b_{1}b_{0} and c, the carry in, the function that represents the carry generate function when these two numbers are added is:
Carry c_{1} = a_{0}b_{0}
Carry c_{2} = a_{2}b_{2} + c_{1}(a_{2} ⊕ b_{2} )
= a_{1}b_{1} +c_{1} (a_{1} b’_{1}+ a’_{1} b_{1} )
= a_{1}b_{1} +c_{1} a_{1} b’_{1}+ c_{1} a’_{1} b_{1}
= (a_{1}b_{1} + c_{1}a_{1} b’_{1})+ (c_{1} a’_{1} b_{1} + a_{1}b_{1} )
= a_{1}(b_{1}+c_{1}) +b_{1} (c_{1} + a_{1})
= a_{1}b_{1}+b_{1}c_{1}+a_{1}c_{1}
Carry c_{3} = a_{2}b_{2} + c_{2}(a_{2} ⊕ b_{2})
= a_{2}b_{2} + c_{2}(a’_{2}b_{2} + a_{2}b’_{2} )
= a_{2}b_{2} + b_{2}c_{2} + a_{2}c_{2}
= a_{2}b_{2}+a_{2}a_{1}b_{1}+a_{2}a_{1}a_{0}b_{0}+a_{2}a_{0}b_{1}b_{0}+a_{1}b_{2}b_{1}+a_{1}a_{0}b_{2}b_{0}+a_{0}b_{2}b_{1}b_{0}
Question 84 
Consider the circuit in the diagram. The ⊕ operator represents ExOR. The D flipflops are initialized to zeroes (cleared).
The following data: 100110000 is supplied to the “data” terminal in nine clock cycles. After that the values of q2q1q0 are:
000  
001  
010  
101 
Question 85 
Consider a Boolean function f(w,x,y,z). Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors i_{1} = 〈w_{1}, x_{1}, y_{1}, z_{1}〉 and i_{2} = 〈w_{2}, x_{2}, y_{2}, z_{2}〉, we would like the function to remain true as the input changes from vectors i_{1} to i_{2} (i_{1} and i_{2} differ in exactly one bit position), without becoming false momentarily. Let f(w,x,y,z) = ∑(5,7,11,12,13,15). Which of the following cube covers of f will ensure that the required property is satisfied?
f = X_{1} * X_{2} + X_{1}' * X_{3}
If (X_{1}, X_{2}, X_{3}) = (1,1,1) then f=1 because X_{1} * X_{2} =1 X_{1}' * X_{3} = 0.
Let the input is changed from 111 to 011 , then f = 1 because X_{1} * X_{2} = 0 X_{1}' * X_{3} =1.
The output f will be momentarily 0 if AND gate X_{1} * X_{2} is faster than the AND gate X_{1}' * X_{}3.
This Hazard can be avoided by adding the term X_{2} * X_{3} (because X_{1} is in true form in first term and in complement form in the second term . So pick the fixed terms X_{2} and X_{3} from both terms) to f i.e f = X_{1} * X_{2} + X_{1}' * X_{3} + X_{2} * X_{3}
Option D is equivalent to f(w, x, y, z) = ∑(5,7,11,12,13,15)
Question 86 
We consider the addition of two 2’s complement numbers b_{n1}b_{n2}...b_{0} and a_{n1}a_{n2}…a_{0}. A binary adder for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by c_{n1}c_{n2}c_{0} and the carryout by c_{out}. Which one of the following options correctly identifies the overflow condition?
1. The sign bits are same i.e MSB bits are same.
2. Carry_in ≠ Carry_out.
In option B, the MSB are equal.
Question 87 
Consider numbers represented in 4bit gray code. Let h_{3}h_{2}h_{1}h_{0} be the gray code representation of a number n and let g_{3}g_{2}g_{1}g_{0} be the gray code of (n+1)(modulo 16) value of the number. Which one of the following functions is correct?
g_{0}(h_{3}h_{2}h_{1}h_{0}) = Σ(1,2,3,6,10,13,14,15)  
g_{1}(h_{3}h_{2}h_{1}h_{0}) = Σ(4,9,10,11,12,13,14,15)  
g_{2}(h_{3}h_{2}h_{1}h_{0}) = Σ(2,4,5,6,7,12,13,15)  
g_{3}(h_{3}h_{2}h_{1}h_{0}) = Σ(0,1,6,7,10,11,12,13)

g_{2}(h_{3}h_{2}h_{1}h_{0}) = Σ(2,4,5,6,7,12,13,15)
Question 88 
Consider the following circuit.
Which one of the following is TRUE?
f is independent of X
 
f is independent of Y  
f is independent of Z  
None of X, Y, Z is redundant 
= ((X’+Y) YZ)’
= (X’YZ + YZ)’
= ((X’+1) YZ)’
= (YZ)’
Question 89 
The range of integers that can be represented by an n bit 2's complement number system is:
 2^{n1} to (2^{n1}  1)  
 (2^{n1}  1) to (2^{n1}  1)  
 2^{n1} to 2^{n1}
 
 (2^{n1} + 1) to (2^{n1}  1) 
The smallest (negative) n bit number is 100..0 (i.e., 1 followed by n1 zeros) which is equal to  2^{n1}.
1000...00
0111...11 < 1’s complement
1000..00 < 2’s complement
=  2^{n1}
Question 90 
The hexadecimal representation of 657_{8} is
1AF  
D78  
D71  
32F 
Make 3 zeros on the left side so that the number of bits is multiple of 4.
= (0001 1010 1111)_{2}
= (1 A F)_{16}
Question 91 
The switching expression corresponding to f(A, B, C, D) = Σ (1, 4, 5, 9, 11, 12) is:
BC'D' + A'C'D + AB'D  
ABC' + ACD + B'C'D  
ACD' + A'BC' + AC'D'  
A'BD + ACD' + BCD' 
f(A,B,C,D) = A'C'D + BC'D' + AB'D
Question 92 
Consider the following circuit involving a positive edge triggered D FF.
Consider the following timing diagram. Let A_{i} represent the logic level on the line A in the ith clock period.
Let A' represent the complement of A. The correct output sequence on Y over the clock periods 1 through 5 is
A_{0} A_{1} A_{1}' A_{3} A_{4}  
A_{0} A_{1} A_{2}' A_{3} A_{4}  
A_{1} A_{2} A_{2}' A_{3} A_{4}  
A_{1} A_{2}' A_{3} A_{4} A_{5}' 
Input will be accepted by the flipflop after the cycle gets finished, because +ve edge is occurring at the end of the clock cycle only.
Question 93 
Consider the following circuit.
The flipflops are positive edge triggered D FFs. Each state is designated as a two bit string Q_{0}Q_{1}. Let the initial state be 00. The state transition sequence is:
Question 94 
Consider the following floating point format.
Mantissa is a pure fraction in signmagnitude form.
The decimal number 0.239 × 2^{13} has the following hexadecimal representation (without normalization and rounding off:
0D 24  
0D 4D  
4D 0D  
4D 3D 
Convert 0.239 to binary
0.239 * 2 = 0.478
0.478 * 2 = 0.956
0.956 * 2 = 1.912
0.912 * 2 = 1.824
0.824 * 2 = 1.648
0.648 * 2 = 1.296
0.296 * 2 = 0.512
0.512 * 2 = 1.024
Mantissa = (0. 00111101)_{2}
Bias = 64. So biased exponent is 13+64 = 77= (1001101)_{2}
0.239 × 2^{13} = 0 1001101 00111101
= 0100 1101 0011 1101
= 4 D 3 D
Question 95 
Consider the following floating point format.
Mantissa is a pure fraction in signmagnitude form.
The normalized representation for the above format is specified as follows. The mantissa has an implicit 1 preceding the binary (radix) point. Assume that only 0's are padded in while shifting a field. The normalized representation of the above number (0.239 × 2^{13}) is
0A 20  
11 34  
4D D0
 
4A E8 
Convert 0.239 to binary
0.239 * 2 = 0.478
0.478 * 2 = 0.956
0.956 * 2 = 1.912
0.912 * 2 = 1.824
0.824 * 2 = 1.648
0.648 * 2 = 1.296
0.296 * 2 = 0.512
0.512 * 2 = 1.024
Mantissa = (0. 00111101)_{2}
0.239 × 2^{13} = 1.11101000 x 2^{10} < Normalized Mantissa
Bias = 64. So biased exponent is 10+64 = 74 = (1001010)_{2}
0.239 × 2^{13} = 0 1001010 11101000
= 0100 1010 1110 1000
= (4 A E 8)_{16}
Question 96 
The Boolean function x'y' + xy + x'y is equivalent to
x' + y'  
x + y  
x + y'  
x' + y 
= x'y' + x'y + xy
= x'(y'+y)+xy
= x'⋅1+xy
= x'+xy
= (x'+x)(x'+y)
= 1⋅(x'+y)
= x'+y
Question 97 
In an SR latch made by crosscoupling two NAND gates, if both S and R inputs are set to 0, then it will result in
Q = 0, Q' = 1  
Q = 1, Q' = 0  
Q = 1, Q' = 1  
Indeterminate states 
Truth table for the SR latch by cross coupling two NAND gates is
So, Answer is Option (D).
Question 98 
If 73_{x} (in basex number system) is equal to 54_{y} (in basey number system), the possible values of x and y are
8, 16  
10, 12  
9, 13  
8, 11 
7x+3 = 5y+4
7x5y = 1
Only option (D) satisfies above equation.
Question 99 
What is the result of evaluating the following two expressions using threedigit floating point arithmetic with rounding?
(113. + 111.) + 7.51 113. + (111. + 7.51)
9.51 and 10.0 respectively
 
10.0 and 9.51 respectively
 
9.51 and 9.51 respectively  
10.0 and 10.0 respectively 
= (2) + 7.51
= 9.51 (✔️)
113. + (111. + 7.51)
= 113. + (103.51)
= 113. + 103
= 10 (✔️)
Question 100 
A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001, ..., 9 by 1001. A combinational circuit is to be designed which takes these 4 bits as input and outputs 1 if the digit ≥ 5, and 0 otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required?
2  
3  
4  
5 
= A + BD + BC
= A + B (D + C)
So minimum two OR gates and 1 AND gate is required. Hence, in total minimum 3 gates is required.
Question 101 
Which are the essential prime implicants of the following Boolean function?
f(a,b,c) = a^{ȼ}c + ac^{ȼ} + b^{ȼ}c
a^{ȼ}c and ac^{ȼ}  
a^{ȼ}c and b^{ȼ}c  
a^{ȼ}c only  
ac^{ȼ} and bc^{ȼ} 
There are two EPI,
A'C and AC'.
Question 102 
Consider a multiplexer with X and Y as data inputs and Z as control input. Z = 0 selects input X, and Z = 1 selects input Y. What are the connections required to realize the 2variable Boolean function f = T + R, without using any additional hardware?
R to X, 1 to Y, T to Z  
T to X, R to Y, T to Z  
T to X, R to Y, 0 to Z  
R to X, 0 to Y, T to Z 
f = z'x + zy
Put z=T, x=R, y=1 in f
f = T'R + T = (T+T') (R+T) = T+R
Hence, correct option is (A).
Question 103 
Consider the partial implementation of a 2bit counter using T flipflops following the sequence 02310, as shown below
To complete the circuit, the input X should be
Q_{2}^{c}  
Q_{2} + Q_{1}  
(Q_{1} + Q_{2})^{c}  
Q_{1} ⊕ Q_{2} 
0  2  3  1  0
or
00  10  11  01  00
From the given sequence, we have state table as,
Now we have present state and next state, so we should use excitation table of T flipflop,
From state table,
T_{2} = Q_{2}⊙Q_{1} and T_{1} = Q_{2}⊕Q_{1}
X = T_{1} = Q_{2}⊕Q_{1}
Question 104 
A 4bit carry lookahead adder, which adds two 4bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using twolevel ANDOR logic.
4 time units  
6 time units  
10 time units  
12 time units 
1) (2 time units) In 2 time units we can compute G_{i} and P_{i} in parallel, 2 time units for P_{i} since its an XOR operation and 1 time unit for G_{i} since its an AND operation.
2) (2 time units) Once G_{i} and P_{i} are available, we can calculate the carries, C_{i}, in 2 time units.
Level1 we can compute all the conjunctions (AND).
Example: P_{3}G_{2}, P_{3}P_{2}G_{1}, P_{3}P_{2}P_{1}G_{0} and P_{3}P_{2}P_{1}P_{0}C_{0} which are required for C_{4}.
Level2 we get the carries by computing the disjunction (OR).
3) (2 time units) Finally, we compute the sum in 2 time units, as its a XOR operation.
Hence, the total is 2+2+2 = 6 time units.
Question 105 
Let A = 1111 1010 and B = 0000 1010 be two 8bit 2's complement numbers. Their product in 2's complement is
1100 0100
 
1001 1100
 
1010 0101
 
1101 0101 
B = 0000 1010 = 10_{10} [2's complement number]
A×B = 6×10 =  60_{10}
⇒ 60_{10} = 10111100_{2}
= 11000011_{2} (1's complement)
= 11000100_{2} (2's complement)
Question 106 
Assuming all numbers are in 2's complement representation, which of the following numbers is divisible by 11111011?
11100111  
11100100  
11010111  
11011011 
MSB bit is '1' then all numbers are negative
1's complement = 00000100
2's complement = 00000100 + 00000001 = 00000101 = 5
(A) 11100111  (25)_{10}
(B) 11100100  (28)_{10 (C) 11010111  (41)10 (D) 11011011  (37)10 Answer: Option A (25 is divisible by 5)}
Question 107 
Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is
Θ (1)  
Θ (log n)  
Θ (n)  
Θ (n^{2}) 
The total time is n+knk = Θ(n)
Question 108 
The following is a scheme for floating point number representation using 16 bits.
Let s, e, and m be the numbers represented in binary in the sign, exponent, and mantissa fields respectively. Then the floating point number represented is:
What is the maximum difference between two successive real numbers representable in this system?
2^{40}  
2^{9}  
2^{22}  
2^{31} 
The largest number is 1.111111111× 2^{6231} = (2−2^{−9})×2^{31}
Second largest number is 1.111111110×2^{6231} = (2−2^{8})×2^{31}
Difference = (2−2^{−9})×2^{31}  (2−2^{8})×2^{31}
= (2^{8}−2^{−9}) ×2^{31}
= 2^{−9}×2^{31}
= 2^{22}
Question 109 
A 1input, 2output synchronous sequential circuit behaves as follows:
Let z_{k}, n_{k} denote the number of 0's and 1's respectively in initial k bits of the input (z_{k} + n_{k} = k). The circuit outputs 00 until one of the following conditions holds.
• z_{k}  n_{k} = 2. In this case, the output at the kth and all subsequent clock ticks is 10. • n_{k}  z_{k} = 2. In this case, the output at the kth and all subsequent clock ticks is 01.
What is the minimum number of states required in the state transition graph of the above circuit?
5  
6  
7  
8 
q_{0} ← Number of zeros is one more than number of ones.
q_{1} ← Number of ones is one more than number of zeros.
q_{00} ← Number of zeros is two more than number of ones.
q_{11} ← Number of ones is two more than number of zeros.
Question 110 
The literal count of a boolean expression is the sum of the number of times each literal appears in the expression. For example, the literal count of (xy + xz') is 4. What are the minimum possible literal counts of the productofsum and sumofproduct representations respectively of the function given by the following Karnaugh map ? Here, X denotes "don't care"
(11, 9)  
(9, 13)  
(9, 10)  
(11, 11) 
⇒ w'y' + z'wx' + xyz'
Total 8 literals are there.
For POS,
⇒ (z' + w')(z' + y')(w' + x')(x + z + w)
Total 9 literals are there.
Question 111 
Consider the ALU shown below.
If the operands are in 2's complement representation, which of the following operations can be performed by suitably setting the control lines K and C_{0} only (+ and  denote addition and subtraction respectively)?
A + B, and A – B, but not A + 1  
A + B, and A + 1, but not A – B  
A + B, but not A – B or A + 1  
A + B, and A – B, and A + 1

1) A+B when K=0 and C_{0} = 0. It is binary adder which performs addition of two binary numbers.
2) A  B = A+ B' + 1 when K=1 and C_{0} = 1 ;
Here XOR gates produce B' if K=1. Since 1⊕b= b'.
"1" in (A+B+1) is coming from C_{0}.
Note: 2's complement of B is (B'+1). 3) A+1 when B=0, K=0, C_{0}= 1.
Increments A.
Question 112 
Consider the following circuit composed of XOR gates and noninverting buffers.
The noninverting buffers have delays δ_{1} = 2 ns and δ_{2} = 4 ns as shown in the figure. Both XOR gates and all wires have zero delay. Assume that all gate inputs, outputs and wires are stable at logic level 0 at time 0. If the following waveform is applied at input A, how many transition(s) (change of logic levels) occur(s) at B during the interval from 0 to 10 ns?
1  
2  
3  
4 
⇒ a will always be equal to A.
Question 113 
Minimum sum of product expression for f(w,x,y,z) shown in Karnaughmap below is
xz+y'z  
xz'+zx'  
x'y+zx'  
None of the above 
⇒ xz' + zx'
Question 114 
The decimal value 0.25
is equivalent to the binary value 0.1  
is equivalent to the binary value 0.01  
is equivalent to the binary value 0.00111…  
cannot be represented precisely in binary 
Multiply 0.25 by 2.
0.25×2 = 0.50 (product)
Fractional part = 0.50
Carry = 0
2^{nd} Multiplication iteration:
Multiply 0.50 by 2.
0.50×2 = 1.00 (product)
Fractional part = 0.00
Carry = 1
The fractional part in the 2^{nd} iteration becomes zero and so we stop the multiplication iteration.
Carry from 1^{st} multiplication iteration becomes MSB and carry from 2^{nd} iteration becomes LSB. So the result is 0.01.
Question 115 
The 2’s complement representation of the decimal value 15 is
1111  
11111  
111111  
10001 
15 = 11111
1's complement = 10000
2's complement = 10001
Question 116 
Sign extension is a step in
floating point multiplication  
signed 16 bit integer addition  
arithmetic left shift  
converting a signed integer from one size to another 
Question 117 
In 2’s complement addition, overflow
is flagged whenever there is carry from sign bit addition  
cannot occur when a positive value is added to a negative value  
is flagged when the carries from sign bit and previous bit match  
None of the above 
Question 118 
Consider the following logic circuit whose inputs are functions f_{1}, f_{2}, f_{3} and output is f.
Given that
f_{1}(x,y,z) = ∑(0,1,3,5), f_{2}(x,y,z) = ∑(6,7) and f(x,y,z) = ∑(1,4,5),
f_{3} is:
Σ(1,4,5)  
Σ(6,7)  
Σ(0,1,3,5)  
None of the above 
= (Σ(0,1,3,5) ⋅ Σ(6,7) + Σ(1,4,5))
[Σ(0,1,3,5) and Σ(6,7) ⇒ No common terms]
= (Σ(1,4,5))
Question 119 
Consider the following multiplexor where 10, 11, 12, 13 are four data input lines selected by two address line combinations A1A0 = 00,01,10,11 respectively and f is "the output of the multiplexor. EN is the enable input.
The function f(x,y,z) implemented by the above circuit is:
xyz'  
xy+z  
x+y  
None of the above 
F = (xyz' + xyz + y'zy + zy')z'
= (xyz' + xyz + y'z(y+1))z'
= (xyz' + xyz + y'z)z'
= (xy(z+z') + y'z)z'
= (xy + y'z)z'
= (xyz' + y'zz')
= (xyz')
Question 120 
Let f(A,B) = A' + B. Simplified expression for function f(f(x + y, y)z) is:
x'+z  
xyz  
xy'+z  
None of the above 
⇒ f(f((x+y), y), z)
⇒ f(((x+y)' + y), z)
⇒ f(((x'⋅y') + y), z)
⇒ f((x'⋅y') + y), z)
⇒ ((x'⋅y') + y)' + z
⇒ (x'⋅y')⋅y' + z
⇒ (x+y)⋅y' + z
⇒ (xy'+yy') + z
⇒ xy' + z
Question 121 
(a) Express the function f(x,y,z) = xy' + yz' with only one complement operation and one or more AND/OR operations. Draw the logic circuit implementing the expression obtained, using a single NOT gate and one or more AND/OR gates.
(b) Transform the following logic circuit (without expressing its switching function) into an equivalent logic circuit that employs only 6 NAND gates each with 2inputs.
Theory Explanation is given below. 
(A) f(x,y,z) = xy' +yz'
It is not possible to express only one NOT gate.
Question 122 
Consider the following circuit. A = a_{2}a_{1}a_{0} and B = b_{2}b_{1}b_{0} are three bit binary numbers input to the circuit. The output is Z = z_{3}z_{2}z_{1}z_{0}. R_{0}, R_{1} and R_{2} are registers with loading clock shown. The registers are loaded with their input data with the falling edge of a clock pulse (signal CLOCK shown) and appears as shown. The bits of input number A, B and the full adders are as shown in the circuit. Assume Clock period is greater than the settling time of all circuits.
(a) For 8 clocks pulses on the CLOCK terminal and the inputs A, B as shown, obtain the output Z (sequence of 4bit values of Z). Assume initial contents of R_{0}, R_{1} and R_{2} as all zeros.
A= 110 011 111 101 000 000 000 000 B= 101 101 011 110 000 000 000 000 Clock No 1 2 3 4 5 6 7 8
(b) What does the circuit implement?
Theory Explanation is given below. 
Question 123 
Consider the following 32bit floatingpoint representation scheme as shown in the formal below. A value is specified by 3 fields, a one bit sign field (with 0 for positive and 1 for negative values), a 24 bit fraction field (with the binary point being at the left end of the fraction bits), and a 7 bit exponent field (in excess64 signed integer representation, with 16 being the base of exponentiation). The sign bit is the most significant bit.
(a) It is required to represent the decimal value –7.5 as a normalized floating point number in the given format. Derive the values of the various fields. Express your final answer in the hexadecimal.
(b) What is the largest values that can be represented using this format? Express your answer as the nearest power of 10.
Theory of Explanation is given below. 
Question 124 
Given the following Karnaugh map, which one of the following represents the minimal SumOfProducts of the map?
xy+y'z  
wx'y'+xy+xz  
w'x+y'z+xy  
xz+y 
⇒ y'z + xy
Question 125 
Consider the following circuit with initial state Q_{0} = Q_{1} = 0. The D Flipflops are positive edged triggered and have set up times 20 nanosecond and hold times 0.
Consider the following timing diagrams of X and C; the clock period of C <= 40 nanosecond. Which one is the correct plot of Y?
Given clock is +edge triggered.
See the first positive edge. X is 0, and hence the output is 0, because
Y = Q_{1N} = D_{1}×Q_{0}' = 0⋅Q_{0}' = 0
At second +edge, X is 1 and Q_{0}' is also 1. So output is 1 (when second +ve edge of the clock arrives, Q_{0}' would surely be 1 because the setup time of flip flop is given as 20ns and clock period is ≥ 40ns).
At third +ve edge, X is 1 and Q_{0}' is 0, so output is 0.
Now output never changes back to 1 as Q_{0}' is always 0 and when Q_{0}' finally becomes 1, X is 0.
Hence option (A) is the correct answer.
Question 126 
The 2’s complement representation of (539)_{10} in hexadecimal is
ABE  
DBC  
DE5  
9E7 
For (539)_{10} = (1101 1110 0100)_{2}
1's complement = (1101 1110 0100)_{2}
2's complement = (1101 1110 0101)_{2}
= (DE5)_{16}
Question 127 
Consider the circuit shown below. The output of a 2:1 Mux is given by the function (ac' + bc).
Which of the following is true?
f = x1' + x2  
f = x1'x2 + x1x2'  
f = x1x2 + x1'x2'  
f = x1 + x2' 
g = (1 and x1’) or (0 and x1)
g = x1’
f = ac’ + bc
f = (a and x2′) or (b and x2)
f = (g and x2′) or (x1 and x2)
f = x1’x2’ + x1x2
Question 128 
Consider the circuit given below with initial state Q_{0} = 1, Q_{1} = Q_{2} = 0. The state of the circuit is given by the value 4Q_{2} + 2Q_{1} + Q_{0}
Which one of the following is the correct state sequence of the circuit?
1,3,4,6,7,5,2  
1,2,5,3,7,6,4  
1,2,7,3,5,6,4  
1,6,5,7,2,3,4 
Question 129 
(a) Is the 3variable function f = ∑(0,1,2,4) its selfdual? Justify your answer.
(b) Give a minimal productofsum form of the b output of the following excess3
to BCD converter.
Theory Explanation is given below. 
The function is self dual because
→ There is no mutually exclusive pair.
→ No. of minterms = No. of maxterms
(b)
Write Minimal POS.
Question 130 
A sequential circuit takes an input stream of 0’s and 1’s and produces an output stream of 0’s and 1’s. Initially it replicates the input on its output until two consecutive 0’s are encountered on the input. From then onward, it produces an output stream, which is the bitwise complement of input stream until it encounters two consecutive 1’s, whereupon the process repeats. An example of input and output stream is shown below.
The input stream: 101100 01001011 0 11 The desired output: 101100 10110100 0 11
JK masterslave flipflops are to be used to design the circuit.
(a) Give the state transition diagram.
(b) Give the minimized sumofproduct expression for J and K inputs of one of its
state flipflops.
Theory Explanation is given below. 
Question 131 
The number 43 in 2’s complement representation is
01010101  
11010101  
00101011  
10101011 
Question 132 
The simultaneous equations on the Boolean variables x, y, z and w,
x + y + z = 1 xy = 0 xz + w = 1 xy + = 0
have the following solution for x, y, z and w, respectively.
0 1 0 0  
1 1 0 1  
1 0 1 1  
1 0 0 0 
Question 133 
Which function does NOT implement the Karnaugh map given below?
(w + x)y  
xy + yw  
None of the above 
⇒ wy + wz + xy
Question 134 
The following arrangement of masterslave flip flops
has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),
1, 0  
1, 1  
0, 0  
0, 1 
When 11 is applied to Jk flip flop it toggles the value of P so op at P will be 1.
Input to D flip flop will be 0(initial value of P) so op at Q will be 0.
Question 135 
Consider the values A = 2.0 x 10^{30}, B = 2.0 x 10^{30}, C = 1.0, and the sequence
X: = A + B Y: = A + C X: = X + C Y: = Y + B
executed on a computer where floatingpoint numbers are represented with 32 bits. The values for X and Y will be
X = 1.0, Y = 1.0  
X = 1.0, Y = 0.0  
X = 0.0, Y = 1.0  
X = 0.0, Y = 0.0 
A = 2.0 * 10^{30}, C = 1.0
So, A + C should make the 31^{st} digit to 1, which is surely outside the precision level of A (it is 31^{st} digit and not 31^{st} bit). So, this addition will just return the value of A which will be assigned to Y.
So, Y + B will return 0.0 while X + C will return 1.0.
Question 136 
Design a logic circuit to convert a single digit BCD number to the number modulo six as follows (Do not detect illegal input):
(a) Write the truth table for all bits. Label the input bits I_{1}, I_{2}, …. With I_{1} as the least significant bit. Label the output bits R_{1}, R_{2}, …. With R_{1} as the least significant bit. Use 1 to signify truth.
(b) Draw one circuit for each output bit using, altogether, two twoinput AND gates, one twoinput gate and two NOT gates.
Theory Explanation is given below. 
Question 137 
Which of the following expressions is not equivalent to ?
x NAND X  
x NOR x  
x NAND 1  
x NOR 1 
Question 138 
Which of the following functions implements the Karnaugh map shown below?
⇒ CD+AD = D(A+C)
Question 139 
Booth’s coding in 8 bits for the decimal number –57 is
0 – 100 + 1000  
0 – 100 + 100  1  
0 – 1 + 100 – 10 + 1  
00 – 10 + 100  1 
Question 140 
The maximum gate delay for any output to appear in an array multiplier for multiplying two n bit number is
On^{2}  
O(n)  
O(log n)  
O(1) 
Total delay = 1 * 2n  1 = O(2n  1) = n
Question 141 
The number of full and halfadders required to add 16bit numbers is
8 halfadders, 8 fulladders  
1 halfadder, 15 fulladders  
16 halfadders, 0 fulladders  
4 halfadders, 12 fulladders 
But for rest of bits we need full address since carry from previous addition has to be included into the addition operation.
So, in total 1 half adder and 15 full adders are required.
Question 142 
Zero has two representations in
Sign magnitude  
1’s complement  
2’s complement  
None of the above  
Both A and B 
+0 = 0000
0 = 1000
1's complement:
+0 = 0000
0 = 1111
Question 143 
What happens when a bitstring is XORed with itself ntimes as shown:
[B⊕(B⊕(B⊕(B........ n times)]
complements when n is even  
complements when n is odd  
divides by 2^{n} always  
remains unchanged when n is even 
Consider:
B⊕(B⊕B)
= B⊕0
= 0 (if consider n times it remains unchanged)
Question 144 
A multiplexor with a 4 bit data select input is a
4:1 multiplexor  
2:1 multiplexor  
16:1 multiplexor  
8:1 multiplexor 
For 4 bit data it selects 2^{4} : 1 = 16: 1 input
Question 145 
The threshold level for logic 1 in the TTL family is
any voltage above 2.5 V  
any voltage between 0.8 V and 5.0 V  
any voltage below 5.0 V  
any voltage below V_{cc} but above 2.8 V 
Question 146 
The octal representation of an integer is (342)_{8}. If this were to be treated as an eightbit integer is an 8085 based computer, its decimal equivalent is
226  
98  
76  
30 
If this can be treated as 8 bit integer, then the first becomes sign bit i.e., '1' then the number is negative.
8085 uses 2's complement then
⇒ 30
Question 147 
The function represented by the Karnaugh map given below is:
A⋅B  
AB+BC+CA  
None of the above 
Question 148 
Which of the following operations is commutative but not associative?
AND  
OR  
NAND  
EXOR 
Question 149 
Suppose the domain set of an attribute consists of signed four digit numbers. What is the percentage of reduction in storage space of this attribute if it is stored as an integer rather than in character form?
80%  
20%  
60%  
40% 
We have four digits. So to represent signed 4 digit numbers we need 5 bytes, 4 bytes for four digits and 1 for the sign.
So required memory = 5 bytes.
Now, if we use integer, the largest no. needed to represent is 9999 and this requires 2 bytes of memory for signed representation.
9999 in binary requires 14 bits. So, 2 bits remaining and 1 we can use for sign bit.
So, memory savings,
= 5  2/5 × 100
= 60%
Question 150 
Let * be defined as x * y = x' + y. Let z = x * y. Value of z * x is
x'+y  
x  
0  
1 
Question 151 
An Nbit carry look ahead adder, where N is a multiple of 4, employs ICs 74181 (4 bit ALU) and 74182 (4 bit carry look ahead generator).
The minimum addition time using the best architecture for this adder is
proportional to N  
proportional to log N  
a constant  
None of the above 
Question 152 
Let f(x, y, z) = x' + y'x + xz be a switching function. Which one of the following is valid?
xz is a minterm of f  
xz is an implicant of f  
y is a prime implicant of f 
Question 153 
Given √224)_{r} = 13)_{r}.
The value of the radix r is:
10  
8  
5  
6 
Convert r base to decimal.
√2r^{2} + 25 + 4 = r + 3
Take square both sides,
2r^{2} + 2r + 4 = r^{2} + 6r + 9
r^{2}  4r  5 = 0
r^{2}  5r + r  5 = 0
r(r  5) + (r  5) = 0
r = 1, 5
r cannot be 1,
So r = 5 is correct answer.
Question 154 
Consider a logic circuit shown in figure below. The functions f_{1}, f_{2} and f (in canonical sum of products form in decimal notation) are:
f_{1}(w,x,y,z) = ∑8,9,10 f_{2}(w,x,y,z) = ∑7,8,12,13,14,15 f(w,x,y,z) = ∑8,9
The function f_{3} is
Σ9,10  
Σ9  
Σ1,8,9  
Σ8,10,15 
Since, f_{1} and f_{2} are in canonical sum of products form, f_{1}⋅f_{2} will only contain their common terms that is f_{1}⋅f_{2} = Σ8.
Now,
Σ8 + f_{3} = Σ8,9
So, f_{3}= Σ9
Question 155 
A ROM is sued to store the table for multiplication of two 8bit unsigned integers. The size of ROM required is
256 × 16  
64 K × 8  
4 K × 16  
64 K × 16 
No. of results possible = 2^{8} × 2^{8} = 2^{16} = 64K
Then total size of ROM = 64K × 16
Question 156 
Both’s algorithm for integer multiplication gives worst performance when the multiplier pattern is
101010 …..1010  
100000 …..0001  
111111 …..1111  
011111 …..1110 
Question 157 
Consider the following floating point number representation
The exponent is in 2's complement representation and mantissa is in the sign magnitude representation. The range of the magnitude of the normalized numbers in this representation is
0 to 1  
0.5 to 1  
2^{23} to 0.5  
0.5 to (12^{23}) 
Question 158 
Consider the circuit given below which has a four bit binary number b_{3}b_{2}b_{1}b_{0} as input and a five bit binary number d_{4}d_{3}d_{2}d_{1}d_{0} as output. The circuit implements:
Binary of Hex conversion
 
Binary to BCD conversion  
Binary to grey code conversion  
Binary to radix12 conversion 
Whenever, b_{2} = b_{3} = 1, then only 0100, i.e., 4 is added to the given binary number. Lets write all possibilities for b.
Note that the last 4 combinations leads to b_{3} and b_{2} as 1. So, in these combinations only 0010 will be added.
1100 is 12
1101 is 13
1110 is 14
1111 is 15
in binary unsigned number system.
1100 + 0100 = 10000
1101 + 0100 = 10001, and so on.
This is conversion to radix 12.
Question 159 
Consider the circuit in below figure. f implements
A + B + C  
A ⊕ B ⊕ C  
AB + BC + CA 
Question 160 
What is the equivalent Boolean expression in productofsums form for the Karnaugh map given below.
None of the above 
Question 161 
What values of A, B, C and D satisfy the following simultaneous Boolean equations?
A = 1, B = 0, C = 0, D = 1  
A = 1, B = 1, C = 0, D = 0  
A = 1, B = 0, C = 1, D = 1  
A = 1, B = 0, C = 0, D = 0 
Question 162 
The number of 1’s in the binary representation of
(3*4096 + 15*256 + 5*16 + 3) are:
8  
8  
10  
12 
= (11000000000000)_{2}
15 × 256 = 15 × 2^{8}
= (111100000000)_{2}
5 × 16 = 5 × 2^{4}
= (1010000)_{2}
3 = (11)_{2}
Hence, all binary numbers,
∴ 101's
Question 163 
The logic expression for the output of the circuit shown in figure below is:
None of the above. 
Question 164 
The number of flipflops required to construct a binary modulo N counter is __________.
⌈log_{2} N⌉ 
Question 165 
Consider nbit (including sign bit) 2’s complement representation of integer number. The range of integer values, N, that can be represented is _________ ≤ N ≤ _________
2^{n1} to 2^{n1}  1 
Question 166 
A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is _____.
5 
A 2^{5}x1 Multiplexer with 5 select lines selects one of the 32(= 2^{5}) registers at a time depending on the selection input.
The content from the selected register will be transferred through the output line to the Accumulator.
Question 167 
If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m + n is ____.
1034 
Each output line of the decoder is connected to one of the 1K(= 1024) rows of RAM.
Each row stores 1 Byte.
m=10 and n=1024
Question 168 
Consider the Boolean function z(a,b,c).
Which one of the following minterm lists represents the circuit given above?
Z = ∑(0,1,3,7)  
Z = ∑(2,4,5,6,7)  
Z = ∑(1,4,5,6,7)  
Z = ∑(2,3,5) 
Convert a+b’c into canonical form which is sum of minterms.
a + b’c = a(b + b’)(c + c’) + (a + a’)b’c
= abc + abc’ + ab’c + ab’c’ + ab’c + a’b’c
= Σ(7,6,5,4,1)
Question 169 
Consider three registers R1, R2 and R3 that store numbers in IEEE754 single precision floating point format. Assume that R1 and R2 contain the values (in hexadecimal notation) 0x42200000 and 0xC1200000, respectively.
If R3 = R1/R2, what is the value stored in R3?
0x40800000  
0x83400000  
0xC8500000  
0xC0800000 
R1 = 1.0100..0 X 2^{132127}
= 1.0100..0 X 2^{5}
= 101.0 X 2^{3}
= 5 X 8
= 40
R2 = (1) x 1.0100..0 X 2^{130127}
= (1) x 1.0100..0 X 2^{3}
= (1) x 101.0 X 2^{1}
= (1) x5 X 2
= 10
R3 = R1/R2
= 4
= (1)x 1.0 x 2^{2}
Sign = 1
Mantissa = 000..0
Exponent = 2+127 = 129
R3 = 1100 0000 1000 000..0
= 0x C 0 8 0 0 0 0 0
Question 170 
Identify the logic function performed by the circuit shown in figure.
exclusive OR  
exclusive NOR  
NAND  
NOR 
So finally, we can write
Question 171 
For the initial state of 000, the function performed by the arrangement of the JK flipflops in figure is:
Shift Register  
Mod3 Counter  
Mod6 Counter  
Mod2 Counter  
Both A and C 
Circuit behaves as shift register and mod6 counter. Note that this is the Johnson counter which is the application of shift register. And Johnson counter is mod2N counter.
Question 172 
Convert the following numbers in the given bases into their equivalents in the desired bases.
(a) 110.101)_{2} = x)_{10}
(b) 1118)_{10} = y)_{H}
(a) 6.625, (b) (45E)_{H} 
= 4 + 2 + 0 + 0.5 + 0 + 0.125
= 6.625
(b) 1118 mod 16 = E, quotient = 69
69 mod 16 = 5, quotient = 4
4 mod 16 = 4
Writing the mods result in reverse order gives (45E)_{H}.
Question 173 
A ROM is used to store the Truth table for a binary multiple unit that will multiply two 4bit numbers. The size of the ROM (number of words × number of bits) that is required to accommodate the Truth table is M words × N bits. Write the values of M and N.
M = 256, N = 8 
Output will be of 8 bits.
So memory will be of 2^{8} × 8.
So, M = 256, N = 8.
Question 174 
The Boolean function in sum of products form where Kmap is given below (figure) is:___________
ABC + B'C' + A'C' 
⇒ ABC + B'C' + A'C'
Question 175 
Consider a 3bit error detection and 1bit error correction hamming code for 4bit date. The extra parity bits required would be ________ and the 3bit error detection is possible because the code has a minimum distance of ________
Fill in the blanks 
Question 176 
The operation which is commutative but not associative is:
AND  
OR  
EXOR  
NAND 
Question 177 
All digital circuits can be realized using only
ExOR gates  
Multiplexers  
Half adders  
OR gates  
Both B and C 
Question 178 
For the digital in figure, the expression for the output f is ________
Out of syllabus. 
Question 179 
Consider the number given by the decimal expression:
16^{3} * 9 + 16^{2} * 7 + 16 * 5 + 3
The number of 1’s in the unsigned binary representation of the number is ________.
9 
(9753)_{16}
It's binary representation is,
1001011101010011
∴ The no. of 1's is 9.
Question 180 
When two 4bit binary number A = a_{3}a_{2}a_{1}a_{0} and B = b_{3}b_{2}b_{1}b_{0} are multiplied, the digit c_{1} of the product C is given by _________
c_{1} = b_{1}a_{0} ⊕ a_{1}b_{0} 
⇒ c_{1} = b_{1}a_{0} ⊕ a_{1}b_{0}
Question 181 
Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: Advantage of synchronous sequential circuits over asynchronous ones is:
faster operation  
ease of avoiding problems due to hazards  
lower hardware requirement  
better noise immunity
 
none of the above

Question 182 
Choose the correct alternatives (More than one may be correct). Two NAND gates having open collector outputs are tied together as shown in below figure.
The logic function Y, implemented by the circuit is,
Y = ABC + DE  
Y = ABC . DE  
Both (C) and (D) 
Y = ((ABC)' + (DE)')'
Y = ABC . DE
Note: Open gate works as NOR gate.
Question 183 
State whether the following statements are TRUE or FALSE with reason:
RAM is a combinational circuit and PLA is a sequential circuit.True  
False 
2) PLA is a combination circuit as ROM. PLA is a programmable AND array and a programmable OR array. A PLA with n inputs has fewer than 2n AND gates (otherwise there would be no advantage over a ROM implementation of the same size). A PLA only needs to have enough AND gates to decode as many unique terms as there are in the functions it will implement it.
Question 184 
The total number of Boolean functions which can be realized with four variables is:
4  
17  
256  
65,536 
2^{24} = 2^{16} = 65,536
Question 185 
The above circuit produces the output sequence:
1111 1111 0000 0000  
1111 0000 1111 000  
1111 0001 0011 010  
1010 1010 1010 1010 
So we can draw below table to get the output Q_{3}.
From the above table Q_{3} that is output is 1111 0001 0011 010.
So, answer is (C).
Question 186 
The output F of the below multiplexer circuit can be represented by
A⊕B⊕C  
A⊕B  
Question 187 
The exponent of a floatingpoint number is represented in excessN code so that:
The dynamic range is large.  
The precision is high.  
The smallest number is represented by all zeros.  
Overflow is avoided. 
Question 188 
The refreshing rate of dynamic RAMs is in the range of
2 microseconds  
2 milliseconds  
50 milliseconds  
500 milliseconds 
Question 189 
A set of Boolean connectives is functionally complete if all Boolean functions can be synthesized using those. Which of the following sets of connectives is NOT functionally complete?
EXNOR  
implication, negation  
OR, negation  
NAND 
→ NOR and NAND are the functionally complete logic gates, OR, AND, NOT only logic gate can be implemented by using them.
→ And (Implication, Negation) is also functionally complete.
Question 190 
The following bit pattern represents a floating point number in IEEE 754 single precision format
110000011101000000000000000000000The value of the number in decimal form is
10  
13  
26  
None of these 
Exponent bits  10000011
Exponent can be added with 127 bias in IEEE single precision format then outval exponent
= 10000011  127
= 131  127
= 4
→ In IEEE format, an implied 1 is before mantissa, and hence the outval number is
→ 1.101 × 2^{4} = (11010)_{2} = 26
Question 191 
Consider the following Boolean function of four variables
f(A,B,C,D) = Σ(2, 3, 6, 7, 8, 9, 10, 11, 12, 13)The function is
independent of one variable  
independent of two variables  
independent of three variable  
dependent on all the variables 
Independent of one variable '0'.
Question 192 
What Boolean function does the circuit below realize ?
xz+x’z’  
xz’+x’z  
x’y’+yz  
xy+y’z’ 
= (x’z’ + xz)’
= x’z + xz’
Question 193 
A processor that has carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2's complement numbers 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be:
1, 1, 0  
1, 0, 0  
0, 1, 0  
1, 0, 1 
Carry flag = 1
Overflow flag = 0
Sign bit = 0 (MSB bit is 0)
Overflow flag:
In computer processors, the overflow flag is usually a single bit in a system status register used to indicate when an arithmetic overflow has occurred in an operation.
Question 194 
Consider the following state diagram and its realization by a JK flip flop The combinational circuit generates J and K in terms of x, y and Q. The Boolean expressions for J and K are:
(x⊕y)’ and x’⊕y’  
(x⊕y)’ and x⊕y  
x⊕y and (x⊕y)’  
x⊕y and x⊕y 
Excitation table of JK:
Question 195 
The two numbers given below are multiplied using the Booth's algorithm.
Multiplicand : 0101 1010 1110 1110 Multiplier: 0111 0111 1011 1101How many additions/Subtractions are required for the multiplication of the above two numbers?
6  
8  
10  
12 
Now we have some values defined for pair of bits in Booth’s Algorithm,
00 → 0
11 → 0
01 → 1
10 → 1
Now after adding 0 to the LSB of the multiplier, start traversing from left to right and accordingly put the values defined above.
Hence, total 8 additions / subtractions required.
Question 196 
Which of the following input sequences for a crosscoupled RS flipflop realized with two NAND gates may lead to an oscillation?
11, 00  
01, 10  
10, 01  
00, 11 
So, 00 input cause indeterminate state which may lead to oscillation.
Question 197 
The following circuit implements a twoinput AND gate using two 21 multiplexers. What are the values of X_{1}, X_{2}, X_{3} ?
X1 = b, X2 = 0, X3 = a  
X1 = b, X2 = 1, X3 = b  
X1 = a, X2 = b, X3 = 1  
X1 = a, X2 = 0, X3 = b 
If we put
X1 = b
X2 = 0
X3 = a
Then we get,
F = ab
Question 198 
The following expression was to be realized using 2input AND and OR gates. However, during the fabrication all 2input AND gates were mistakenly substituted by 2input NAND gates.
(a.b).c + (a'.c).d + (b.c).d + a. dWhat is the function finally realized?
1  
a’ + b’ + c’ + d’  
a’ + b + c’ + d’  
a’ + b’ + c + d’ 
= ((ab)'c)' + ((a'c)'d)' + ((bc)'d)' + (ad)'
= ab + c' + a'c + d' + bc + d' + a' + d'
= ab + c' + a'c + bc + a' + d'
= ab + c' + bc + a' + d'
= b + c' + bc + a' + d'
= a' + b + c' + d'
Question 199 
What is the final value stored in the linear feedback shift register if the input is 101101?
0110  
1011  
1101  
1111 
Question 200 
(C012.25)_{H} – (10111001110.101)_{B} =
(135103.412)_{O}  
(564411.412)_{O}  
(564411.205)_{O}  
(135103.205)_{O} 
= 1100000000010010.00100101  0000010111001110.10100000
= 1011101001000011.10000101
= 1011101000011.100001010
= (135103.412)_{O}
Question 201 
The line T in the following figure is permanently connected to the ground.
Which of the following inputs (X1 X2 X3 X4) will detect the fault?
0000  
0111  
1111  
None of these 
Since the problem is in the link T which is connected as input to NOR gate. So to check link T we have to make the output dependent on T by deactivating link M. So to deactivate link M, the output at M should be 0, as link M is input to NOR gate. So, to output at M as 0,
X1 = 1
X2 = 1
X3 = 1
X4 = 0
∴ None of the given option is correct.
Question 202 
Consider the following expression
ad' + (ac)' + bc'dWhich of the following Karnaugh Maps correctly represents the expression?
ad' + a'c' + bc'd
Hence, option (A) matches.
Question 203 
Consider the following expression
ad' + (ac)' + bc'dWhich of the following expressions does not correspond to the Karnaugh Map obtained for the above expression?
c’d’+ ad’ + abc’ + (ac)’d  
(ac)’ + c’d’ + ad’ + abc’d  
(ac)’ + ad’ + abc’ + c’d  
b’c’d’ + acd’ + (ac)’ + abc’ 
a'c' + ad' + abc' + c'd
Not equivalent to the Kmap, we get in previous question.
Question 204 
The addition of 4bit, two’s complement, binary numbers 1101 and 0100 results in
0001 and an overflow  
1001 and no overflow  
0001 and no overflow  
1001 and an overflow 
2's complement of 1100 = 1100
Add = 1111
Now convert 1111 to normal form.
⇒ 0000 (1's complement)
⇒ 0001 (2's complement) No carry bit.
Question 205 
The boolean function for a combinational circuit with four inputs is represented by the following Karnaugh map.
Which of the product terms given below is an essential prime implicant of the function?
QRS  
PQS  
PQ'S'  
Q'S' 
Question 206 
The majority function is a Boolean function f(x, y, z) that takes the value 1 whenever a majority of the variables x, y, z and 1. In the circuit diagram for the majority function shown below, the logic gates for the boxes labeled P and Q are, respectively,
XOR, AND  
XOR, XOR  
OR, OR  
OR, AND 
Thus we have OR and AND which gives different outputs on (0,0) and (1,1).
The encodes can be hence select from the two and decide output of the function according to x.
Question 207 
When multiplicand Y is multiplied by multiplier X = x_{n1}x_{n2} ...x_{0} using bitpair recoding in Booth's algorithm, partial products are generated according to the following table.
The partial products for rows 5 and 8 are
2Y and Y  
2Y and 2Y  
2Y and 0  
0 and Y 
⇒ 2Y and 0
Question 208 
A twoway switch has three terminals a, b and c. In ON position (logic value 1), a is connected to b, and in OFF position, a is connected to c. Two of these twoway switches S1 and S2 are connected to a bulb as shown below.
Which of the following expressions, if true, will always result in the lighting of the bulb ?
From this we can clearly know that given is EXNOR operation i.e.,
(S1⊙S2) = (S1⊕S2)'
Question 209 
How many pulses are needed to change the contents of a 8bit up counter from 10101100 to 00100111 (rightmost bit is the LSB)?
134  
133  
124  
123 
→ First counter is move from 172 to 255 = 83 pulses
→ 255 to 0 = 1 pulse
→ 0 to 39 = 39 pulses
Total = 83 + 1 + 39 = 123 pulses
Question 210 
A line L in a circuit is said to have a stuckat0 fault if the line permanently has a logic value 0. Similarly a line L in a circuit is said to have a stuckat1 fault if the line permanently has a logic value 1. A circuit is said to have a multiple stuckat fault if one or more lines have stuck at faults. The total number of distinct multiple stuckat faults possible in a circuit with N lines is
3^{N}  
3^{N}  1  
2^{N}  1  
2 
This is because the total possible combinations (i.e., a line may either be at fault (in 2 ways i.e., stuck at 0 or 1) or it may not be, so there are only 3 possibilities for a line) is 3^{N}. In only one combination the circuit will have all lines to be correct (i.e., not a fault). Hence, total combinations in which distinct multiple stuckatfaults possible in a circuit with N lines is 3^{N}  1.
Question 211 
(34.4)_{8} × (23.4)_{8} evaluates to
(1053.6)_{8}  
(1053.2)_{8}  
(1024.2)_{8}  
None of these 
(34.4)_{8} = 3×8^{1} + 4×8^{0} + 4×8^{1}
= 24 + 4 + 0.5
= (28.5)_{10}
(23.4)_{8} = 2×8^{1} + 3×8^{0} + 4×8^{1}
= 16 + 3 + 0.5
= (19.5)_{10}
Now,
(28.5)_{10} × (19.5)_{01} = (555.75)_{10}
Now,
(555.75)_{10} = ( ? )_{8}
To convert the integer part,
We get, 1053.
To convert the fractional part, keep multiplying by 8 till decimal part becomes 0,
∴ (555.75)_{10} = (1053.6)_{8}
Question 212 
The circuit shown below implements a 2input NOR gate using two 24 MUX (control signal 1 selects the upper input). What are the values of signals x, y and z?
1, 0, B  
1, 0, A  
0, 1, B  
0, 1, A 
g = Ax + Bz'
In MUX2, the equation is
f = xg + yg'
= x(Az+Bz') + y(Az+Bz')'
Function f should be equal to (A+B)'.
Just try to put the values of option (D), i.e., x=0, y=1, z=A,
f = 0(AA+BA') +1(AA+BA')'
= (A+B)'
∴ Option (D) is correct.
Question 213 
n instruction set of a processor has 125 signals which can be divided into 5 groups of mutually exclusive signals as follows:
Group 1 : 20 signals, Group 2 : 70 signals, Group 3 : 2 signals, Group 4 : 10 signals, Group 5 : 23 signals.
How many bits of the control words can be saved by using vertical microprogramming over horizontal microprogramming?
0  
103  
22  
55 
= 20 + 70 + 2 + 10 + 23
= 125
Now lets consider vertical microprogramming. In vertical microprogramming no. of bits required to activate 1 signal in group of N signals, is ⌈log_{2} N⌉. And in the question 5 groups contains mutually exclusive signals,
group 1 = ⌈log_{2} 20⌉ = 5
group 2 = ⌈log_{2} 70⌉ = 7
group 3 = ⌈log_{2} 2⌉ = 1
group 4 = ⌈log_{2} 10⌉ = 4
group 5 = ⌈log_{2} 23⌉ = 5
Total bits required in vertical microprogramming
= 5 + 7 + 1 + 4 + 5
= 22
So, number of bits saved is
= 125  22
= 103
Question 214 
What is the minimum number of NAND gates required to implement a 2input EXCLUSIVEOR function without using any other logic gate?
3  
4  
5  
6 
To create 2input ExclusiveOR function we require 4 NAND gates.
Question 215 
What is the minimum size of ROM required to store the complete truth table of an 8bit × 8bit multiplier?
32 K × 16 bits  
64 K × 16 bits  
16 K × 32 bits  
64 K × 32 bits 
Possible combination in ROM = (2^{8} × (2^{8}) [size of truth table]
= 2^{16}
= 64 KB
= 64 K ×16 bits
Question 216 
Using a 4bit 2’s complement arithmetic, which of the following additions will result in an overflow?
1. 1100 +1100 2. 0011 +0111 3. 1111 +0111
1 only  
2 only  
3 only  
1 and 3 only 
1) Sign bit of two input numbers is 0, and the result has sign bit 1.
2) Sign bit of two input numbers is 1, and the result has sign bit 0.
So, only (2) causes overflow.
Question 217 
The number (123456)_{8} is equivalent to
(A72E)_{16} and (22130232)_{4}  
(A72E)_{16} and (22131122)_{4}  
(A73E)_{16} and (22130232)_{4}  
(A62E)_{16} and (22120232)_{4}

= (00 1010 0111 0010 1110)_{2}
= (A72E)_{16}
Also,
(001 010 011 100 101 110)_{2}
= (00 10 10 01 11 00 10 11 10)_{2}
= (22130232)_{4}
Question 218 
The function AB’C + A’BC + ABC’ + A’B’C + AB’C’ is equivalent to
AC’+ AB + A’C  
AB’+ AC’+ A’C  
A’B+ AC’+ AB’  
A’B + AC + AB’ 
⇒ A'C + AC' + AB'
Question 219 
Consider a parity check code with three data bits and four parity check bits. Three of the code words are 0101011, 1001101 and 1110001. Which of the following are also code words?
1. 0010111 2. 0110110 3. 1011010 4. 0111010
1 and 3  
1, 2 and 3  
2 and 4  
1, 2, 3 and 4 
Given transmitted codewords are
By inspection we can find the rule for generating each of the parity bits,
Now from above we can see that (I) and (III) are only codewords.
Question 220 
3+n ternary digits  
2n/3 ternary digits  
n(log_{2}3) ternary digits  
n(log_{3}2 ) ternary digits 
→ But in question they are given ternary numbers, it means 3x1.
→ Both will take different no. of bits to represent the same number.
3^{x} 1 = 2^{n} 1
3^{x} = 2^{n}
Apply log on both side
x= log_{3}( 2^{n})
x=n*log_{3}2 .
Question 221 
AC'  
BC'  
C'  
A 
Y = AC' + B'C' + A'BC'
Y = (A + A'B)C' + B'C'
Y = (A + B)C' + B'C'
Y = AC' + BC' + B'C'
Y = AC' + C'(B + B') → B + B' = 1
Y = AC' + C'
Y = C'
Question 222 
(( A + B )’ +C ) ( D’E’ ))  
(( A + B )’ + C ) ( DE’ ))  
( A + ( B + C )’ ) ( D’E )  
( A + B + C’ ) ( D’E’ ) 
Y = (((A + B)' + C)' + ((D + E)')')'
Y = ((A + B)' + C)')' . (D + E)'
Y = ((A + B)' + C) (D'E')
Question 223 
full adder  
full subtractor  
shift register  
decade counter 
Question 224 
subtract 0011 from the sum  
add 0011 to the sum
 
subtract 0110 from the sum
 
add 0110 to the sum

Example:
x+3
y+3

(x+y+6)
Here, sum is excess6. Hence, subtract 0011 to make it excess3.
Question 225 
7ns  
9ns  
11ns  
13ns 
Step2: 1st AND gate(ab’) takes 19ns because combining NOT gate(9ns)+extra(10ns)
Step3: Second AND gate(bc) takes only 12ns because we are not using inverter here.
Step4: A glitch will take 1st AND gate(ab’)  Second AND gate(bc)
=1912
=7ns
Question 226 
Q_{n+1} = S + RQ_{n}  
Q_{n+1}= RQ^{’}_{n} + SQ_{n}  
Q_{n+1}= S^{’} + RQ^{n}  
Q_{n+1} = S + R^{’}Q_{n} 
So, by simplifying using kmaps:
characteristic equation of an SR flipflop = Q_{n+1} = S + R^{’}Q_{n}
Question 227 
1.8^{o}  
3.4^{o}  
2.8^{o}  
1.4^{o} 
Optical encoders enable an angular displacement to be converted directly into a digital form.
Encoder resolution is often referred to in bits, which are binary units: a 16 bit resolution rotary encoder will have 65,536 (216) increments per turn, or PPR.
In the given question, 8bit optical encoder will have 2^{8} increments Resolution = 360/2^{n} = 360/2^{8} = 1.4^{o}
Question 228 
8  
9  
10  
12 
= (2 + 1)× 512 + (4 + 2 + 1)× 64 + (4 + 1)× 8 + 2 + 1
= 1024 + 512 + 64 x 4 + 64 x 2 + 64 + 32 + 8 + 2 + 1
= 1024 + 512 + 256 + 128 + 64 + 32 + 8 + 2 + 1
As 1024 has ten 0’s followed by 1, 512 has nine 0’s followed by 1 and so on..
So, the expression will contain total nine 1’s and will be be represented as 11111101011.
Question 229 
{ AND, OR }  
{ AND, NOT }  
{ NOT, OR }  
{ NOR } 
→ NAND and NOR gates are universal gates.
→ With the help of universal gates, we can construct any boolean expressions. These gates are also called functionally complete.
→ AND+NOT=NAND→ Functionally Complete
→ OR+NOT=NOR→ Functionally Complete
→ NOR→ Functionally Complete
→ AND+OR→ Not functionally complete
Question 230 
0.60  
0.52  
0.54  
0.50 
= (0.6)_{8}
Option (A) is correct.
Question 231 
Q = 0, Q’ = 1  
Q = 1, Q’ = 0  
Q = 1, Q’ = 1  
Indeterminate states 
Question 232 
Toggle Switch  
Latch  
Stepping Switch  
SR flip flop 
There are two types of ring counters:
1. A straight ring counter, also known as a onehot counter, connects the output of the last shift register to the first shift register input and circulates a single one (or zero) bit around the ring.
2. A twisted ring counter, also called switchtail ring counter, walking ring counter, Johnson counter, or Möbius counter, connects the complement of the output of the last shift register to the input of the first register and circulates a stream of ones followed by zeros around the ring.
Note: Ring counter is analogous to Stepping Switch
Question 233 
0.1 and 5V  
0.6 and 3.5 V  
0.9 and 1.75 V  
1.75 and 0.9 V 
→ However, real TTL gate circuits cannot output such perfect voltage levels, and are designed to accept “high” and “low” signals deviating substantially from these ideal values.
Question 234 
1 × 10^{128} and 2^{15}× 10^{15}
 
1 × 10^{256} and 2^{15}× 10^{255}  
1 × 10^{128} and 2^{15}× 10^{127}  
1 × 10^{128}and 2^{15}– 1 × 10^{127} 
According to question 16 bit mantissa and 8 bit Exponent.
Since the mantissa is always 1.xxxxxxxxx in the normalised form, no need to represent the leading 1.
Single Precision: mantissa ===> 1 bit + 15 bits
The largest mantissa value value is 2^{15}1 (one bit meant for sign)
The largest exponent value is 2^{7}1=127
The smallest mantissa value is 0000 0000 0000 0000(one bit is always 1) =1
The Smallest (largest negative) exponent value is 1111 1111 (which is 2’s complement form) 2^{8}=128
Question 235 
lower bit density and higher power consumption  
higher bit density and higher power consumption  
lower bit density and lower power consumption  
higher bit density and lower power consumption 
→ DRAM stands for Dynamic Random Access Memory. It is used in most of the computers. It is the least expensive kind of RAM. It requires an electric current to maintain its electrical state. The electrical charge of DRAM decreases with time that may result in loss of DATA.
→ DRAM is recharged or refreshed again and again to maintain its data. The processor cannot access the data of DRAM when it is being refreshed. That is why it is slow.
SRAM (Static Random Access Memory)
→ SRAM stands for Static Random Access Memory. It can store data without any need of frequent recharging. CPU does not need to wait to access data from SRAM during processing. That is why it is faster than DRAM. It utilizes less power than DRAM.
→ SRAM is more expensive as compared to DRAM. It is normally used to build a very fast memory known as cache memory
Question 236 
CD73E  
ABD3F  
7CDE3  
FA4CD 
7 C D E 3
(7CDE3)16
Question 237 
4  
5  
6  
7 
Question 238 
[log(n)] + 1 bits  
[log (n1)) + 1 bits  
[log (n+1)] + 1 bits  
None of the above 
Question 239 
10  
8  
6  
5 
For f(x) to be maximum
f'(x) = 4x  2 = 0
⇒ x = 1/2
So at x = 1/2, f(x) is an extremum (either maximum or minimum).
f(2) = 2(2)^{2}  2(2) + 6 = 10
f(1/2) = 2 × (1/2)^{2}  2 × 1/2 + 6 = 5.5
f(0) = 6
So, the maximum value is at x=2 which is 10 as there are no other extremum for the given function.
Question 240 
(A + B) ∙ (A’ + C) ∙ (B + C) = (A + B) ∙ (A’ + C)  
AB + A’C + BC = AB + BC  
AB + A’C + BC = (A + B) ∙ ( A ‘+ C) ∙ (B + C)  
(A + B) ∙ (A’ + C) ∙ (B + C) = AB + A’C 
XY+XZ+YZ=XY+XZ Consensus Law
For minterm: AB + A'C +BC = AB + A'C
AND for maxterm : ( A + B ).( A' + C ).( B + C ) = ( A + B ).(A' + C )
Question 241 
X_{0}X_{1}X_{2} … X_{n} + X_{1}X_{2} … X_{n} + X_{2}X_{3} … X_{n} + ⋯ + X_{n}  
X_{0}X_{1} + X_{2}X_{3} + … X_{n1} X_{n}  
X_{0} + X_{1} + X_{2} + … + X_{n}  
X_{0}X_{1} + X_{3} … X_{n−1} + X_{2}X_{3} + X_{5} … X_{n−1} + ⋯ + X_{n−2}X_{n−1} + X_{n}  
None of the above 
=(X_{0}X_{1}X_{3}+X_{2}X_{3}+X_{4})X_{5}+⋯+X_{N}
=X_{0}X_{1}X_{3}X_{5}+X_{2}X_{3}X_{5}+X_{4}X_{5}+⋯+X_{N}
=X_{0}X_{1}X_{3}X_{5}⋯X_{N−1}+X_{2}X_{3}X_{5}⋯X_{N−1}+X_{4}X_{5}X_{7}⋯X_{N−1}+⋯+X_{N}
Question 242 
(241)_{5}  
(143)_{6}  
(165)_{7}  
(39)_{16} 
N^{2} = 7*8*8*8 + 6*8*8 + 0 + 1*8
N^{2} = 3969
N = (63)^{10}
Now, (241)_{5} = 2*5*5 + 4*5 + 1 = 71
Option (A) is incorrect.
(143)_{6} = 1*6*6 + 4*6 + 3 = 63
Option (B) is correct.
Question 243 
3  
3 or 4  
2  
None of these 
Since LHS has 3 as the base and RHS has ‘x’ base,
1 * 3*3 + 2 * 3 + x * 1 = 1 * x*x + 2 * x + 3
9 + 6 + x = x2 + 2x + 3
x2 + x  12 = 0
x2 + 4x  3x  12 = 0
x( x + 4 )  3(x + 4) = 0
(x + 4)(x  3) = 0
x = 3 and 4
But, both the values are infeasible.
Alternative explanation :
According to the rules of number systems , the numbers present in a number system should not be greater than the base of the number system.
According to LHS , (12x)3 tells us that the value of x should be less than 3.
According to RHS , (123)x tells us that the value of x should be greater than 3 as largest digit in 123 is 3.
Therefore, any combination is not possible.
Question 244 
result in an overflow error  
result in an underflow error  
be 0  
be 5.28 E + 11 
The computer uses 8 digit mantissa and 2 digit exponent:
a = 0.052 We can represent the number in M*E So a= 0.052 = 0.52*101
mantissa = 0.52, exponent = −1.
b = 28E+11, We can represent the number in M*E So b = 28E+11= 0.28*1013
mantissa = 0.28, exponent = 13.
To add b+a, Small exponent number, a is shifted
to 13(1) = 14 places to right side
a = 0.0000000000000052E+13
From the given data computer uses only 8 digit mantissa, so digits beyond 8th position will be discarded.
So a = 0.00000000E+13 = 0.0 E+13
b + a = (0.28E + 13) + (0.0E + 13 )
= 0.28E + 13
Then b + a  b = (0.28E + 13)  (0.28E + 13)
= 0
Question 245 
C’ + AB’  
C’ (A’ + B)  
B’C’ + AB’  
None of these. 
The following expression can be simplified as:
(A + C')(B'+ C')
= AB' + AC' + B'C' + C
'
= AB' + C'(A + B' + 1) // 1 + A = 1
= AB' + C'
Question 246 
A + AB  
AB  
A'  
A + B 
A'(A’ + B’)
This expression can be simplified as:
= A'A' + A'B'
= A' + A'B'
= A'(1 + B') // 1 + B' = 1
= A'
Question 247 
512  
1024  
128  
32 
= 32x1024x32 bits. [Note: 1k=1024 bytes]
Step2: Given RAM chip capacity is 128x8 bits
Step3: Required size/Given size
=(32*1024*32) / (128*8)
=1024
Question 248 
entirely different  
identical  
complementary  
dual 
The Two functions are entirely different as:
Figure 1: The logic gates derive the following function:
F1 = ((X + Y')' + X)'
= ((X + Y')')'. X'
= (X + Y'). X'
= XX' + X'Y'
= X'Y'
Figure 2: It is simple AND gate which has 1 input already complimented.
F2 = XY'
So, these two functions are entirely different.
Question 249 
1  
0  
X  
X’ 
Question 250 
0 XOR 0 = 0  
1 XOR 1 = 1  
1 XOR 0 = 1  
B XOR B = 0 
XOR gate only returns 1 as the output when both inputs are different and in every other case, it returns 0.
So, options (A), (C) and (D) are correct.
Question 251 
One  
Two  
Three  
Four 
Question 252 
n bits  
(n+3) bits  
(n+2) bits  
(n+1) bits 
Example = 2 Decimal numbers are (7)_{10} and (7)_{10}
= Equivalent binary numbers are (111)_{2} + (111)_{2}
= Adding two binary numbers, the final result will be n+1 number (1110)_{2}
Question 253 
low  
high  
same  
different 
Question 254 
(1217)_{16}  
(028F)_{16}  
(2297)_{1o}  
(0B17)_{16} 
=(0010 1000 1111)_{2}
=(2 8 F)_{16}
Question 255 
Binary code  
Gray code  
Excess 3 code  
Octal code 
Gray codes are less errorprone for mechanical devices that involve making and breaking electrical circuits because they only change in one bit position at a time.
So, they are considered as the minimum error code.
Question 256 
Lower hardware requirement  
Better noise immunity  
Faster operation  
None of the above 
Question 257 
roundoff errors  
syntax errors  
runtime errors  
logic errors 
→A runtime error is a program error that occurs while the program is running.
→A logic error is a bug in a program that causes it to operate incorrectly, but not to terminate abnormally (or crash). A logic error produces unintended or undesired output or other behaviour, although it may not immediately be recognized.
→Roundoff error is the difference between an approximation of a number used in computation and its exact (correct) value. In certain types of computation, roundoff error can be magnified as any initial errors are carried through one or more intermediate steps and repeated execution.
Question 258 
1023  
31  
10  
127 
2^{10} x1 MUX has 2^{10} inputs.
Level1 has 2^{9} (=512) 2x1 multiplexers which take 2*2^{9} = 2^{10} inputs and produces 512 outputs.
Similarly,
Level2 has 256 MUX.
Level3 has 128 MUX.
Level4 has 64 MUX.
Level5 has 32 MUX.
Level6 has 16 MUX.
Level7 has 8 MUX.
Level8 has 4 MUX.
Level9 has 2 MUX.
Level10 has 1 MUX.
Total number of Multiplexers= 512+256+128+64+32+16+8+4+2+1
=1023
Question 259 
0  
1  
4  
7 
No GATE is required to implement the function A.
Question 260 
AB + AC + BC  
A + BC  
A + B  
A + B + C 
A(B+C) + AB + (A+B)C = AB + AC + AB + AC + BC
= (AB+AB) + (AC+AC) + BC
= AB + AC + BC
Question 261 
D = AB + A’B , X = A’B  
D = A’B + AB’ , X = AB’  
D = A’B + AB’ , X = A’B  
D = AB + A’B , X = AB’ 
AB= D= A’B + AB’
X= A’B
Question 262 
Gate No. 1  
Gate No. 2  
Gate No. 3  
Gate No. 4 
= W’ + Z’XY
The term W’Z is redundant which is represented by GATE 2.
Question 263 
combinational circuit alone  
sequential circuit only  
Both (a) and (b)  
None of the above 
→ Dynamic hazards often occur in larger logic circuits where there are different routes to the output (from the input).
→ If each route has a different delay, then it quickly becomes clear that there is the potential for changing output values that differ from the required / expected output. e.g.
→ A logic circuit is meant to change output state from 1 to 0, but instead changes from 1 to 0 then 1 and finally rests at the correct value 0. This is a dynamic hazard.
→ As a rule, dynamic hazards are more complex to resolve, but note that if all static hazards have been eliminated from a circuit, then dynamic hazards cannot occur.
Question 264 
Excess3 code  
Gray code  
BCD code  
Hamming Code 
X2= Y1⊕ Y2
X3= Y2 ⊕ Y3
Question 265 
An oscillating circuit and its output is a square wave  
The one whose output remains stable in ‘1’ state  
The one having output remains stable in ‘0’ state  
has a single pulse of three times propagation delay 
An odd number of cascaded NOT gates produce a square wave.
Note: Duty cycle= Ratio of durations in which the circuit is ON and OFF in a cycle.
Question 266 
224174  
425174  
6173  
225174 
MAke blocks of 3 bits each from LSB to MSB.
(Note: In the last block append zeros (as MSBs) if number bits is not three)
(000 010 010 101 001 111 100)
Each of the above blocks represents a digit in base 8 and they can be converted to base 8 as shown below.
= (0 2 2 5 1 7 4)_{8}
Question 267 
Cyclic Redundancy Code  
Weighted Code  
SelfComplementing Code  
Algebraic Code 
→ In excess3 code, each of the 4bit numbers represents decimal digit which is 3 less than the actual decimal digit. So the bits have no fixed weight.
Excess3 code is neither CRC nor Algebraic Code which is used for error detection and/or correction.
Question 268 
(P’Q + R)  
(P + Q’R’)  
(P Q’ + R )  
(PQ + R) 
Question 269 
1010  
0101  
1000  
1001 
(Decimal value of maximum 4bit number +1 )/2= (15+1)/2=8
Question 270 
JK Flipflop is faster than SR flipflop  
JK flipflop has a feedback path  
JK flipflop accepts both inputs 1  
None of them 
> JK flip flop doesn’t have a feedback path.
Question 271 
2^{n1} to (2^{n1} – 1)  
(2^{n1} – 1)to (2^{n1} – 1)  
2^{n1} to (2^{n1} )  
(2^{n1} + 1)to (2^{n1} – 1) 
Question 272 
1, 1, 0
 
1, 0, 0  
0, 1, 0  
1, 0, 1

Question 273 
6  
8  
10  
12 
Question 274 
0001 and an overflow
 
1001 and no overflow
 
0001 and no overflow  
1001 and an overflow

Another number is 1101(3 is decimal value)
Adding of 3 and 4, the result is 1 and there is no overflow
Question 275 
BC’D’ + A’C’D + AB’D
 
ABC’ + ACD + B’C’D  
ACD’ + A’BC’ + AC’D’  
A’BD + ACD’ + BCD’ 
Question 276 
Independent of one variable  
Independent of two variables  
Independent of three variables  
Dependent on all variables 
w and y are not needed to represent the function f. So f is independent of two variables.
Question 277 
All 1’s  
All 0’s  
X  
Y 
Question 278 
28  
15  
26  
28 
Floating Point number in Binary = 1100 0001 1101 0000 0000 0000 0000 0000
In 32bit, single precision floating point IEEE representation, first MSB represents sign of mantissa: 1 is used to represent a negative mantissa and 0 for a positive value of mantissa, next 8 bits are for exponent value and then 23 bits represents mantissa.
Value of exponent = 131127 = 4
Mantissa = 1.1010000 0000 0000 0000 0000
Floating point number = 1.1010000 0000 0000 0000 0000
Converting the above one into decimal no (1*2^{0}+1*2^{1}*0*2^{2}+1*2^{2}+0* 2^{3} +.....)
= (1+½+⅛)=13/8
Decimal value =sign*Exponent*mantissa=1*4*13/8
= 26
Question 279 
Y+XZ  
X+YZ  
XY+Z  
XZ+Y 
(X+Y)(X+Z) = X + XZ + XY + YZ
= X(1 + Z + Y) + YZ // as (1 + A = A)
= X.1 + YZ
= X + YZ
Question 280 
Set to 1  
Set to 0
 
No change in state
 
Forbidden 
Question 281 
X. Y + X’ Y’  
X. Y + X. Y  
X. Y
 
X + Y 
Question 282 
2  
4  
8  
16 
Number of chips needed are = total memory capacity / RAM memory
= 2048 bytes / 128 x 8 =2048x8/128x8
= 16
Question 283 
7  
5  
8  
6 
→ In other words, it measures the minimum number of substitutions required to change one string into the other, or the minimum number of errors that could have transformed one string into the other.
→ Given HexaDecimal numbers are 0xAA and 0x55.
Decimal equivalent of 0xAA is 170
Binary form of 0xAA is 1010 1010
Decimal equivalent of 0x55 is 85
Binary form of 0xAA is 0101 0101
The two numbers binary length length is 8.
→ If you observe all the bits of above two binary numbers, both numbers have different bits in all positions.
→ So according to definition , the number of positions at which the corresponding symbols are different which is 8.
Question 284 
7  
8  
9 
Step2: Level2 has total 8*8=64 output lines. Based on the input, the decoder in level1 enables one of the Decoders in level2.
Step3: The enabled decoder in level2 selects one of the output lines and keeps that line high and remaining lines low.
Question 285 
101010.110  
100110.101  
101010.101  
100110.110 
Question 286 
OR gate  
AND gate  
NAND gate  
XOR gate 
Question 287 
0x22  
0x1c  
0x16  
results in overflow 
Representation of the above two numbers in the 4bit number format as follows
0x14 = 0001 0100
0x08 = 0000 1000
1. After performing the addition of the two binary numbers , we will get 0001 110
2. The lower value of BCD is 0000 which is 0 and upper value is1001 which is 9 If the four bit result of addition is greater than 9 and if a carry bit is present in the result then it is invalid and we have to add 6 whose binary equivalent is (0110)_{2} to the result of addition. Then the resultant that we would get will be a valid binary coded number
The result from the BCD addition is greater than 9,So we need to add to “6” to the result.
0001 1100
0000 0110

0010 0010 (22)
So, the final resultant number is 22
Question 288 
4  
5  
6  
8 
(1102)_{3} = (123) _{x}
= 1x3x3x3 + 1x3x3 + 2 = 1x^{2} + 2x + 3
= 27 + 9 + 2 = 1x^{2} + 2x + 3
= x = 5
Question 289 
{NOT, OR}  
{NOR}  
{AND, OR}  
{AND, NOT} 
Question 290 
1032  
776  
1284  
1536 
Total programmable fuses= fuses required by AND gates + fuses required by OR gates
Fuses required by AND gates = 2* no. of inputs * no. of and gates = 2*16*32= 1024 fuses
Fuses required by OR gates = no. Of outputs * no. Of and gates = 8* 32 = 256
Total fuses = 1024+ 256= 1280
Question 291 
1  
2  
9  
10 
→The total number of values are 8 (2^{3})
→The initial value of counter is 1 So the counter will return to initial stage after 8 pulses.
→At Eight stage, again the counter value is 1
→At Ninth stage, the counter value is 2.
Question 292 
A + A’BCD  
AB + CD  
A + BCD  
ABC + D 
Question 293 
0, 1,1  
1, 1,0  
1, 0,1  
0, 1,0 
Question 294 
5  
6  
7  
8 
In the IEEE 7542008 standard, the 32bit base2 format is officially referred to as binary32; it was called single in IEEE 7541985. IEEE 754 specifies additional floatingpoint types, such as 64bit base2 double precision and, more recently, base10 representations.
We can convert the binary into decimal representation by using the following steps
let the number of digits in decimal digits be ‘x’
2^{23} = 10^{x }
After taking log on both sides
log_{2}10^{x} =log2 2^{23}
x log_{2}