DigitalLogicDesign
Question 1 
bias of 127.
S : 1 E : 10000001 F : 11110000000000000000000
Here S, E and F denote the sign, exponent and fraction components of the floating point representation.
The decimal value corresponding to the above representation (rounded to 2 decimal places) is _______
A  7.75 
Sign bit S= 1. The given number is a negative number.
Biased Exponent E = 2^{7} + 1= 129
Actual Exponent e = E127
= 129 127
= 2
The decimal value= (1)^{s} x 1.M x 2^{e}
= (1) 1 x 1.1111 x 2^{2}
=  (111.11)
=  (7 + 0.75)
= 7.7
Question 2 
A  21 
B  528

C  D2 
D  15 
On converting (210)3 in decimal, we will get:=>
2*3^{2}+1*3=2*9+3=21_{10 }
=>(15)_{16}
Question 3 
A  
B  
C  
D 
XY’+Z’ is a minimal SoP expression which represents the function (X,Y,Z).
The expression XY’ + YZ’ + X’Y’Z’ can be reduced to XY’+Z’
XY’ + YZ’ + X’Y’Z
= Y’(X+X’Z’) + YZ
= Y’(X+Z’) + Y
= XY’ + Y’Z’ + YZ’
= XY’ + (Y’+Y)Z’
= XY’ + Z’.
The expression (X+Z’)(Y’+Z’) is a PoS expression which also represents the same function (X,Y,Z).
Question 4 
Which one of the following choices gives the correct values of x and y?
A  x is 1 and y is 1 
B  x is 0 and y is 1 
C  x is 1 and y is 0 
D  x is 0 and y is 0 
C2 checks the bits d1, d3, d4, d6, d7.
C2=1, d1= 1, d3= 1, d4= 0, d6= 0, d7= 1.
The number of 1s is even. So, even parity is used in this problem.
C1 checks the bits d1, d2, d4, d5, d7.
C1=0, d1= 1, d2= 0, d4= 0, d5= x, d7= 1.
As the parity used is even parity, the value of d5 should be 0.
x=d5=0
C8 checks the bitsa d5, d6, d7, d8.
C8=y, d5= x=0, d6= 0, d7= 1, d8= 1.
As the parity used is even parity, the value of C8 should be 0.
C8=y=0.
x=y=0.
Question 5 
A  011, 101, 000 
B  001, 010, 111 
C  001, 010, 000 
D  011, 101, 111 
The truth table will be
RQP 
Rn Qn Pn 
000 
011 
011 
101 
101 
000 
Therefore, the next three states are : 101, 000 and 011
Question 6 
What values of A, B, C and D satisfy the following simultaneous Boolean equations?
A  A = 1, B = 0, C = 0, D = 1 
B  A = 1, B = 1, C = 0, D = 0 
C  A = 1, B = 0, C = 1, D = 1 
D  A = 1, B = 0, C = 0, D = 0 
Question 7 
The number of 1’s in the binary representation of
(3*4096 + 15*256 + 5*16 + 3) are:
A  8 
B  8 
C  10 
D  12 
= (11000000000000)_{2}
15 × 256 = 15 × 2^{8}
= (111100000000)_{2}
5 × 16 = 5 × 2^{4}
= (1010000)_{2}
3 = (11)_{2}
Hence, all binary numbers,
∴ 101's
Question 8 
(a) Implement a circuit having the following output expression using an inverter and NAND gate .
(b) What is the equivalent minimal Boolean expression (in sum of products form)
for the Karnaugh map given below?
A  Theory Explanation. 
Question 9 
(a) An asynchronous serial communication controller that uses a start stop scheme for controlling the serial I/O of a system is programmed for a string of length seven bits, one parity bit (odd parity) and one step bit. The
transmission rate is 1200 bits/second.
(i) What is the complete bit stream that is transmitted for the string ‘0110101’?
(ii) How many such strings can be transmitted per second?
(b) Consider a CRT display that has a text mode display format of 80 × 25 characters with a 9 × 12 character cell. What is the size of the video buffer RAM for the display to be used in monochrome (1 bit per pixel) graphics mode?
A  Theory Explanation. 
Question 10 
A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is _____.
A  5 
A 2^{5}x1 Multiplexer with 5 select lines selects one of the 32(= 2^{5}) registers at a time depending on the selection input.
The content from the selected register will be transferred through the output line to the Accumulator.
Question 11 
If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m + n is ____.
A  1034 
Each output line of the decoder is connected to one of the 1K(= 1024) rows of RAM.
Each row stores 1 Byte.
m=10 and n=1024
Question 12 
Consider the Boolean function z(a,b,c).
Which one of the following minterm lists represents the circuit given above?
A  Z = ∑(0,1,3,7) 
B  Z = ∑(2,4,5,6,7) 
C  Z = ∑(1,4,5,6,7) 
D  Z = ∑(2,3,5) 
Convert a+b’c into canonical form which is sum of minterms.
a + b’c = a(b + b’)(c + c’) + (a + a’)b’c
= abc + abc’ + ab’c + ab’c’ + ab’c + a’b’c
= Σ(7,6,5,4,1)
Question 13 
Consider three registers R1, R2 and R3 that store numbers in IEEE754 single precision floating point format. Assume that R1 and R2 contain the values (in hexadecimal notation) 0x42200000 and 0xC1200000, respectively.
If R3 = R1/R2, what is the value stored in R3?
A  0x40800000 
B  0x83400000 
C  0xC8500000 
D  0xC0800000 
R1 = 1.0100..0 X 2^{132127}
= 1.0100..0 X 2^{5}
= 101.0 X 2^{3}
= 5 X 8
= 40
R2 = (1) x 1.0100..0 X 2^{130127}
= (1) x 1.0100..0 X 2^{3}
= (1) x 101.0 X 2^{1}
= (1) x5 X 2
= 10
R3 = R1/R2
= 4
= (1)x 1.0 x 2^{2}
Sign = 1
Mantissa = 000..0
Exponent = 2+127 = 129
R3 = 1100 0000 1000 000..0
= 0x C 0 8 0 0 0 0 0
Question 14 
A ROM is sued to store the table for multiplication of two 8bit unsigned integers. The size of ROM required is
A  256 × 16 
B  64 K × 8 
C  4 K × 16 
D  64 K × 16 
No. of results possible = 2^{8} × 2^{8} = 2^{16} = 64K
Then total size of ROM = 64K × 16
Question 15 
Both’s algorithm for integer multiplication gives worst performance when the multiplier pattern is
A  101010 …..1010 
B  100000 …..0001 
C  111111 …..1111 
D  011111 …..1110 
Question 16 
Consider the following floating point number representation
The exponent is in 2's complement representation and mantissa is in the sign magnitude representation. The range of the magnitude of the normalized numbers in this representation is
A  0 to 1 
B  0.5 to 1 
C  2^{23} to 0.5 
D  0.5 to (12^{23}) 
Question 17 
Consider the circuit given below which has a four bit binary number b_{3}b_{2}b_{1}b_{0} as input and a five bit binary number d_{4}d_{3}d_{2}d_{1}d_{0} as output. The circuit implements:
A  Binary of Hex conversion

B  Binary to BCD conversion 
C  Binary to grey code conversion 
D  Binary to radix12 conversion 
Whenever, b_{2} = b_{3} = 1, then only 0100, i.e., 4 is added to the given binary number. Lets write all possibilities for b.
Note that the last 4 combinations leads to b_{3} and b_{2} as 1. So, in these combinations only 0010 will be added.
1100 is 12
1101 is 13
1110 is 14
1111 is 15
in binary unsigned number system.
1100 + 0100 = 10000
1101 + 0100 = 10001, and so on.
This is conversion to radix 12.
Question 18 
Consider the circuit in below figure. f implements
A  
B  A + B + C 
C  A ⊕ B ⊕ C 
D  AB + BC + CA 
Question 19 
What is the equivalent Boolean expression in productofsums form for the Karnaugh map given below.
A  
B  
C  
D  
E  None of the above 
Question 20 
A logic network has two data inputs A and B, and two control inputs C_{0} and C_{1}. It implements the function F according to the following table.
Implement the circuit using one 4 to 1 Multiplexer, one 2input Exclusive OR gate, one 2input AND gate, one 2input OR gate and one Inverter.
A  Theory Explanation. 
Question 21 
Consider the synchronous sequential circuit in the below figure.
(a) Draw a state diagram, which is implemented by the circuit. Use the following names for the states corresponding to the values of flipflops as given below.
(b) Given that the initial state of the circuit is S_{4}, identify the set of states, which are not reachable.
A  Theory Explanation. 
Question 22 
Let * be defined as x * y = x' + y. Let z = x * y. Value of z * x is
A  x'+y 
B  x 
C  0 
D  1 
Question 23 
An Nbit carry look ahead adder, where N is a multiple of 4, employs ICs 74181 (4 bit ALU) and 74182 (4 bit carry look ahead generator).
The minimum addition time using the best architecture for this adder is
A  proportional to N 
B  proportional to log N 
C  a constant 
D  None of the above 
Question 24 
Let f(x, y, z) = x' + y'x + xz be a switching function. Which one of the following is valid?
A  
B  xz is a minterm of f 
C  xz is an implicant of f 
D  y is a prime implicant of f 
Question 25 
Given √224)_{r} = 13)_{r}.
The value of the radix r is:
A  10 
B  8 
C  5 
D  6 
Convert r base to decimal.
√2r^{2} + 25 + 4 = r + 3
Take square both sides,
2r^{2} + 2r + 4 = r^{2} + 6r + 9
r^{2}  4r  5 = 0
r^{2}  5r + r  5 = 0
r(r  5) + (r  5) = 0
r = 1, 5
r cannot be 1,
So r = 5 is correct answer.
Question 26 
Consider a logic circuit shown in figure below. The functions f_{1}, f_{2} and f (in canonical sum of products form in decimal notation) are:
f_{1}(w,x,y,z) = ∑8,9,10 f_{2}(w,x,y,z) = ∑7,8,12,13,14,15 f(w,x,y,z) = ∑8,9
The function f_{3} is
A  Σ9,10 
B  Σ9 
C  Σ1,8,9 
D  Σ8,10,15 
Since, f_{1} and f_{2} are in canonical sum of products form, f_{1}⋅f_{2} will only contain their common terms that is f_{1}⋅f_{2} = Σ8.
Now,
Σ8 + f_{3} = Σ8,9
So, f_{3}= Σ9
Question 27 
Choose the correct alternatives (More than one may be correct). Two NAND gates having open collector outputs are tied together as shown in below figure.
The logic function Y, implemented by the circuit is,
A  Y = ABC + DE 
B  
C  Y = ABC . DE 
D  
E  Both (C) and (D) 
Y = ((ABC)' + (DE)')'
Y = ABC . DE
Note: Open gate works as NOR gate.
Question 28 
State whether the following statements are TRUE or FALSE with reason:
RAM is a combinational circuit and PLA is a sequential circuit.A  True 
B  False 
2) PLA is a combination circuit as ROM. PLA is a programmable AND array and a programmable OR array. A PLA with n inputs has fewer than 2n AND gates (otherwise there would be no advantage over a ROM implementation of the same size). A PLA only needs to have enough AND gates to decode as many unique terms as there are in the functions it will implement it.
Question 29 
What happens when a bitstring is XORed with itself ntimes as shown:
[B⊕(B⊕(B⊕(B........ n times)]
A  complements when n is even 
B  complements when n is odd 
C  divides by 2^{n} always 
D  remains unchanged when n is even 
Consider:
B⊕(B⊕B)
= B⊕0
= 0 (if consider n times it remains unchanged)
Question 30 
A multiplexor with a 4 bit data select input is a
A  4:1 multiplexor 
B  2:1 multiplexor 
C  16:1 multiplexor 
D  8:1 multiplexor 
For 4 bit data it selects 2^{4} : 1 = 16: 1 input
Question 31 
The threshold level for logic 1 in the TTL family is
A  any voltage above 2.5 V 
B  any voltage between 0.8 V and 5.0 V 
C  any voltage below 5.0 V 
D  any voltage below V_{cc} but above 2.8 V 
Question 32 
The octal representation of an integer is (342)_{8}. If this were to be treated as an eightbit integer is an 8085 based computer, its decimal equivalent is
A  226 
B  98 
C  76 
D  30 
If this can be treated as 8 bit integer, then the first becomes sign bit i.e., '1' then the number is negative.
8085 uses 2's complement then
⇒ 30
Question 33 
The function represented by the Karnaugh map given below is:
A  A⋅B 
B  AB+BC+CA 
C  
D  None of the above 
Question 34 
Which of the following operations is commutative but not associative?
A  AND 
B  OR 
C  NAND 
D  EXOR 
Question 35 
Suppose the domain set of an attribute consists of signed four digit numbers. What is the percentage of reduction in storage space of this attribute if it is stored as an integer rather than in character form?
A  80% 
B  20% 
C  60% 
D  40% 
We have four digits. So to represent signed 4 digit numbers we need 5 bytes, 4 bytes for four digits and 1 for the sign.
So required memory = 5 bytes.
Now, if we use integer, the largest no. needed to represent is 9999 and this requires 2 bytes of memory for signed representation.
9999 in binary requires 14 bits. So, 2 bits remaining and 1 we can use for sign bit.
So, memory savings,
= 5  2/5 × 100
= 60%
Question 36 
(a) The implication gate shown below, has two inputs (x and y), the output is 1 except when x=1 and y=0. Realize f = x'y + xy' using only four implication gates.
(b) Show that the implication gate is functionally complete.
A  Theory Explanation. 
Question 37 
Design a synchronous counter to go through the following states:
1, 4, 2, 3, 1, 4, 2, 3, 1, 4,...........
A  Theory Explanation. 
Question 38 
?
A  x NAND X 
B  x NOR x 
C  x NAND 1 
D  x NOR 1 
Question 39 
A  
B  
C  
D 
⇒ CD+AD = D(A+C)
Question 40 
Booth’s coding in 8 bits for the decimal number –57 is
A  0 – 100 + 1000 
B  0 – 100 + 100  1 
C  0 – 1 + 100 – 10 + 1 
D  00 – 10 + 100  1 
Question 41 
The maximum gate delay for any output to appear in an array multiplier for multiplying two n bit number is
A  On^{2} 
B  O(n) 
C  O(log n) 
D  O(1) 
Total delay = 1 * 2n  1 = O(2n  1) = n
Question 42 
The number of full and halfadders required to add 16bit numbers is
A  8 halfadders, 8 fulladders 
B  1 halfadder, 15 fulladders 
C  16 halfadders, 0 fulladders 
D  4 halfadders, 12 fulladders 
But for rest of bits we need full address since carry from previous addition has to be included into the addition operation.
So, in total 1 half adder and 15 full adders are required.
Question 43 
Zero has two representations in
A  Sign magnitude 
B  1’s complement 
C  2’s complement 
D  None of the above 
E  Both A and B 
+0 = 0000
0 = 1000
1's complement:
+0 = 0000
0 = 1111
Question 44 
The number 43 in 2’s complement representation is
A  01010101 
B  11010101 
C  00101011 
D  10101011 
Question 45 
The simultaneous equations on the Boolean variables x, y, z and w,
x + y + z = 1 xy = 0 xz + w = 1 xy + = 0
have the following solution for x, y, z and w, respectively.
A  0 1 0 0 
B  1 1 0 1 
C  1 0 1 1 
D  1 0 0 0 
Question 46 
Which function does NOT implement the Karnaugh map given below?
A  (w + x)y 
B  xy + yw 
C  
D  None of the above 
⇒ wy + wz + xy
Question 47 
The following arrangement of masterslave flip flops
has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),
A  1, 0 
B  1, 1 
C  0, 0 
D  0, 1 
When 11 is applied to Jk flip flop it toggles the value of P so op at P will be 1.
Input to D flip flop will be 0(initial value of P) so op at Q will be 0.
Question 48 
Consider the values A = 2.0 x 10^{30}, B = 2.0 x 10^{30}, C = 1.0, and the sequence
X: = A + B Y: = A + C X: = X + C Y: = Y + B
executed on a computer where floatingpoint numbers are represented with 32 bits. The values for X and Y will be
A  X = 1.0, Y = 1.0 
B  X = 1.0, Y = 0.0 
C  X = 0.0, Y = 1.0 
D  X = 0.0, Y = 0.0 
A = 2.0 * 10^{30}, C = 1.0
So, A + C should make the 31^{st} digit to 1, which is surely outside the precision level of A (it is 31^{st} digit and not 31^{st} bit). So, this addition will just return the value of A which will be assigned to Y.
So, Y + B will return 0.0 while X + C will return 1.0.
Question 49 
Design a logic circuit to convert a single digit BCD number to the number modulo six as follows (Do not detect illegal input):
(a) Write the truth table for all bits. Label the input bits I_{1}, I_{2}, …. With I_{1} as the least significant bit. Label the output bits R_{1}, R_{2}, …. With R_{1} as the least significant bit. Use 1 to signify truth.
(b) Draw one circuit for each output bit using, altogether, two twoinput AND gates, one twoinput gate and two NOT gates.
A  Theory Explanation is given below. 
Question 50 
Given the following Karnaugh map, which one of the following represents the minimal SumOfProducts of the map?
A  xy+y'z 
B  wx'y'+xy+xz 
C  w'x+y'z+xy 
D  xz+y 
⇒ y'z + xy