What is the minimum number of NAND gates required to implement a 2-input EXCLUSIVE-OR function without using any other logic gate?

What is the minimum size of ROM required to store the complete truth table of an 8-bit × 8-bit multiplier?

Using a 4-bit 2’s complement arithmetic, which of the following additions will result in an overflow?

1. 1100 
  +1100 
2. 0011 
  +0111 
3. 1111 
  +0111 

The number (123456)₈ is equivalent to

The function AB’C + A’BC + ABC’ + A’B’C + AB’C’ is equivalent to

Consider a parity check code with three data bits and four parity check bits. Three of the code words are 0101011, 1001101 and 1110001. Which of the following are also code words?

1. 0010111             
2. 0110110         
3. 1011010             
4. 0111010 

A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is _____.

If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m + n is ____.

Consider the Boolean function z(a,b,c).

Which one of the following minterm lists represents the circuit given above?

Consider three registers R1, R2 and R3 that store numbers in IEEE-754 single precision floating point format. Assume that R1 and R2 contain the values (in hexadecimal notation) 0x42200000 and 0xC1200000, respectively.

If R3 = R1/R2, what is the value stored in R3?

A ROM is sued to store the table for multiplication of two 8-bit unsigned integers. The size of ROM required is

Both’s algorithm for integer multiplication gives worst performance when the multiplier pattern is

Consider the following floating point number representation

The exponent is in 2’s complement representation and mantissa is in the sign magnitude representation. The range of the magnitude of the normalized numbers in this representation is

Consider the circuit given below which has a four bit binary number b₃b₂b₁b₀ as input and a five bit binary number d₄d₃d₂d₁d₀ as output. The circuit implements:

Consider the circuit in below figure. f implements

What is the equivalent Boolean expression in product-of-sums form for the Karnaugh map given below.

A logic network has two data inputs A and B, and two control inputs C₀ and C₁. It implements the function F according to the following table.

Implement the circuit using one 4 to 1 Multiplexer, one 2-input Exclusive OR gate, one 2-input AND gate, one 2-input OR gate and one Inverter.

Consider the synchronous sequential circuit in the below figure.

(a) Draw a state diagram, which is implemented by the circuit. Use the following names for the states corresponding to the values of flip-flops as given below.

(b) Given that the initial state of the circuit is S₄, identify the set of states, which are not reachable.

Let * be defined as x * y = x’ + y. Let z = x * y. Value of z * x is

An N-bit carry look ahead adder, where N is a multiple of 4, employs ICs 74181 (4 bit ALU) and 74182 (4 bit carry look ahead generator).

The minimum addition time using the best architecture for this adder is

Let f(x, y, z) = x’ + y’x + xz be a switching function. Which one of the following is valid?

Given √224)_r = 13)_r.
The value of the radix r is:

Consider a logic circuit shown in figure below. The functions f₁, f₂ and f (in canonical sum of products form in decimal notation) are:

f1(w,x,y,z) = ∑8,9,10
f2(w,x,y,z) = ∑7,8,12,13,14,15
f(w,x,y,z) = ∑8,9 

The function f₃ is

What happens when a bit-string is XORed with itself n-times as shown:

  [B⊕(B⊕(B⊕(B........ n times)]  

A multiplexor with a 4 bit data select input is a

The threshold level for logic 1 in the TTL family is

The octal representation of an integer is (342)₈. If this were to be treated as an eight-bit integer is an 8085 based computer, its decimal equivalent is

The function represented by the Karnaugh map given below is:

Which of the following operations is commutative but not associative?

Suppose the domain set of an attribute consists of signed four digit numbers. What is the percentage of reduction in storage space of this attribute if  it is stored as an integer rather than in character form?

(a) The implication gate shown below, has two inputs (x and y), the output is 1 except when x=1 and y=0. Realize f = x’y + xy’ using only four implication gates.

(b) Show that the implication gate is functionally complete.

Design a synchronous counter to go through the following states:

  1, 4, 2, 3, 1, 4, 2, 3, 1, 4,........... 

Booth’s coding in 8 bits for the decimal number –57 is

The maximum gate delay for any output to appear in an array multiplier for multiplying two n bit number is

The number of full and half-adders required to add 16-bit numbers is

Zero has two representations in

The number 43 in 2’s complement representation is

The simultaneous equations on the Boolean variables x, y, z and w,

      x + y + z = 1
             xy = 0
         xz + w = 1
      xy +  = 0

have the following solution for x, y, z and w, respectively.

Which function does NOT implement the Karnaugh map given below?

The following arrangement of master-slave flip flops

has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),

Consider the values A = 2.0 x 10³⁰, B = -2.0 x 10³⁰, C = 1.0, and the sequence

             X: = A + B    Y: = A + C
             X: = X + C    Y: = Y + B  

executed on a computer where floating-point numbers are represented with 32 bits. The values for X and Y will be

Design a logic circuit to convert a single digit BCD number to the number modulo six as follows (Do not detect illegal input):
(a) Write the truth table for all bits. Label the input bits I₁, I₂, …. With I₁ as the least significant bit. Label the output bits R₁, R₂, …. With R₁ as the least significant bit. Use 1 to signify truth.
(b) Draw one circuit for each output bit using, altogether, two two-input AND gates, one two-input gate and two NOT gates.

Minimum sum of product expression for f(w,x,y,z) shown in Karnaugh-map below is

The decimal value 0.25

The 2’s complement representation of the decimal value -15 is