Digital-Logic-Design

Question 1
Consider the following representation of a number in IEEE 754 single-precision floating point format with a 
bias of 127.
        S : 1      E : 10000001      F : 11110000000000000000000
Here S, E and F denote the sign, exponent and fraction components of the floating point representation.
The decimal value corresponding to the above representation (rounded to 2 decimal places) is _______
A
-7.75
Question 1 Explanation: 

Sign bit S= 1. The given number is a negative number. 

Biased Exponent E = 27 + 1= 129 

Actual Exponent e = E-127 

= 129- 127

= 2

The decimal value= (-1)s x 1.M x 2e 

= (-1) 1 x 1.1111 x 22 

= - (111.11) 

= - (7 + 0.75) 

= -7.7

Question 2
Let the representation of a number in base 3 be 210. What is the hexadecimal representation of the number?
A
21
B
528
C
D2
D
15
Question 2 Explanation: 

On converting (210)3 in decimal, we will get:=>

 2*32+1*3=2*9+3=2110 

=>(15)16

Question 3
 Consider the following Boolean expression.
A
B
C
D
Question 3 Explanation: 

XY’+Z’ is a minimal SoP expression which represents the function (X,Y,Z).

The expression XY’ + YZ’ + X’Y’Z’ can be reduced to XY’+Z’

XY’ + YZ’ + X’Y’Z

= Y’(X+X’Z’) + YZ

= Y’(X+Z’) + Y

= XY’ + Y’Z’ + YZ’

= XY’ + (Y’+Y)Z’

= XY’ + Z’.

The expression (X+Z’)(Y’+Z’) is a PoS expression which also represents the same function (X,Y,Z).

Question 4

Which one of the following choices gives the correct values of x and y?
A
x is 1 and y is 1
B
x is 0 and y is 1
C
x is 1 and y is 0
D
x is 0 and y is 0
Question 4 Explanation: 

C2 checks the bits d1, d3, d4, d6, d7.

C2=1, d1= 1, d3= 1, d4= 0, d6= 0, d7= 1.

The number of 1s is even. So, even parity is used in this problem.

C1 checks the bits d1, d2, d4, d5, d7.

C1=0, d1= 1, d2= 0, d4= 0, d5= x, d7= 1.

As the parity used is even parity, the value of d5 should be 0.

x=d5=0

 

C8 checks the bitsa d5, d6, d7, d8.

C8=y, d5= x=0, d6= 0, d7= 1, d8= 1.

As the parity used is even parity, the value of C8 should be 0.

C8=y=0.

x=y=0.

Question 5
Consider a 3-bit counter, designed using T flip-flops, as shown below: Assuming the initial state of the counter given by PQR as 000, what are the next three states?
A
011, 101, 000
B
001, 010, 111
C
001, 010, 000
D
011, 101, 111
Question 5 Explanation: 

The truth table will be

RQP

Rn Qn Pn

000

011

011

101

101

000

 

Therefore, the next three states are : 101, 000 and 011

Question 6

What values of A, B, C and D satisfy the following simultaneous Boolean equations?

A
A = 1, B = 0, C = 0, D = 1
B
A = 1, B = 1, C = 0, D = 0
C
A = 1, B = 0, C = 1, D = 1
D
A = 1, B = 0, C = 0, D = 0
Question 6 Explanation: 
For verification, just put up the values and check for AND, OR operations and their outputs.
Question 7

The number of 1’s in the binary representation of
(3*4096 + 15*256 + 5*16 + 3) are:

A
8
B
8
C
10
D
12
Question 7 Explanation: 
3 × 4096 = 3 × 212
= (11000000000000)2
15 × 256 = 15 × 28
= (111100000000)2
5 × 16 = 5 × 24
= (1010000)2
3 = (11)2
Hence, all binary numbers,

∴ 101's
Question 8

(a) Implement a circuit having the following output expression using an inverter and NAND gate .
(b) What is the equivalent minimal Boolean expression (in sum of products form) for the Karnaugh map given below?

A
Theory Explanation.
Question 9

(a) An asynchronous serial communication controller that uses a start stop scheme for controlling the serial I/O of a system is programmed for a string of length seven bits, one parity bit (odd parity) and one step bit. The transmission rate is 1200 bits/second.
(i) What is the complete bit stream that is transmitted for the string ‘0110101’?
(ii) How many such strings can be transmitted per second?

(b) Consider a CRT display that has a text mode display format of 80 × 25 characters with a 9 × 12 character cell. What is the size of the video buffer RAM for the display to be used in monochrome (1 bit per pixel) graphics mode?

A
Theory Explanation.
Question 10

A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is _____.

A
5
Question 10 Explanation: 
Number of registers is 32. Only one register has to be selected at any instant of time.
A 25x1 Multiplexer with 5 select lines selects one of the 32(= 25) registers at a time depending on the selection input.
The content from the selected register will be transferred through the output line to the Accumulator.
Question 11

If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m + n is ____.

A
1034
Question 11 Explanation: 
The size of the decoder required is 10 x 210 i.e., 10 x 1024.
Each output line of the decoder is connected to one of the 1K(= 1024) rows of RAM.
Each row stores 1 Byte.
m=10 and n=1024
Question 12

Consider the Boolean function z(a,b,c).

Which one of the following minterm lists represents the circuit given above?

A
Z = ∑(0,1,3,7)
B
Z = ∑(2,4,5,6,7)
C
Z = ∑(1,4,5,6,7)
D
Z = ∑(2,3,5)
Question 12 Explanation: 
The output of the given circuit is a + b’c.
Convert a+b’c into canonical form which is sum of minterms.
a + b’c = a(b + b’)(c + c’) + (a + a’)b’c
= abc + abc’ + ab’c + ab’c’ + ab’c + a’b’c
= Σ(7,6,5,4,1)
Question 13

Consider three registers R1, R2 and R3 that store numbers in IEEE-754 single precision floating point format. Assume that R1 and R2 contain the values (in hexadecimal notation) 0x42200000 and 0xC1200000, respectively.

If R3 = R1/R2, what is the value stored in R3?

A
0x40800000
B
0x83400000
C
0xC8500000
D
0xC0800000
Question 13 Explanation: 
Given numbers are 0x42200000 and 0xC1200000 which are stored in the registers R1 and R2, respectively.

R1 = 1.0100..0 X 2132-127
= 1.0100..0 X 25
= 101.0 X 23
= 5 X 8
= 40

R2 = (-1) x 1.0100..0 X 2130-127
= (-1) x 1.0100..0 X 23
= (-1) x 101.0 X 21
= (-1) x5 X 2
= -10
R3 = R1/R2
= -4
= (-1)x 1.0 x 22
Sign = 1
Mantissa = 000..0
Exponent = 2+127 = 129

R3 = 1100 0000 1000 000..0
= 0x C 0 8 0 0 0 0 0
Question 14

A ROM is sued to store the table for multiplication of two 8-bit unsigned integers. The size of ROM required is

A
256 × 16
B
64 K × 8
C
4 K × 16
D
64 K × 16
Question 14 Explanation: 
When we multiply the two 8 bit numbers result will reach upto 16 bits. So we require 16 bits for each multiplication output.
No. of results possible = 28 × 28 = 216 = 64K
Then total size of ROM = 64K × 16
Question 15

Both’s algorithm for integer multiplication gives worst performance when the multiplier pattern is

A
101010 …..1010
B
100000 …..0001
C
111111 …..1111
D
011111 …..1110
Question 15 Explanation: 
When the pairs 01 (or) 10 occur frequently in the multiplier. In that case Booth multiplication gives worst performance.
Question 16

Consider the following floating point number representation

The exponent is in 2's complement representation and mantissa is in the sign magnitude representation. The range of the magnitude of the normalized numbers in this representation is

A
0 to 1
B
0.5 to 1
C
2-23 to 0.5
D
0.5 to (1-2-23)
Question 16 Explanation: 
Maximum value of mantissa will be 23, is where a decimal point is assumed before first 1. So the value is 1 - 2-23.
Question 17

Consider the circuit given below which has a four bit binary number b3b2b1b0 as input and a five bit binary number d4d3d2d1d0 as output. The circuit implements:

A
Binary of Hex conversion
B
Binary to BCD conversion
C
Binary to grey code conversion
D
Binary to radix-12 conversion
Question 17 Explanation: 
Here ф means 0.
Whenever, b2 = b3 = 1, then only 0100, i.e., 4 is added to the given binary number. Lets write all possibilities for b.

Note that the last 4 combinations leads to b3 and b2 as 1. So, in these combinations only 0010 will be added.
1100 is 12
1101 is 13
1110 is 14
1111 is 15
in binary unsigned number system.
1100 + 0100 = 10000
1101 + 0100 = 10001, and so on.
This is conversion to radix 12.
Question 18

Consider the circuit in below figure. f implements

A
B
A + B + C
C
A ⊕ B ⊕ C
D
AB + BC + CA
Question 18 Explanation: 
Question 19

What is the equivalent Boolean expression in product-of-sums form for the Karnaugh map given below.

A
B
C
D
E
None of the above
Question 19 Explanation: 
Correct option is

Question 20

A logic network has two data inputs A and B, and two control inputs C0 and C1. It implements the function F according to the following table.

Implement the circuit using one 4 to 1 Multiplexer, one 2-input Exclusive OR gate, one 2-input AND gate, one 2-input OR gate and one Inverter.

A
Theory Explanation.
Question 21

Consider the synchronous sequential circuit in the below figure.

(a) Draw a state diagram, which is implemented by the circuit. Use the following names for the states corresponding to the values of flip-flops as given below.

(b) Given that the initial state of the circuit is S4, identify the set of states, which are not reachable.

A
Theory Explanation.
Question 22

Let * be defined as x * y = x' + y. Let z = x * y. Value of z * x is

A
x'+y
B
x
C
0
D
1
Question 22 Explanation: 
Question 23

An N-bit carry look ahead adder, where N is a multiple of 4, employs ICs 74181 (4 bit ALU) and 74182 (4 bit carry look ahead generator).

The minimum addition time using the best architecture for this adder is

A
proportional to N
B
proportional to log N
C
a constant
D
None of the above
Question 24

Let f(x, y, z) = x' + y'x + xz be a switching function. Which one of the following is valid?

A
B
xz is a minterm of f
C
xz is an implicant of f
D
y is a prime implicant of f
Question 24 Explanation: 
In sum of terms,any term is an implicant because it implies the function. So xz is an implicant and hence 'C' is the answer.
Question 25

Given √224)r = 13)r.
The value of the radix r is:

A
10
B
8
C
5
D
6
Question 25 Explanation: 
(√224)r = (13)r
Convert r base to decimal.
√2r2 + 25 + 4 = r + 3
Take square both sides,
2r2 + 2r + 4 = r2 + 6r + 9
r2 - 4r - 5 = 0
r2 - 5r + r - 5 = 0
r(r - 5) + (r - 5) = 0
r = -1, 5
r cannot be -1,
So r = 5 is correct answer.
Question 26

Consider a logic circuit shown in figure below. The functions f1, f2 and f (in canonical sum of products form in decimal notation) are:

f1(w,x,y,z) = ∑8,9,10
f2(w,x,y,z) = ∑7,8,12,13,14,15
f(w,x,y,z) = ∑8,9 

The function f3 is

A
Σ9,10
B
Σ9
C
Σ1,8,9
D
Σ8,10,15
Question 26 Explanation: 
f = f1⋅f2 + f3
Since, f1 and f2 are in canonical sum of products form, f1⋅f2 will only contain their common terms that is f1⋅f2 = Σ8.
Now,
Σ8 + f3 = Σ8,9
So, f3= Σ9
Question 27

Choose the correct alternatives (More than one may be correct). Two NAND gates having open collector outputs are tied together as shown in below figure.

The logic function Y, implemented by the circuit is,

A
Y = ABC + DE
B
C
Y = ABC . DE
D
E
Both (C) and (D)
Question 27 Explanation: 
There should be bubbled connection between two gates
Y = ((ABC)' + (DE)')'
Y = ABC . DE
Note: Open gate works as NOR gate.
Question 28

State whether the following statements are TRUE or FALSE with reason:

RAM is a combinational circuit and PLA is a sequential circuit.
A
True
B
False
Question 28 Explanation: 
1) RAM is not a combinational circuit. For RAM, the input is the memory location selector and operation (read or write) and another byte (which can be input for write operation or output for read operation), and the output is either a success indicator (for write operation) or the byte at the selected location (for read operation). It does depend on past inputs, or rather, on the past write operations at the selected byte. This is a sequential logic circuit.
2) PLA is a combination circuit as ROM. PLA is a programmable AND array and a programmable OR array. A PLA with n inputs has fewer than 2n AND gates (otherwise there would be no advantage over a ROM implementation of the same size). A PLA only needs to have enough AND gates to decode as many unique terms as there are in the functions it will implement it.
Question 29

What happens when a bit-string is XORed with itself n-times as shown:

  [B⊕(B⊕(B⊕(B........ n times)]  
A
complements when n is even
B
complements when n is odd
C
divides by 2n always
D
remains unchanged when n is even
Question 29 Explanation: 
B⊕(B⊕(B⊕...) n times
Consider:
B⊕(B⊕B)
= B⊕0
= 0 (if consider n times it remains unchanged)
Question 30

A multiplexor with a 4 bit data select input is a

A
4:1 multiplexor
B
2:1 multiplexor
C
16:1 multiplexor
D
8:1 multiplexor
Question 30 Explanation: 
For 'n' bit data it selects 2n : 1 input
For 4 bit data it selects 24 : 1 = 16: 1 input
Question 31

The threshold level for logic 1 in the TTL family is

A
any voltage above 2.5 V
B
any voltage between 0.8 V and 5.0 V
C
any voltage below 5.0 V
D
any voltage below Vcc but above 2.8 V
Question 31 Explanation: 
Voltage is to be below Vcc = 5V but above 2.8V
Question 32

The octal representation of an integer is (342)8. If this were to be treated as an eight-bit integer is an 8085 based computer, its decimal equivalent is

A
226
B
-98
C
76
D
-30
Question 32 Explanation: 
(342)8 = (011 100 010)2 = (1110 0010)2
If this can be treated as 8 bit integer, then the first becomes sign bit i.e., '1' then the number is negative.
8085 uses 2's complement then

⇒ -30
Question 33

The function represented by the Karnaugh map given below is:

A
A⋅B
B
AB+BC+CA
C
D
None of the above
Question 33 Explanation: 
Question 34

Which of the following operations is commutative but not associative?

A
AND
B
OR
C
NAND
D
EXOR
Question 34 Explanation: 
NAND operation is commutative but not associative.
Question 35

Suppose the domain set of an attribute consists of signed four digit numbers. What is the percentage of reduction in storage space of this attribute if  it is stored as an integer rather than in character form?

A
80%
B
20%
C
60%
D
40%
Question 35 Explanation: 
We assume byte addressable memory - nothing smaller than a byte can be used.
We have four digits. So to represent signed 4 digit numbers we need 5 bytes, 4 bytes for four digits and 1 for the sign.
So required memory = 5 bytes.
Now, if we use integer, the largest no. needed to represent is 9999 and this requires 2 bytes of memory for signed representation.
9999 in binary requires 14 bits. So, 2 bits remaining and 1 we can use for sign bit.
So, memory savings,
= 5 - 2/5 × 100
= 60%
Question 36

(a) The implication gate shown below, has two inputs (x and y), the output is 1 except when x=1 and y=0. Realize f = x'y + xy' using only four implication gates.

(b) Show that the implication gate is functionally complete.

A
Theory Explanation.
Question 37

Design a synchronous counter to go through the following states:

  1, 4, 2, 3, 1, 4, 2, 3, 1, 4,........... 

A
Theory Explanation.
Question 38
Which of the following expressions is not equivalent to
?
A
x NAND X
B
x NOR x
C
x NAND 1
D
x NOR 1
Question 38 Explanation: 
Question 39
Which of the following functions implements the Karnaugh map shown below?
A
B
C
D
Question 39 Explanation: 

⇒ CD+AD = D(A+C)
Question 40

Booth’s coding in 8 bits for the decimal number –57 is

A
0 – 100 + 1000
B
0 – 100 + 100 - 1
C
0 – 1 + 100 – 10 + 1
D
00 – 10 + 100 - 1
Question 40 Explanation: 
Question 41

The maximum gate delay for any output to appear in an array multiplier for multiplying two n bit number is

A
On2
B
O(n)
C
O(log n)
D
O(1)
Question 41 Explanation: 
Total no. of gates being used for 'n' bit multiplication in an array multiplier (n*n) = (2n-1)
Total delay = 1 * 2n - 1 = O(2n - 1) = n
Question 42

The number of full and half-adders required to add 16-bit numbers is

A
8 half-adders, 8 full-adders
B
1 half-adder, 15 full-adders
C
16 half-adders, 0 full-adders
D
4 half-adders, 12 full-adders
Question 42 Explanation: 
For Least Significant Bit we do not need a full adder since initially carry is not present.
But for rest of bits we need full address since carry from previous addition has to be included into the addition operation.
So, in total 1 half adder and 15 full adders are required.
Question 43

Zero has two representations in

A
Sign magnitude
B
1’s complement
C
2’s complement
D
None of the above
E
Both A and B
Question 43 Explanation: 
Sign magnitude:
+0 = 0000
-0 = 1000
1's complement:
+0 = 0000
-0 = 1111
Question 44

The number 43 in 2’s complement representation is

A
01010101
B
11010101
C
00101011
D
10101011
Question 44 Explanation: 
Positive integers are represented in its normal binary form while negative numbers are represented in its 2′s complement form. Binary representation of 43 is 00101011.
Question 45

The simultaneous equations on the Boolean variables x, y, z and w,

      x + y + z = 1
             xy = 0
         xz + w = 1
      xy +  = 0

have the following solution for x, y, z and w, respectively.

A
0 1 0 0
B
1 1 0 1
C
1 0 1 1
D
1 0 0 0
Question 45 Explanation: 
Just put the values of each options in the equation and check it.
Question 46

Which function does NOT implement the Karnaugh map given below?

A
(w + x)y
B
xy + yw
C
D
None of the above
Question 46 Explanation: 
Given k-map gives xy + xy + wz

⇒ wy + wz + xy
Question 47

The following arrangement of master-slave flip flops

has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),

A
1, 0
B
1, 1
C
0, 0
D
0, 1
Question 47 Explanation: 
Here clocks are applied to both flip flops simultaneously.
When 11 is applied to Jk flip flop it toggles the value of P so op at P will be 1.
Input to D flip flop will be 0(initial value of P) so op at Q will be 0.
Question 48

Consider the values A = 2.0 x 1030, B = -2.0 x 1030, C = 1.0, and the sequence

             X: = A + B    Y: = A + C
             X: = X + C    Y: = Y + B  

executed on a computer where floating-point numbers are represented with 32 bits. The values for X and Y will be

A
X = 1.0, Y = 1.0
B
X = 1.0, Y = 0.0
C
X = 0.0, Y = 1.0
D
X = 0.0, Y = 0.0
Question 48 Explanation: 
Given: 32 bits representation. So, the maximum precision can be 32 bits (In 32-bit IEEE representation, maximum precision is 24 bits but we take best case here). This means approximately 10 digits.
A = 2.0 * 1030, C = 1.0
So, A + C should make the 31st digit to 1, which is surely outside the precision level of A (it is 31st digit and not 31st bit). So, this addition will just return the value of A which will be assigned to Y.
So, Y + B will return 0.0 while X + C will return 1.0.
Question 49

Design a logic circuit to convert a single digit BCD number to the number modulo six as follows (Do not detect illegal input):
(a) Write the truth table for all bits. Label the input bits I1, I2, …. With I1 as the least significant bit. Label the output bits R1, R2, …. With R1 as the least significant bit. Use 1 to signify truth.
(b) Draw one circuit for each output bit using, altogether, two two-input AND gates, one two-input gate and two NOT gates.

A
Theory Explanation is given below.
Question 50

Given the following Karnaugh map, which one of the following represents the minimal Sum-Of-Products of the map?

A
xy+y'z
B
wx'y'+xy+xz
C
w'x+y'z+xy
D
xz+y
Question 50 Explanation: 

⇒ y'z + xy
There are 50 questions to complete.

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