In 16-bit 2's complement representation, the decimal number -28 is:

Two numbers are chosen independently and uniformly at random from the set {1, 2, ..., 13}. The probability (rounded off to 3 decimal places) that their 4-bit (unsigned) binary representations have the same most significant bit is ______.

Consider Z = X - Y, where X, Y and Z are all in sign-magnitude form. X and Y are each represented in n bits. To avoid overflow, the representation of Z would require a minimum of:

Which one of the following is NOT a valid identity?

What is the minimum number of 2-input NOR gates required to implement a 4-variable function function expressed in sum-of-minterms form as f = Σ(0, 2, 5, 7, 8, 10, 13, 15)? Assume that all the inputs and their complements are available.

Consider three 4-variable functions f₁, f₂ and f₃, which are expressed in sum-of-minterms as

f1 = Σ(0, 2, 5, 8, 14),  f2 = Σ(2, 3, 6, 8, 14, 15),  f3 = Σ(2, 7, 11, 14)

For the following circuit with one AND gate and one XOR gate, the output function f can be expressed as:

Let ⊕ and ⊙ denote the Exclusive OR and Exclusive NOR operations, respectively. Which one of the following is NOT CORRECT?

Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops.

The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is ______

Consider the unsigned 8-bit fixed point binary number representation below,

b₇b₆b₅b₄b₃ ⋅ b₂b₁b₀

where the position of the binary point is between b₃ and b₂ . Assume b₇ is the most significant bit. Some of the decimal numbers listed below cannot be represented exactly in the above representation:

(i) 31.500    (ii) 0.875    (iii) 12.100    (iv) 3.001

Which one of the following statements is true?

Consider the minterm list form of a Boolean function F given below.

F(P, Q, R, S) = Σm(0, 2, 5, 7, 9, 11) + d(3, 8, 10, 12, 14)

Here, m denotes a minterm and d denotes a don’t care term. The number of essential prime implicants of the function F is _______.

The n-bit fixed-point representation of an unsigned real number X uses f bits for the fraction part. Let i = n-f. The range of decimal values for X in this representation is

When two 8-bit numbers A₇...A₀ and B₇...B₀ in 2’s complement representation (with A₀ and B₀ as the least significant bits) are added using a ripple-carry adder, the sum bits obtained are S₇...S₀ and the carry bits are C₇...C₀. An overflow is said to have occurred if

Consider the Karnaugh map given below, where X represents “don’t care” and blank represents 0.

Assume for all inputs , the respective complements are also available. The above logic is implemented using 2-input NOR gates only. The minimum number of gates required is _________.

Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop.

Initially, both Q₀ and Q₁ are set to 1 (before the 1^st clock cycle). The outputs

The representation of the value of a 16-bit unsigned integer X in hexadecimal number system is BCA9. The representation of the value of X in octal number system is

Given the following binary number in 32-bit (single precision) IEEE-754 format:

The decimal value closest to this floating-point number is

Consider a quadratic equation x² - 13x + 36 = 0 with coefficients in a base b. The solutions of this equation in the same base b are x = 5 and x = 6. Then b=________.

If w, x, y, z are Boolean variables, then which one of the following is INCORRECT?

Given f(w,x,y,z) = Σ_m(0,1,2,3,7,8,10) + Σ_d(5,6,11,15), where d represents the don’t-care condition in Karnaugh maps. Which of the following is a minimum product-of-sums (POS) form of f(w,x,y,z)?

Consider a binary code that consists of only four valid code words as given below:

Let the minimum Hamming distance of the code be p and the maximum number of erroneous bits that can be corrected by the code be q. Then the values of p and q are

The next state table of a 2-bit saturating up-counter is given below.

The counter is built as a synchronous sequential circuit using T flip-flops. The expressions for T₁ and T₀ are

Consider the Boolean operator with the following properties:

Then x#y is equivalent to

The 16-bit 2’s complement representation of an integer is 1111 1111 1111 0101; its decimal representation is __________.

We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is __________.

Consider the two cascaded 2-to-1 multiplexers as shown in the figure.

The minimal sum of products form of the output X is

Consider a carry lookahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is __________.

Consider an eight-bit ripple-carry adder for computing the sum of A and B, where A and B are integers represented in 2’s complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is _________.

Let, x₁⊕x₂⊕x₃⊕x₄ = 0 where x₁, x₂, x₃, x₄ are Boolean variables, and ⊕ is the XOR operator. Which one of the following must always be TRUE?

Let X be the number of distinct 16-bit integers in 2’s complement representation. Let Y be the number of distinct 16-bit integers in sign magnitude representation.

Then X-Y is _________.

Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is

The binary operator ≠ is defined by the following truth table

Which one of the following is true about the binary operator ≠?

A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flipflop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.

The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0,……) is ___________.

The number of min-terms after minimizing the following Boolean expression is ______.

      [D′ + AB′ + A′C + AC′D + A′C′D]′    

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ____________.

The total number of prime implicants of the function f(w,x,y,z) = Σ(0, 2, 4, 5, 6, 10) is ______.

Consider the following Boolean expression for F:

   F(P, Q, R, S) = PQ + P'QR + P'QR'S

The minimal sum-of-products form of F is

The base (or radix) of the number system such that the following equation holds is_________.

        312/20 = 13.1     

Consider a 4-to-1 multiplexer with two select lines S1 and S0, given below

The minimal sum-of-products form of the Boolean expression for the output F of the multiplexer is

The dual of a Boolean function F(x₁, x₂, ..., x_n, +, ⋅, '), written as F^D, is the same expression as that of F with + and ⋅ swapped. F is said to be self-dual if F = F^D. The number of self-dual functions with n Boolean variables is

Let k = 2ⁿ. A circuit is built by giving the output of an n-bit binary counter as input to an n-to-2ⁿ bit decoder. This circuit is equivalent to a

Consider the equation (123)₅ = (x8)_y with x and y as unknown. The number of possible solutions is __________.

Consider the following minterm expression for F:

  F(P,Q,R,S) = Σ0,2,5,7,8,10,13,15  

The minterms 2, 7, 8 and 13 are 'do not care' terms. The minimal sum-of-products form for F is:

Consider the following combinational function block involving four Boolean variables x, y, a, b where x, a, b are inputs and y is the output.

f (x, y, a, b)
{
   if (x is 1) y = a;
   else y = b;
}

Which one of the following digital logic blocks is the most suitable for implementing this function?

The above synchronous sequential circuit built using JK flip-flops is initialized with Q2Q1Q0 = 000. The state sequence for this circuit for the next 3 clock cycles is

Let ⊕ denote the Exclusive OR (XOR) operation. Let ‘1’ and ‘0’ denote the binary constants. Consider the following Boolean expression for F over two variables P and Q:

     F(P,Q) = ((1⊕P)⊕(P⊕Q))⊕((P⊕Q)⊕(Q⊕0)) 

The equivalent expression for F is

The smallest integer that can be represented by an 8-bit number in 2’s complement form is

In the following truth table, V = 1 if and only if the input is valid.

What function does the truth table represent?

Which one of the following expressions does NOT represent exclusive NOR of x and y?

The truth table

represents the Boolean function

The decimal value 0.5 in IEEE single precision floating point representation has

The amount of ROM needed to implement a 4 bit multiplier is

What is the minimal form of the karnaugh map shown below? Assume that X denotes a don't care term

The simplified SOP (sum of product) form of the boolean expression

The minimum number of D flip-flops needed to design a mod-258 counter is

Which one of the following circuits is NOT equivalent to a 2-input XNOR (exclusive NOR) gate?

Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.

If all the flip-flops were reset to O at power on, what is the total number of distinct outputs *states) represented by PQR generated by the counter?

Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.

If at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?

The minterm expansion of is

A main memory unit with a capacity of 4 megabytes is built using 1M 1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is

P is a 16-bit signed integer. The 2's complement representation of P is (F87B)₁₆. The 2's complement representation of 8*P is

The Boolean expression for the output 'f' of the multiplexer shown below is

What is the Boolean expression for the output f of the combinational logic circuit of NOR gates given below?

In the sequential circuit shown below,if the initial value of the output Q₁Q₀ is 00,what are the next four values of Q₁Q₀?

(1217)₈ is equivalent to

What is the minimum number of gates required to implement the Boolean function (AB+C) if we have to use only 2-input NOR gates?

How many 32K × 1 RAM chips are needed to provide a memory capacity of 256K-bytes?

In the IEEE floating point representation, the hexadecimal value 0×00000000 corresponds to

In the Karnaugh map shown below, X denotes a don’t care term. What is the minimal form of the function represented by the Karnaugh map?

Let r denote number system radix. The only value(s) of r that satisfy the equation is/are

If P, Q, R are Boolean variables, then

Simplifies to

What is the maximum number of different Boolean functions involving n Boolean variables?

How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates?

Consider the following Boolean function of four variables:

The function is:

Let f(w, x, y, z) = ∑(0, 4, 5, 7, 8, 9, 13, 15). Which of the following expressions are NOT equivalent to f?

(P) x'y'z' + w'xy' + wy'z + xz
(Q) w'y'z' + wx'y' + xz
(R) w'y'z' + wx'y' + xyz + xy'z
(S) x'y'z' + wx'y' + w'y

Define the connective * for the Boolean variables X and Y as: X * Y = XY + X'Y'. Let Z = X * Y.

Consider the following expressions P, Q and R.

P: X = Y⋆Z 
Q: Y = X⋆Z 
R: X⋆Y⋆Z = 1

Which of the following is TRUE?

Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of n variables. What is the minimum size of the multiplexer needed?

In a look-ahead carry generator, the carry generate function G_i and the carry propagate function P_i for inputs A_i and B_i are given by:

Pi = Ai ⨁ Bi and Gi = AiBi

The expressions for the sum bit S_i and the carry bit C_i+1 of the look-ahead carry adder are given by:

Si = Pi ⨁ Ci and Ci+1 = Gi + PiCi , where C0 is the input carry.

Consider a two-level logic implementation of the look-ahead carry generator. Assume that all P_i and G_i are available for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND gates and OR gates needed to implement the look-ahead carry generator for a 4-bit adder with S3, S2, S1, S0 and C4 as its outputs are respectively:

The control signal functions of a 4-bit binary counter are given below (where X is “don’t care”) The counter is connected as follows:

The counter is connected as follows:

Assume that the counter and gate delays are negligible. If the counter starts at 0, then it cycles through the following sequence:

Which of the following is TRUE about formulae in Conjunctive Normal Form?

You are given a free running clock with a duty cycle of 50% and a digital waveform f  which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of f  by 180°?

Consider the circuit above. Which one of the following options correctly represents f(x,y,z)?

Given two three bit numbers a₂a₁a₀ and b₂b₁b₀ and c, the carry in, the function that represents the carry generate function when these two numbers are added is:

Consider the circuit in the diagram. The ⊕ operator represents Ex-OR. The D flipflops are initialized to zeroes (cleared).

The following data: 100110000 is supplied to the “data” terminal in nine clock cycles. After that the values of q2q1q0 are:

Consider a Boolean function f(w,x,y,z). Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors i₁ = 〈w₁, x₁, y₁, z₁〉 and i₂ = 〈w₂, x₂, y₂, z₂〉, we would like the function to remain true as the input changes from vectors i₁ to i₂ (i₁ and i₂ differ in exactly one bit position), without becoming false momentarily. Let f(w,x,y,z) = ∑(5,7,11,12,13,15). Which of the following cube covers of f will ensure that the required property is satisfied?

We consider the addition of two 2’s complement numbers b_n-1b_n-2...b₀ and a_n-1a_n-2…a₀. A binary adder for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by c_n-1c_n-2c₀ and the carry-out by c_out. Which one of the following options correctly identifies the overflow condition?

Consider numbers represented in 4-bit gray code. Let h₃h₂h₁h₀ be the gray code representation of a number n and let g₃g₂g₁g₀ be the gray code of (n+1)(modulo 16) value of the number. Which one of the following functions is correct?

Consider the following circuit.

Which one of the following is TRUE?

The range of integers that can be represented by an n bit 2's complement number system is:

The hexadecimal representation of 657₈ is

The switching expression corresponding to f(A, B, C, D) = Σ (1, 4, 5, 9, 11, 12) is:

Consider the following circuit involving a positive edge triggered D FF.

Consider the following timing diagram. Let A_i represent the logic level on the line A in the i-th clock period.

Let A' represent the complement of A. The correct output sequence on Y over the clock periods 1 through 5 is

Consider the following circuit.

The flip-flops are positive edge triggered D FFs. Each state is designated as a two bit string Q₀Q₁. Let the initial state be 00. The state transition sequence is:

Consider the following floating point format.

Mantissa is a pure fraction in sign-magnitude form.

The decimal number 0.239 × 2¹³ has the following hexadecimal representation (without normalization and rounding off:

Consider the following floating point format.

Mantissa is a pure fraction in sign-magnitude form.

The normalized representation for the above format is specified as follows. The mantissa has an implicit 1 preceding the binary (radix) point. Assume that only 0's are padded in while shifting a field. The normalized representation of the above number (0.239 × 2¹³) is

The Boolean function x'y' + xy + x'y is equivalent to

In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in

If 73_x (in base-x number system) is equal to 54_y (in base-y number system), the possible values of x and y are

What is the result of evaluating the following two expressions using three-digit floating point arithmetic with rounding?

   (113. + -111.) + 7.51
   113. + (-111. + 7.51) 

A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001, ..., 9 by 1001. A combinational circuit is to be designed which takes these 4 bits as input and outputs 1 if the digit ≥ 5, and 0 otherwise. If only AND, OR and NOT gates may be used, what is the minimum number of gates required?

Which are the essential prime implicants of the following Boolean function?

 f(a,b,c) = aȼc + acȼ + bȼc 

Consider a multiplexer with X and Y as data inputs and Z as control input. Z = 0 selects input X, and Z = 1 selects input Y. What are the connections required to realize the 2-variable Boolean function f = T + R, without using any additional hardware?

Consider the partial implementation of a 2-bit counter using T flip-flops following the sequence 0-2-3-1-0, as shown below

To complete the circuit, the input X should be

A 4-bit carry lookahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic.

Let A = 1111 1010 and B = 0000 1010 be two 8-bit 2's complement numbers. Their product in 2's complement is

Assuming all numbers are in 2's complement representation, which of the following numbers is divisible by 11111011?

Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is

The following is a scheme for floating point number representation using 16 bits.

Let s, e, and m be the numbers represented in binary in the sign, exponent, and mantissa fields respectively. Then the floating point number represented is:

What is the maximum difference between two successive real numbers representable in this system?

A 1-input, 2-output synchronous sequential circuit behaves as follows:

Let z_k, n_k denote the number of 0's and 1's respectively in initial k bits of the input (z_k + n_k = k). The circuit outputs 00 until one of the following conditions holds.

•   zk - nk = 2. In this case, the output at the k-th and all subsequent clock ticks is 10.
•   nk - zk = 2. In this case, the output at the k-th and all subsequent clock ticks is 01. 

What is the minimum number of states required in the state transition graph of the above circuit?

The literal count of a boolean expression is the sum of the number of times each literal appears in the expression. For example, the literal count of (xy + xz') is 4. What are the minimum possible literal counts of the product-of-sum and sum-of-product representations respectively of the function given by the following Karnaugh map ? Here, X denotes "don't care"

Consider the ALU shown below.

If the operands are in 2's complement representation, which of the following operations can be performed by suitably setting the control lines K and C₀ only (+ and - denote addition and subtraction respectively)?

Consider the following circuit composed of XOR gates and non-inverting buffers.

The non-inverting buffers have delays δ₁ = 2 ns and δ₂ = 4 ns as shown in the figure. Both XOR gates and all wires have zero delay. Assume that all gate inputs, outputs and wires are stable at logic level 0 at time 0. If the following waveform is applied at input A, how many transition(s) (change of logic levels) occur(s) at B during the interval from 0 to 10 ns?

Minimum sum of product expression for f(w,x,y,z) shown in Karnaugh-map below is

The decimal value 0.25

The 2’s complement representation of the decimal value -15 is

Sign extension is a step in

In 2’s complement addition, overflow

Consider the following logic circuit whose inputs are functions f₁, f₂, f₃ and output is f.

Given that

f1(x,y,z) = ∑(0,1,3,5),
f2(x,y,z) = ∑(6,7) and
f(x,y,z) = ∑(1,4,5),

f₃ is:

Consider the following multiplexor where 10, 11, 12, 13 are four data input lines selected by two address line combinations A1A0 = 00,01,10,11 respectively and f is "the output of the multiplexor. EN is the enable input.

The function f(x,y,z) implemented by the above circuit is:

Let f(A,B) = A' + B. Simplified expression for function f(f(x + y, y)z) is:

(a) Express the function f(x,y,z) = xy' + yz' with only one complement operation and one or more AND/OR operations. Draw the logic circuit implementing the expression obtained, using a single NOT gate and one or more AND/OR gates.

(b) Transform the following logic circuit (without expressing its switching function) into an equivalent logic circuit that employs only 6 NAND gates each with 2-inputs.

Consider the following circuit. A = a₂a₁a₀ and B = b₂b₁b₀ are three bit binary numbers input to the circuit. The output is Z = z₃z₂z₁z₀. R₀, R₁ and R₂ are registers with loading clock shown. The registers are loaded with their input data with the falling edge of a clock pulse (signal CLOCK shown) and appears as shown. The bits of input number A, B and the full adders are as shown in the circuit. Assume Clock period is greater than the settling time of all circuits.

(a) For 8 clocks pulses on the CLOCK terminal and the inputs A, B as shown, obtain the output Z (sequence of 4-bit values of Z). Assume initial contents of R₀, R₁ and R₂ as all zeros.

A=          110 011 111 101 000 000 000 000
B=          101 101 011 110 000 000 000 000
Clock No     1   2   3   4   5   6   7   8 

(b) What does the circuit implement?

Consider the following 32-bit floating-point representation scheme as shown in the formal below. A value is specified by 3 fields, a one bit sign field (with 0 for positive and 1 for negative values), a 24 bit fraction field (with the binary point being at the left end of the fraction bits), and a 7 bit exponent field (in excess-64 signed integer representation, with 16 being the base of exponentiation). The sign bit is the most significant bit.

(a) It is required to represent the decimal value –7.5 as a normalized floating point number in the given format. Derive the values of the various fields. Express your final answer in the hexadecimal.

(b) What is the largest values that can be represented using this format? Express your answer as the nearest power of 10.

Given the following Karnaugh map, which one of the following represents the minimal Sum-Of-Products of the map?

Consider the following circuit with initial state Q₀ = Q₁ = 0. The D Flip-flops are positive edged triggered and have set up times 20 nanosecond and hold times 0.

Consider the following timing diagrams of X and C; the clock period of C <= 40 nanosecond. Which one is the correct plot of Y?

The 2’s complement representation of (-539)₁₀ in hexadecimal is

Consider the circuit shown below. The output of a 2:1 Mux is given by the function (ac' + bc).

Which of the following is true?

Consider the circuit given below with initial state Q₀ = 1, Q₁ = Q₂ = 0. The state of the circuit is given by the value 4Q₂ + 2Q₁ + Q₀

Which one of the following is the correct state sequence of the circuit?

(a) Is the 3-variable function f = ∑(0,1,2,4) its self-dual? Justify your answer.
(b) Give a minimal product-of-sum form of the b output of the following excess-3 to BCD converter.

A sequential circuit takes an input stream of 0’s and 1’s and produces an output stream of 0’s and 1’s. Initially it replicates the input on its output until two consecutive 0’s are encountered on the input. From then onward, it produces an output stream, which is the bit-wise complement of input stream until it encounters two consecutive 1’s, whereupon the process repeats. An example of input and output stream is shown below.

The input stream: 101100 01001011 0 11
The desired output: 101100 10110100 0 11 

J-K master-slave flip-flops are to be used to design the circuit.
(a) Give the state transition diagram.
(b) Give the minimized sum-of-product expression for J and K inputs of one of its state flip-flops.

The number 43 in 2’s complement representation is

The simultaneous equations on the Boolean variables x, y, z and w,

      x + y + z = 1
             xy = 0
         xz + w = 1
      xy +  = 0

have the following solution for x, y, z and w, respectively.

Which function does NOT implement the Karnaugh map given below?

The following arrangement of master-slave flip flops

has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),

Consider the values A = 2.0 x 10³⁰, B = -2.0 x 10³⁰, C = 1.0, and the sequence

             X: = A + B    Y: = A + C
             X: = X + C    Y: = Y + B  

executed on a computer where floating-point numbers are represented with 32 bits. The values for X and Y will be

Design a logic circuit to convert a single digit BCD number to the number modulo six as follows (Do not detect illegal input):
(a) Write the truth table for all bits. Label the input bits I₁, I₂, …. With I₁ as the least significant bit. Label the output bits R₁, R₂, …. With R₁ as the least significant bit. Use 1 to signify truth.
(b) Draw one circuit for each output bit using, altogether, two two-input AND gates, one two-input gate and two NOT gates.

Which of the following expressions is not equivalent to ?

Which of the following functions implements the Karnaugh map shown below?

Booth’s coding in 8 bits for the decimal number –57 is

The maximum gate delay for any output to appear in an array multiplier for multiplying two n bit number is

The number of full and half-adders required to add 16-bit numbers is

Zero has two representations in

What happens when a bit-string is XORed with itself n-times as shown:

  [B⊕(B⊕(B⊕(B........ n times)]  

A multiplexor with a 4 bit data select input is a

The threshold level for logic 1 in the TTL family is