solutions adda
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Question 1 |
What is the minimum number of NAND gates required to implement a 2-input EXCLUSIVE-OR function without using any other logic gate?
A | 3 |
B | 4 |
C | 5 |
D | 6 |
Question 2 |
What is the minimum size of ROM required to store the complete truth table of an 8-bit × 8-bit multiplier?
A | 32 K × 16 bits |
B | 64 K × 16 bits |
C | 16 K × 32 bits |
D | 64 K × 32 bits |
Question 3 |
Using a 4-bit 2’s complement arithmetic, which of the following additions will result in an overflow?
1. 1100 +1100 2. 0011 +0111 3. 1111 +0111
A | 1 only |
B | 2 only |
C | 3 only |
D | 1 and 3 only |
Question 4 |
The number (123456)8Â is equivalent to
A | (A72E)16 and (22130232)4 |
B | (A72E)16 and (22131122)4 |
C | (A73E)16 and (22130232)4 |
D | (A62E)16 and (22120232)4
|
Question 5 |
The function AB’C + A’BC + ABC’ + A’B’C + AB’C’ is equivalent to
A | AC’+ AB + A’C |
B | AB’+ AC’+ A’C |
C | A’B+ AC’+ AB’ |
D | A’B + AC + AB’ |
Question 6 |
Consider a parity check code with three data bits and four parity check bits. Three of the code words are 0101011, 1001101 and 1110001. Which of the following are also code words?
1. 0010111Â Â Â Â Â Â Â Â Â Â Â Â 2. 0110110Â Â Â Â Â Â Â Â 3. 1011010Â Â Â Â Â Â Â Â Â Â Â Â 4. 0111010
A | 1 and 3 |
B | 1, 2 and 3 |
C | 2 and 4 |
D | 1, 2, 3 and 4 |
Question 7 |
A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is _____.
A | 5 |
Question 8 |
If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m + n is ____.
A | 1034 |
Question 9 |
Consider the Boolean function z(a,b,c).
Which one of the following minterm lists represents the circuit given above?
A | Z = ∑(0,1,3,7) |
B | Z = ∑(2,4,5,6,7) |
C | Z = ∑(1,4,5,6,7) |
D | Z = ∑(2,3,5) |
Question 10 |
Consider three registers R1, R2 and R3 that store numbers in IEEE-754 single precision floating point format. Assume that R1 and R2 contain the values (in hexadecimal notation) 0x42200000 and 0xC1200000, respectively.
If R3 = R1/R2, what is the value stored in R3?
A | 0x40800000 |
B | 0x83400000 |
C | 0xC8500000 |
D | 0xC0800000 |
Question 11 |
A | R1 = 1011 and R2 = 1110 |
B | R1 = 1100 and R2 = 1010 |
C | R1 = 0011 and R2 = 0100 |
D | R1 = 1001 and R2 = 1111 |
Question 12 |
A | P is 10:1 multiplexer; Q is 5:1 multiplexer; T is 2:1 multiplexer |
B | P is 10:2 ^10 decoder; Q is 5:2^ 5 decoder; T is 2:1 encoder |
C | P is 10:2^ 10 decoder; Q is 5:2^ 5 decoder; T is 2:1 multiplexer |
D | P is 1:10 de-multiplexer; Q is 1:5 de-multiplexer; T is 2:1 multiplexer |
Question 13 |
A | A + C = 0 |
B | C = A + B |
C | B = 3 C |
D | ( B - C ) > 0 |
Question 14 |
A ROM is sued to store the table for multiplication of two 8-bit unsigned integers. The size of ROM required is
A | 256 × 16 |
B | 64 K × 8 |
C | 4 K × 16 |
D | 64 K × 16 |
Question 15 |
Both’s algorithm for integer multiplication gives worst performance when the multiplier pattern is
A | 101010 …..1010 |
B | 100000 …..0001 |
C | 111111 …..1111 |
D | 011111 …..1110 |
Question 16 |
Consider the following floating point number representation
The exponent is in 2's complement representation and mantissa is in the sign magnitude representation. The range of the magnitude of the normalized numbers in this representation is
A | 0 to 1 |
B | 0.5 to 1 |
C | 2-23 to 0.5 |
D | 0.5 to (1-2-23) |
Question 17 |
Consider the circuit given below which has a four bit binary number b3b2b1b0 as input and a five bit binary number d4d3d2d1d0 as output. The circuit implements:
A | Binary of Hex conversion
|
B | Binary to BCD conversion |
C | Binary to grey code conversion |
D | Binary to radix-12 conversion |
Question 18 |
Consider the circuit in below figure. f implements
A | ![]() |
B | A + B + C |
C | A ⊕ B ⊕ C |
D | AB + BC + CA |
Question 19 |
What is the equivalent Boolean expression in product-of-sums form for the Karnaugh map given below.
A | ![]() |
B | ![]() |
C | ![]() |
D | ![]() |
E | None of the above |
Question 20 |
A logic network has two data inputs A and B, and two control inputs C0 and C1. It implements the function F according to the following table.
Implement the circuit using one 4 to 1 Multiplexer, one 2-input Exclusive OR gate, one 2-input AND gate, one 2-input OR gate and one Inverter.
A | Theory Explanation. |
Question 21 |
Consider the synchronous sequential circuit in the below figure.
(a) Draw a state diagram, which is implemented by the circuit. Use the following names for the states corresponding to the values of flip-flops as given below.
(b) Given that the initial state of the circuit is S4, identify the set of states, which are not reachable.
A | Theory Explanation. |
Question 22 |
Let * be defined as x * y = x' + y. Let z = x * y. Value of z * x is
A | x'+y |
B | x |
C | 0 |
D | 1 |
Question 23 |
An N-bit carry look ahead adder, where N is a multiple of 4, employs ICs 74181 (4 bit ALU) and 74182 (4 bit carry look ahead generator).
The minimum addition time using the best architecture for this adder is
A | proportional to N |
B | proportional to log N |
C | a constant |
D | None of the above |
Question 24 |
Let f(x, y, z) = x' + y'x + xz be a switching function. Which one of the following is valid?
A | ![]() |
B | xz is a minterm of f |
C | xz is an implicant of f |
D | y is a prime implicant of f |
Question 25 |
Given √224)r = 13)r.
The value of the radix r is:
A | 10 |
B | 8 |
C | 5 |
D | 6 |
Question 26 |
Consider a logic circuit shown in figure below. The functions f1, f2 and f (in canonical sum of products form in decimal notation) are:
f1(w,x,y,z) = ∑8,9,10 f2(w,x,y,z) = ∑7,8,12,13,14,15 f(w,x,y,z) = ∑8,9
The function f3 is
A | Σ9,10 |
B | Σ9 |
C | Σ1,8,9 |
D | Σ8,10,15 |
Question 27 |
What happens when a bit-string is XORed with itself n-times as shown:
[B⊕(B⊕(B⊕(B........ n times)]
A | complements when n is even |
B | complements when n is odd |
C | divides by 2n always |
D | remains unchanged when n is even |
Question 28 |
A multiplexor with a 4 bit data select input is a
A | 4:1 multiplexor |
B | 2:1 multiplexor |
C | 16:1 multiplexor |
D | 8:1 multiplexor |
Question 29 |
The threshold level for logic 1 in the TTL family is
A | any voltage above 2.5 V |
B | any voltage between 0.8 V and 5.0 V |
C | any voltage below 5.0 V |
D | any voltage below Vcc but above 2.8 V |
Question 30 |
The octal representation of an integer is (342)8. If this were to be treated as an eight-bit integer is an 8085 based computer, its decimal equivalent is
A | 226 |
B | -98 |
C | 76 |
D | -30 |
Question 31 |
The function represented by the Karnaugh map given below is:
A | Aâ‹…B |
B | AB+BC+CA |
C | ![]() |
D | None of the above |
Question 32 |
Which of the following operations is commutative but not associative?
A | AND |
B | OR |
C | NAND |
D | EXOR |
Question 33 |
Suppose the domain set of an attribute consists of signed four digit numbers. What is the percentage of reduction in storage space of this attribute if it is stored as an integer rather than in character form?
A | 80% |
B | 20% |
C | 60% |
D | 40% |
Question 34 |
(a) The implication gate shown below, has two inputs (x and y), the output is 1 except when x=1 and y=0. Realize f = x'y + xy' using only four implication gates.
(b) Show that the implication gate is functionally complete.
A | Theory Explanation. |
Question 35 |
Design a synchronous counter to go through the following states:
1, 4, 2, 3, 1, 4, 2, 3, 1, 4,...........
A | Theory Explanation. |
Question 36 |
A | x NAND X |
B | x NOR x |
C | x NAND 1 |
D | x NOR 1 |
Question 37 |
A | ![]() |
B | ![]() |
C | ![]() |
D | ![]() |
Question 38 |
Booth’s coding in 8 bits for the decimal number –57 is
A | 0 – 100 + 1000 |
B | 0 – 100 + 100 - 1 |
C | 0 – 1 + 100 – 10 + 1 |
D | 00 – 10 + 100 - 1 |
Question 39 |
The maximum gate delay for any output to appear in an array multiplier for multiplying two n bit number is
A | On2 |
B | O(n) |
C | O(log n) |
D | O(1) |
Question 40 |
The number of full and half-adders required to add 16-bit numbers is
A | 8 half-adders, 8 full-adders |
B | 1 half-adder, 15 full-adders |
C | 16 half-adders, 0 full-adders |
D | 4 half-adders, 12 full-adders |
Question 41 |
Zero has two representations in
A | Sign magnitude |
B | 1’s complement |
C | 2’s complement |
D | None of the above |
E | Both A and B |
Question 42 |
The number 43 in 2’s complement representation is
A | 01010101 |
B | 11010101 |
C | 00101011 |
D | 10101011 |
Question 43 |
The simultaneous equations on the Boolean variables x, y, z and w,
x + y + z = 1 xy = 0 xz + w = 1 xy += 0
have the following solution for x, y, z and w, respectively.
A | 0 1 0 0 |
B | 1 1 0 1 |
C | 1 0 1 1 |
D | 1 0 0 0 |
Question 44 |
Which function does NOT implement the Karnaugh map given below?
A | (w + x)y |
B | xy + yw |
C | ![]() |
D | None of the above |
Question 45 |
The following arrangement of master-slave flip flops
has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),
A | 1, 0 |
B | 1, 1 |
C | 0, 0 |
D | 0, 1 |
Question 46 |
Consider the values A = 2.0 x 1030, B = -2.0 x 1030, C = 1.0, and the sequence
X: = A + B Y: = A + C X: = X + C Y: = Y + B
executed on a computer where floating-point numbers are represented with 32 bits. The values for X and Y will be
A | X = 1.0, Y = 1.0 |
B | X = 1.0, Y = 0.0 |
C | X = 0.0, Y = 1.0 |
D | X = 0.0, Y = 0.0 |
Question 47 |
Design a logic circuit to convert a single digit BCD number to the number modulo six as follows (Do not detect illegal input):
(a) Write the truth table for all bits. Label the input bits I1, I2, …. With I1 as the least significant bit. Label the output bits R1, R2, …. With R1 as the least significant bit. Use 1 to signify truth.
(b) Draw one circuit for each output bit using, altogether, two two-input AND gates, one two-input gate and two NOT gates.
A | Theory Explanation is given below. |
Question 48 |
Minimum sum of product expression for f(w,x,y,z) shown in Karnaugh-map below is
A | xz+y'z |
B | xz'+zx' |
C | x'y+zx' |
D | None of the above |
Question 49 |
The decimal value 0.25
A | is equivalent to the binary value 0.1 |
B | is equivalent to the binary value 0.01 |
C | is equivalent to the binary value 0.00111… |
D | cannot be represented precisely in binary |
Question 50 |
The 2’s complement representation of the decimal value -15 is
A | 1111 |
B | 11111 |
C | 111111 |
D | 10001 |