Digital-Logic-Design

Question 1
A computer uses ternary system instead of the traditional binary system. An n bit string in the binary system will occupy
A
3+n ternary digits
B
2n/3 ternary digits
C
n(log23) ternary digits
D
n(log32 ) ternary digits
       Digital-Logic-Design       Number-Systems       ISRO-2018
Question 1 Explanation: 
→ Binary numbers are maximum 2n-1.
→ But in question they are given ternary numbers, it means 3x-1.
→ Both will take different no. of bits to represent the same number.
3x -1 = 2n -1
3x = 2n
Apply log on both side
x= log3( 2n)
x=n*log32 .
Question 2
In the diagram above, the inverter (NOT gate) and the AND-gates labelled 1 and 2 have delays of 9, 10 and 12 nanoseconds(ns), respectively. Wire delays are negligible. For certain values of a and c, together with the certain transition of b, a glitch (spurious output) is generated for a short time, after which the output assumes its correct value. The duration of the glitch is
A
7ns
B
9ns
C
11ns
D
13ns
       Digital-Logic-Design       Logic-Gates       ISRO-2018
Question 2 Explanation: 
Step-1: Inverter→ NOT gate(b’) will generate 9ns
Step-2: 1st AND gate(ab’) takes 19ns because combining NOT gate(9ns)+extra(10ns)
Step-3: Second AND gate(bc) takes only 12ns because we are not using inverter here.
Step-4: A glitch will take 1st AND gate(ab’) - Second AND gate(bc)
=19-12
=7ns
Question 3
Any set of Boolean operators that is sufficient to represent all Boolean expressions is said to be complete. Which of the following is not complete?
A
{ AND, OR }
B
{ AND, NOT }
C
{ NOT, OR }
D
{ NOR }
       Digital-Logic-Design       Boolean-Algebra       ISRO-2018
Question 3 Explanation: 
→ NOT, AND and OR gates are basic gates
→ NAND and NOR gates are universal gates.
→ With the help of universal gates, we can construct any boolean expressions. These gates are also called functionally complete.
→ AND+NOT=NAND→ Functionally Complete
→ OR+NOT=NOR→ Functionally Complete
→ NOR→ Functionally Complete
→ AND+OR→ Not functionally complete
Question 4
If a variable can take only integral values from 0 to n, where n is an integer, then the variable can be represented as a bit field whose width is (the log in the Solutions are to the base 2, and [log n] means the floor of log n)
A
[log(n)] + 1 bits
B
[log (n-1)) + 1 bits
C
[log (n+1)] + 1 bits
D
None of the above
       Digital-Logic-Design       Number-Systems       ISRO-2018
Question 4 Explanation: 
Question 5
Given √(224)r = 13r the value of radix r is
A
10
B
8
C
6
D
5
       Digital-Logic-Design       Number-Systems       ISRO-2018
Question 5 Explanation: 
√(224)r = 13r
For f(x) to be maximum
f'(x) = 4x - 2 = 0
⇒ x = 1/2
So at x = 1/2, f(x) is an extremum (either maximum or minimum).
f(2) = 2(2)2 - 2(2) + 6 = 10
f(1/2) = 2 × (1/2)2 - 2 × 1/2 + 6 = 5.5
f(0) = 6
So, the maximum value is at x=2 which is 10 as there are no other extremum for the given function.
Question 6
The Boolean expression Y = (A + B' + A'B)C' is given by
A
AC'
B
BC'
C
C'
D
A
       Digital-Logic-Design       Boolean-Algebra       ISRO-2007
Question 6 Explanation: 
Y = (A + B' + A'B)C'
Y = AC' + B'C' + A'BC'
Y = (A + A'B)C' + B'C'
Y = (A + B)C' + B'C'
Y = AC' + BC' + B'C'
Y = AC' + C'(B + B') → B + B' = 1
Y = AC' + C'
Y = C'
Question 7
The circuit shown in the following figure realizes the function
A
(( A + B )’ +C ) ( D’E’ ))
B
(( A + B )’ + C ) ( DE’ ))
C
( A + ( B + C )’ ) ( D’E )
D
( A + B + C’ ) ( D’E’ )
       Digital-Logic-Design       Combinational-Circuit       ISRO-2007
Question 7 Explanation: 
The given function is equivalent to the following expression:
Y = (((A + B)' + C)' + ((D + E)')')'
Y = ((A + B)' + C)')' . (D + E)'
Y = ((A + B)' + C) (D'E')
Question 8
The circuit shown in the given figure is a
A
full adder
B
full subtractor
C
shift register
D
decade counter
       Digital-Logic-Design       Combinational-Circuit       ISRO-2007
Question 8 Explanation: 
The above diagram is full subtractor. The equation is D=X⊕Y⊕Bin and Bout=X'Bin+X'Y+YBin
Question 9
When two numbers are added in excess-3 code and the sum is less than 9, then in order to get the correct answer it is necessary to
A
subtract 0011 from the sum
B
add 0011 to the sum
C
subtract 0110 from the sum
D
add 0110 to the sum
       Digital-Logic-Design       Number-Systems       ISRO-2007
Question 9 Explanation: 
Subtract 0011 if there is no carry otherwise add 0011.
Example:
x+3
y+3
-------
(x+y+6)
Here, sum is excess-6. Hence, subtract 0011 to make it excess-3.
Question 10
The characteristic equation of an SR flip-flop is given by
A
Qn+1 = S + RQn
B
Qn+1= RQn + SQn
C
Qn+1= S + RQn
D
Qn+1 = S + RQn
       Digital-Logic-Design       Sequential-Circuits       ISRO-2007
Question 10 Explanation: 
The characteristic table of an SR flip-flop is:

So, by simplifying using k-maps:
characteristic equation of an SR flip-flop = Qn+1 = S + RQn
Question 11
By using an eight-bit optical encoder the degree of resolution that can be obtained is (approximately)
A
1.8o
B
3.4o
C
2.8o
D
1.4o
       Digital-Logic-Design       Combinational-Circuit       ISRO-2007
Question 11 Explanation: 
An optical encoder is an electromechanical device which has an electrical output in digital form proportional to the angular position of the input shaft.
Optical encoders enable an angular displacement to be converted directly into a digital form.
Encoder resolution is often referred to in bits, which are binary units: a 16 bit resolution rotary encoder will have 65,536 (216) increments per turn, or PPR.
In the given question, 8-bit optical encoder will have 28 increments Resolution = 360/2n = 360/28 = 1.4o
Question 12
The number of digit 1 present in the binary representation of 3 × 512 + 7 × 64 + 5 × 8 + 3
A
8
B
9
C
10
D
12
       Digital-Logic-Design       Number-Systems       ISRO-2007
Question 12 Explanation: 
3 × 512 + 7 × 64 + 5 × 8 + 3
= (2 + 1)× 512 + (4 + 2 + 1)× 64 + (4 + 1)× 8 + 2 + 1
= 1024 + 512 + 64 x 4 + 64 x 2 + 64 + 32 + 8 + 2 + 1
= 1024 + 512 + 256 + 128 + 64 + 32 + 8 + 2 + 1
As 1024 has ten 0’s followed by 1, 512 has nine 0’s followed by 1 and so on..
So, the expression will contain total nine 1’s and will be be represented as 11111101011.
Question 13
0.75 decimal system is equivalent to ____ in octal system
A
0.60
B
0.52
C
0.54
D
0.50
       Digital-Logic-Design       Number-Systems       ISRO-2007
Question 13 Explanation: 
0.75 = (0.110)2
= (0.6)8
Option (A) is correct.
Question 14
In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result in
A
Q = 0, Q’ = 1
B
Q = 1, Q’ = 0
C
Q = 1, Q’ = 1
D
Indeterminate states
       Digital-Logic-Design       Sequential-Circuits       ISRO-2007
Question 14 Explanation: 
Question 15
Ring counter is analogous to
A
Toggle Switch
B
Latch
C
Stepping Switch
D
S-R flip flop
       Digital-Logic-Design       Sequential-Circuits       ISRO-2007
Question 15 Explanation: 
→ A ring counter is a type of counter composed of flip-flops connected into a shift register, with the output of the last flip-flop fed to the input of the first, making a "circular" or "ring" structure.
There are two types of ring counters:
1. A straight ring counter, also known as a one-hot counter, connects the output of the last shift register to the first shift register input and circulates a single one (or zero) bit around the ring.
2. A twisted ring counter, also called switch-tail ring counter, walking ring counter, Johnson counter, or Möbius counter, connects the complement of the output of the last shift register to the input of the first register and circulates a stream of ones followed by zeros around the ring.
Note: Ring counter is analogous to Stepping Switch
Question 16
Digital-Logic-Design
A
0.1 and 5V
B
0.6 and 3.5 V
C
0.9 and 1.75 V
D
-1.75 and 0.9 V
       Digital-Logic-Design       TTL       ISRO-2007
Question 16 Explanation: 
→ TTL high signal would be 5.00 volts exactly, and a TTL low signal 0.00 volts exactly.
→ However, real TTL gate circuits cannot output such perfect voltage levels, and are designed to accept “high” and “low” signals deviating substantially from these ideal values.
Question 17
Consider a computer system that stores a floating-point numbers with 16-bit mantissa and an 8-bit exponent, each in two’s complement. The smallest and largest positive values which can be stored are
A
1 × 10-128 and 215× 1015
B
1 × 10-256 and 215× 10255
C
1 × 10-128 and 215× 10127
D
1 × 10-128and 215– 1 × 10127
       Digital-Logic-Design       Number-Systems       ISRO-2007
Question 17 Explanation: 

According to question 16 bit mantissa and 8 bit Exponent.
Since the mantissa is always 1.xxxxxxxxx in the normalised form, no need to represent the leading 1.
Single Precision: mantissa ===> 1 bit + 15 bits
The largest mantissa value value is 215-1 (one bit meant for sign)
The largest exponent value is 27-1=127
The smallest mantissa value is 0000 0000 0000 0000(one bit is always 1) =1
The Smallest (largest negative) exponent value is 1111 1111 (which is 2’s complement form) 2-8=-128
Question 18
In comparison with static RAM memory, the dynamic RAM memory has
A
lower bit density and higher power consumption
B
higher bit density and higher power consumption
C
lower bit density and lower power consumption
D
higher bit density and lower power consumption
       Digital-Logic-Design       RAM       ISRO-2007
Question 18 Explanation: 
DRAM (Dynamic Random Access Memory)
→ DRAM stands for Dynamic Random Access Memory. It is used in most of the computers. It is the least expensive kind of RAM. It requires an electric current to maintain its electrical state. The electrical charge of DRAM decreases with time that may result in loss of DATA.
→ DRAM is recharged or refreshed again and again to maintain its data. The processor cannot access the data of DRAM when it is being refreshed. That is why it is slow.
SRAM (Static Random Access Memory)
→ SRAM stands for Static Random Access Memory. It can store data without any need of frequent recharging. CPU does not need to wait to access data from SRAM during processing. That is why it is faster than DRAM. It utilizes less power than DRAM.
→ SRAM is more expensive as compared to DRAM. It is normally used to build a very fast memory known as cache memory
Question 19
The Hexadecimal equivalent of 01111100110111100011 is
A
CD73E
B
ABD3F
C
7CDE3
D
FA4CD
       Digital-Logic-Design       Number-Systems       ISRO-2007
Question 19 Explanation: 
Binary number = 0111 1100 1101 1110 0011
7 C D E 3

(7CDE3)16
Question 20
One approach to handling fuzzy logic data might be to design a computer using ternary (base-3) logic so that data could be stored as “true,” “false,” and “unknown.” If each ternary logic element is called a flit, how many blits are required to represent at least 256 different values?
A
4
B
5
C
6
D
7
       Digital-Logic-Design       Number-Systems       ISRO-2007
Question 20 Explanation: 
In binary representation, to represent 256 different values, you need log_2 (256) = 8 bits. Similarly in ternary representation, you would require log_3 (256) which is 5.something. Now rounding off to the upper integer (since number of bits is an integer) and we get 6
Question 21
How many 128×8 bit RAMs are required to design 32K×32 bit RAM?
A
512
B
1024
C
128
D
32
       Digital-Logic-Design       RAM       ISRO-2017 May
Question 21 Explanation: 
Step-1: RAM size required is 32Kx32 bits
= 32x1024x32 bits. [Note: 1k=1024 bytes]

Step-2: Given RAM chip capacity is 128x8 bits
Step-3: Required size/Given size
=(32*1024*32) / (128*8)
=1024
Question 22
What is the minimum number of two-input NAND gates used to perform the function of two input OR gate
A
One
B
Two
C
Three
D
Four
       Digital-Logic-Design       Logic-Gates       ISRO-2017 May
Question 22 Explanation: 
Question 23
When two n-bit binary numbers are added the sum will contain at the most
A
n bits
B
(n+3) bits
C
(n+2) bits
D
(n+1) bits
       Digital-Logic-Design       Number-Systems       ISRO-2017 May
Question 23 Explanation: 
→ When two n-bit binary numbers are added the sum will contain at the most (n+1) bits
Example = 2 Decimal numbers are (7)10 and (7)10
= Equivalent binary numbers are (111)2 + (111)2
= Adding two binary numbers, the final result will be n+1 number (1110)2
Question 24
The 2-input XOR has a high output only when the input values are
A
low
B
high
C
same
D
different
       Digital-Logic-Design       Logic-Gates       ISRO-2017 May
Question 24 Explanation: 
The 2-input XOR(⊕) has a high output only when the input values are different.

Question 25
(1217)8 is equivalent to
A
(1217)16
B
(028F)16
C
(2297)1o
D
(0B17)16
       Digital-Logic-Design       Number-Systems       ISRO-2017 May
Question 25 Explanation: 
(1217)8=(001 010 001 111)2
=(0010 1000 1111)2
=(2 8 F)16
Question 26
Advantages of synchronous sequential circuits over asynchronous one is
A
Lower hardware requirement
B
Better noise immunity
C
Faster operation
D
None of the above
       Digital-Logic-Design       Sequential-Circuits       ISRO-2017 May
Question 26 Explanation: 
Excluded for evaluation.
Question 27
The Boolean theorem AB + A’C + BC = AB + A’C corresponds to
A
(A + B) ∙ (A’ + C) ∙ (B + C) = (A + B) ∙ (A’ + C)
B
AB + A’C + BC = AB + BC
C
AB + A’C + BC = (A + B) ∙ ( A ‘+ C) ∙ (B + C)
D
(A + B) ∙ (A’ + C) ∙ (B + C) = AB + A’C
       Digital-Logic-Design       Boolean-algebra       ISRO CS 2008
Question 27 Explanation: 
(X+Y)*(X+Z)*(Y+Z)=(X+Y)*(X+Z) Consensus Law
XY+XZ+YZ=XY+XZ Consensus Law

For min-term: AB + A'C +BC = AB + A'C
AND for max-term : ( A + B ).( A' + C ).( B + C ) = ( A + B ).(A' + C )
Question 28
In the given network of AND and OR gates, f can be written as
A
X0X1X2 … Xn + X1X2 … Xn + X2X3 … Xn + ⋯ + Xn
B
X0X1 + X2X3 + … Xn-1 Xn
C
X0 + X1 + X2 + … + Xn
D
X0X1 + X3 … Xn−1 + X2X3 + X5 … Xn−1 + ⋯ + Xn−2Xn−1 + Xn
E
None of the above
       Digital-Logic-Design       Boolean-algebra       ISRO CS 2008
Question 28 Explanation: 
(X0X1+X2)X3+X4)X5+⋯+XN
=(X0X1X3+X2X3+X4)X5+⋯+XN

=X0X1X3X5+X2X3X5+X4X5+⋯+XN

=X0X1X3X5⋯XN−1+X2X3X5⋯XN−1+X4X5X7⋯XN−1+⋯+XN
Question 29
If N2 = (7601)8 where N is a positive integer, then the value of N is
A
(241)5
B
(143)6
C
(165)7
D
(39)16
       Digital-Logic-Design       Number-system       ISRO CS 2008
Question 29 Explanation: 
N2 = (7601)8
N2 = 7*8*8*8 + 6*8*8 + 0 + 1*8
N2 = 3969
N = (63)10
Now, (241)5 = 2*5*5 + 4*5 + 1 = 71
Option (A) is incorrect.
(143)6 = 1*6*6 + 4*6 + 3 = 63
Option (B) is correct.
Question 30
If (12x)3 = (123)x then the value of x is
A
3
B
3 or 4
C
2
D
None of these
       Digital-Logic-Design       Number-system       ISRO CS 2008
Question 30 Explanation: 
Given, (12x)3 = (123)x
Since LHS has 3 as the base and RHS has ‘x’ base,
1 * 3*3 + 2 * 3 + x * 1 = 1 * x*x + 2 * x + 3
9 + 6 + x = x2 + 2x + 3
x2 + x - 12 = 0
x2 + 4x - 3x - 12 = 0
x( x + 4 ) - 3(x + 4) = 0
(x + 4)(x - 3) = 0
x = 3 and -4
But, both the values are infeasible.

Alternative explanation :
According to the rules of number systems , the numbers present in a number system should not be greater than the base of the number system.
According to LHS , (12x)3 tells us that the value of x should be less than 3.
According to RHS , (123)x tells us that the value of x should be greater than 3 as largest digit in 123 is 3.
Therefore, any combination is not possible.
Question 31
A computer uses 8 digit mantissa and 2 digit exponent. If a = 0.052 and b = 28E + 11 then b + a – b will
A
result in an overflow error
B
result in an underflow error
C
be 0
D
be 5.28 E + 11
       Digital-Logic-Design       Number-system       ISRO CS 2008
Question 31 Explanation: 

The computer uses 8 digit mantissa and 2 digit exponent:

a = 0.052 We can represent the number in M*E So a= 0.052 = 0.52*10-1

mantissa = 0.52, exponent = −1.

b = 28E+11, We can represent the number in M*E So b = 28E+11= 0.28*1013

mantissa = 0.28, exponent = 13.

To add b+a, Small exponent number, a is shifted

to 13-(-1) = 14 places to right side

a = 0.0000000000000052E+13

From the given data computer uses only 8 digit mantissa, so digits beyond 8th position will be discarded.

So a = 0.00000000E+13 = 0.0 E+13

b + a = (0.28E + 13) + (0.0E + 13 )

= 0.28E + 13

Then b + a - b = (0.28E + 13) - (0.28E + 13)

= 0
Question 32
The Boolean expression ( A + C’)(B’+ C’) simplifies to
A
C’ + AB’
B
C’ (A’ + B)
C
B’C’ + AB’
D
None of these.
       Digital-Logic-Design       Boolean-algebra       ISRO CS 2008
Question 32 Explanation: 

The following expression can be simplified as:

(A + C')(B'+ C')

= AB' + AC' + B'C' + C
'
= AB' + C'(A + B' + 1) // 1 + A = 1

= AB' + C'
Question 33
In the expression A'(A’ + B’) by writing the first term A as A + 0, the expression is best simplified as
A
A + AB
B
AB
C
A'
D
A + B
       Digital-Logic-Design       Boolean-Algebra       ISRO CS 2008
Question 33 Explanation: 

A'(A’ + B’)

This expression can be simplified as:

= A'A' + A'B'

= A' + A'B'

= A'(1 + B') // 1 + B' = 1

= A'
Question 34
The logic operations of two combinational circuits in Figure-I and Figure-II are
A
entirely different
B
identical
C
complementary
D
dual
       Digital-Logic-Design       Sequential-Circuits       ISRO CS 2008
Question 34 Explanation: 

The Two functions are entirely different as:

Figure 1: The logic gates derive the following function:

F1 = ((X + Y')' + X)'

= ((X + Y')')'. X'

= (X + Y'). X'

= XX' + X'Y'

= X'Y'

Figure 2: It is simple AND gate which has 1 input already complimented.

F2 = XY'

So, these two functions are entirely different.
Question 35
The output Y of the given circuit
A
1
B
0
C
X
D
X’
       Digital-Logic-Design       Sequential-Circuits       ISRO CS 2008
Question 35 Explanation: 
The above function is implemented using XOR function, and gives output as 1 only when both the inputs are different. In this function, both the inputs of the first XOR gate are set to 0. Then the output is also 0 and the further two gates are also getting 0 as both their inputs. So, the final output Y is 0.
Question 36
Which of the following is not a valid rule of XOR?
A
0 XOR 0 = 0
B
1 XOR 1 = 1
C
1 XOR 0 = 1
D
B XOR B = 0
       Digital-Logic-Design       Boolean-Algebra       ISRO CS 2008
Question 36 Explanation: 

XOR gate only returns 1 as the output when both inputs are different and in every other case, it returns 0.

So, options (A), (C) and (D) are correct.
Question 37
Which of the following is termed as minimum error code
A
Binary code
B
Gray code
C
Excess 3 code
D
Octal code
       Digital-Logic-Design       Number-system       ISRO CS 2008
Question 37 Explanation: 

Gray codes are less error-prone for mechanical devices that involve making and breaking electrical circuits because they only change in one bit position at a time.

So, they are considered as the minimum error code.
Question 38
Repeated execution of simple computation may cause compounding of
A
round-off errors
B
syntax errors
C
run-time errors
D
logic errors
       Digital-Logic-Design       Compilers-and-Parsers       ISRO CS 2008
Question 38 Explanation: 
→A syntax error in computer science is an error in the syntax of a coding or programming language, entered by a programmer. Syntax errors are caught by a software program called a compiler, and the programmer must fix them before the program is compiled and then run
→A runtime error is a program error that occurs while the program is running.
→A logic error is a bug in a program that causes it to operate incorrectly, but not to terminate abnormally (or crash). A logic error produces unintended or undesired output or other behaviour, although it may not immediately be recognized.
→Roundoff error is the difference between an approximation of a number used in computation and its exact (correct) value. In certain types of computation, roundoff error can be magnified as any initial errors are carried through one or more intermediate steps and repeated execution.
Question 39
How many 2-input multiplexers are required to construct a 2<sup>10<sup>-input multiplexer?
A
1023
B
31
C
10
D
127
       Digital-Logic-Design       Multiplexer       ISRO CS 2008
Question 39 Explanation: 

210 x1 MUX has 210 inputs.
Level-1 has 29 (=512) 2x1 multiplexers which take 2*29 = 210 inputs and produces 512 outputs.
Similarly,
Level-2 has 256 MUX.
Level-3 has 128 MUX.
Level-4 has 64 MUX.
Level-5 has 32 MUX.
Level-6 has 16 MUX.
Level-7 has 8 MUX.
Level-8 has 4 MUX.
Level-9 has 2 MUX.
Level-10 has 1 MUX.
Total number of Multiplexers= 512+256+128+64+32+16+8+4+2+1
=1023
Question 40
The range of integers that can be represented by n bit 2’s complement number system is:
A
-2n-1 to (2n-1 – 1)
B
-(2n-1 – 1)to (2n-1 – 1)
C
-2n-1 to (2n-1 )
D
-(2n-1 + 1)to (2n-1 – 1)
       Digital-Logic-Design       Number-system       ISRO CS 2009
Question 40 Explanation: 
The range of integers that can be represented by n bit 2’s complement number system is -2n-1 to (2n-1 – 1).
Question 41
A processor that has carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two 2’s complement numbers 01001101 and 11101001. After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be
A
1, 1, 0
B
1, 0, 0
C
0, 1, 0
D
1, 0, 1
       Digital-Logic-Design       Number-system       ISRO CS 2009
Question 41 Explanation: 

Question 42
The two numbers given below are multiplied using the Booth’s algorithm Multiplicand: 0101 1010 1110 1110 Multiplier: 0111 0111 1011 1101 How many additions/subtractions are required for the multiplication of the above two numbers?
A
6
B
8
C
10
D
12
       Digital-Logic-Design       Booth\'s-algorithm       ISRO CS 2009
Question 42 Explanation: 

Question 43
The addition of 4-bit, two’s complement, binary numbers 1101 and 0100 results in
A
0001 and an overflow
B
1001 and no overflow
C
0001 and no overflow
D
1001 and an overflow
       Digital-Logic-Design       Number-Systems       ISRO CS 2009
Question 43 Explanation: 
Number one is 0100 (4-Decimal value)
Another number is 1101(-3 is decimal value)
Adding of -3 and 4, the result is 1 and there is no overflow
Question 44
The switching expression corresponding to F(A,B,C,D)= Σ(1,4,5,9,11,12) is:
A
BC’D’ + A’C’D + AB’D
B
ABC’ + ACD + B’C’D
C
ACD’ + A’BC’ + AC’D’
D
A’BD + ACD’ + BCD’
       Digital-Logic-Design       K-Map       ISRO CS 2009
Question 44 Explanation: 
The K-Map for the boolean function of four variables can be drawn as:
Question 45
Consider the following boolean function of four variables, f (w, x, y,z) = Σ(1, 3, 4, 6, 9, 11, 12, 14], the function is
A
Independent of one variable
B
Independent of two variables
C
Independent of three variables
D
Dependent on all variables
       Digital-Logic-Design       Boolean-Function       ISRO CS 2009
Question 45 Explanation: 

w and y are not needed to represent the function f. So f is independent of two variables.
Question 46
The minimum number of NAND gates required to implement the Boolean function A + AB’+ AB’C is equal to
A
0
B
1
C
4
D
7
       Digital-Logic-Design       Boolean-Function       ISRO-2016
Question 46 Explanation: 
A + AB’+ AB’C = A(1+B’+B’C) = A
No GATE is required to implement the function A.
Question 47
The minimum Boolean expression for the following circuit is:
A
AB + AC + BC
B
A + BC
C
A + B
D
A + B + C
       Digital-Logic-Design       Boolean-Expression       ISRO-2016
Question 47 Explanation: 
If the switches are in parallel then use “+”, and if they are serial then use “ ”.
A(B+C) + AB + (A+B)C = AB + AC + AB + AC + BC
= (AB+AB) + (AC+AC) + BC
= AB + AC + BC
Question 48
For a binary half-subtractor having two inputs A and B, the correct set of logical expressions for the outputs D (= A minus B) and X (=borrow) are
A
D = AB + A’B , X = A’B
B
D = A’B + AB’ , X = AB’
C
D = A’B + AB’ , X = A’B
D
D = AB + A’B , X = AB’
       Digital-Logic-Design       Combinational-Circuit       ISRO-2016
Question 48 Explanation: 
The function table for the Half Subtractor is as follows
A-B= D= A’B + AB’
X= A’B
Question 49
Consider the following gate network Which one of the following gates is redundant?
A
Gate No. 1
B
Gate No. 2
C
Gate No. 3
D
Gate No. 4
       Digital-Logic-Design       Logic-Gates       ISRO-2016
Question 49 Explanation: 
W’ + W’Z + Z’XY = W’(1+Z) + Z’XY
= W’ + Z’XY
The term W’Z is redundant which is represented by GATE 2.
Question 50
The dynamic hazard problem occurs in
A
combinational circuit alone
B
sequential circuit only
C
Both (a) and (b)
D
None of the above
       Digital-Logic-Design       Hazards       ISRO-2016
Question 50 Explanation: 
→ A dynamic hazard is the possibility of an output changing more than once as a result of a single input change.
→ Dynamic hazards often occur in larger logic circuits where there are different routes to the output (from the input).
→ If each route has a different delay, then it quickly becomes clear that there is the potential for changing output values that differ from the required / expected output. e.g.
→ A logic circuit is meant to change output state from 1 to 0, but instead changes from 1 to 0 then 1 and finally rests at the correct value 0. This is a dynamic hazard.
→ As a rule, dynamic hazards are more complex to resolve, but note that if all static hazards have been eliminated from a circuit, then dynamic hazards cannot occur.
Question 51
The logic circuit given below converts a binary code y1,y2,y3 into
A
Excess-3 code
B
Gray code
C
BCD code
D
Hamming Code
       Digital-Logic-Design       Number-Systems       ISRO-2016
Question 51 Explanation: 
X1= Y1
X2= Y1⊕ Y2
X3= Y2 ⊕ Y3
Question 52
The circuit given below in the figure below is
A
An oscillating circuit and its output is a square wave
B
The one whose output remains stable in ‘1’ state
C
The one having output remains stable in ‘0’ state
D
has a single pulse of three times propagation delay
       Digital-Logic-Design       Logic-Gates       ISRO-2016
Question 52 Explanation: 
The square wave has alternating amplitudes(0 and 1) with duty cycle 1.
An odd number of cascaded NOT gates produce a square wave.

Note: Duty cycle= Ratio of durations in which the circuit is ON and OFF in a cycle.
Question 53
If 12A7C16 = X8, then the value of X is
A
224174
B
425174
C
6173
D
225174
       Digital-Logic-Design       Number-Systems       ISRO-2016
Question 53 Explanation: 
Given, (12A7C)16 = (0001 0010 1010 0111 1100)2
MAke blocks of 3 bits each from LSB to MSB.
(Note: In the last block append zeros (as MSBs) if number bits is not three)
(000 010 010 101 001 111 100)
Each of the above blocks represents a digit in base 8 and they can be converted to base 8 as shown below.
= (0 2 2 5 1 7 4)8
Question 54
The Excess-3 code is also called
A
Cyclic Redundancy Code
B
Weighted Code
C
Self-Complementing Code
D
Algebraic Code
       Digital-Logic-Design       Number-Systems       ISRO-2016
Question 54 Explanation: 
Excess-3 code is also called Self-Complementing Code. Because 1’s complement of an excess-3 number is equivalent to 9’s complement of the corresponding decimal digit.
→ In excess-3 code, each of the 4-bit numbers represents decimal digit which is 3 less than the actual decimal digit. So the bits have no fixed weight.
Excess-3 code is neither CRC nor Algebraic Code which is used for error detection and/or correction.
Question 55
The simplified SOP (Sum of Product) form the Boolean expression (P + Q’ + R’)(P + Q’ + R)(P + Q + R’)
A
(P’Q + R)
B
(P + Q’R’)
C
(P Q’ + R )
D
(PQ + R)
       Digital-Logic-Design       Boolean-Expression       ISRO-2016
Question 55 Explanation: 
Question 56
Which of the following binary number is the same as its 2’s complement?
A
1010
B
0101
C
1000
D
1001
       Digital-Logic-Design       Number-Systems       ISRO-2016
Question 56 Explanation: 
Hint: Number of bits=4
(Decimal value of maximum 4-bit number +1 )/2= (15+1)/2=8
Question 57
The functional difference between SR flip-flop and JK flip-flop is that
A
JK Flip-flop is faster than SR flip-flop
B
JK flip-flop has a feedback path
C
JK flip-flop accepts both inputs 1
D
None of them
       Digital-Logic-Design       Sequential-Circuits       ISRO-2016
Question 57 Explanation: 
-> JK flip flop accepts input J=K=1. When J=K=1, the state of the flip-flop gets complimented. But it's not a valid input in SR flip-flop.
-> JK flip flop doesn’t have a feedback path.
Question 58
Evaluate (X XOR Y) XOR Y?
A
All 1’s
B
All 0’s
C
X
D
Y
       Digital-Logic-Design       Boolean-Expression       ISRO CS 2011
Question 58 Explanation: 

Question 59
What is the decimal value of the floating-point number C1D00000 (hexadecimal notation)? (Assume 32-bit, single precision floating point IEEE representation)
A
28
B
-15
C
-26
D
-28
       Digital-Logic-Design       Number-Systems       ISRO CS 2011
Question 59 Explanation: 
Floating Point number in Hexadecimal = C1D00000
Floating Point number in Binary = 1100 0001 1101 0000 0000 0000 0000 0000
In 32-bit, single precision floating point IEEE representation, first MSB represents sign of mantissa: 1 is used to represent a negative mantissa and 0 for a positive value of mantissa, next 8 bits are for exponent value and then 23 bits represents mantissa.
Value of exponent = 131-127 = 4
Mantissa = -1.1010000 0000 0000 0000 0000
Floating point number = -1.1010000 0000 0000 0000 0000
Converting the above one into decimal no -(1*20+1*2-1*0*2-2+1*2-2+0* 2-3 +.....)
= -(1+½+⅛)=-13/8
Decimal value =sign*Exponent*mantissa=1*4*-13/8

= -26
Question 60
In Boolean algebra, rule (X+Y)(X+Z) =
A
Y+XZ
B
X+YZ
C
XY+Z
D
XZ+Y
       Digital-Logic-Design       Boolean-Algebra       ISRO CS 2011
Question 60 Explanation: 
in Boolean algebra,
(X+Y)(X+Z) = X + XZ + XY + YZ
= X(1 + Z + Y) + YZ // as (1 + A = A)
= X.1 + YZ
= X + YZ
Question 61
In an RS flip-flop, if the S line (Set line) is set high (1) and the R line (Reset line) is set low (0), then the state of the flip-flop is
A
Set to 1
B
Set to 0
C
No change in state
D
Forbidden
       Digital-Logic-Design       Flip=flops       ISRO CS 2011
Question 61 Explanation: 
Question 62
The output expression of the following gate network is
A
X. Y + X’ Y’
B
X. Y + X. Y
C
X. Y
D
X + Y
       Digital-Logic-Design       Boolean-Function       ISRO CS 2011
Question 62 Explanation: 
AND operation is represented by ‘.’ and OR operation is representation is represented with ‘+’. According to diagram, option (A) is correct
Question 63
Number of chips (128 x 8 RAM) needed to provide a memory capacity of 2048 bytes
A
2
B
4
C
8
D
16
       Digital-Logic-Design       Memory-interfacing       ISRO CS 2011
Question 63 Explanation: 
Given memory capacity is 2048 Bytes RAM memory is 128x8
Number of chips needed are = total memory capacity / RAM memory
= 2048 bytes / 128 x 8 =2048x8/128x8
= 16
Question 64
The hamming distance between the octets of 0xAA and 0x55 is
A
7
B
5
C
8
D
6
       Digital-Logic-Design       Number-system       ISRO CS 2011
Question 64 Explanation: 
→ The Hamming distance between two strings of equal length is the number of positions at which the corresponding symbols are different.
→ In other words, it measures the minimum number of substitutions required to change one string into the other, or the minimum number of errors that could have transformed one string into the other.
→ Given HexaDecimal numbers are 0xAA and 0x55.
Decimal equivalent of 0xAA is 170
Binary form of 0xAA is 1010 1010
Decimal equivalent of 0x55 is 85
Binary form of 0xAA is 0101 0101
The two numbers binary length length is 8.
→ If you observe all the bits of above two binary numbers, both numbers have different bits in all positions.
→ So according to definition , the number of positions at which the corresponding symbols are different which is 8.
Question 65
How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates?
A
7
B
8
C
9
       Digital-Logic-Design       Encpder-decoder       ISRO CS 2011
Question 65 Explanation: 
Step-1: Level-1 has one 3x8 Decoder and Level-2 has eight 3x8 Decoders. Out of 6 inputs 3 inputs given to level-1 and remaining to level 2.
Step-2: Level-2 has total 8*8=64 output lines. Based on the input, the decoder in level-1 enables one of the Decoders in level-2.
Step-3: The enabled decoder in level-2 selects one of the output lines and keeps that line high and remaining lines low.
Question 66
The binary equivalent of the decimal number 42.75 is
A
101010.110
B
100110.101
C
101010.101
D
100110.110
       Digital-Logic-Design       Number-system       ISRO CS 2013
Question 66 Explanation: 
(42.75)10 = (?)2
Question 67
Which logic gate is used to detect overflow in 2’s complement arithmetic?
A
OR gate
B
AND gate
C
NAND gate
D
XOR gate
       Digital-Logic-Design       Boolean-algebra       ISRO CS 2013
Question 67 Explanation: 

Question 68
When two BCD numbers 0x14 and 0x08 are added what is the binary representation of the resultant number?
A
0x22
B
0x1c
C
0x16
D
results in overflow
       Digital-Logic-Design       Number-system       ISRO CS 2013
Question 68 Explanation: 
In the BCD numbering system, a decimal number is separated into four bits for each decimal digit within the number. Each decimal digit is represented by its weighted binary value performing a direct translation of the number. So a 4-bit group represents each displayed decimal digit from 0000 for a zero to 1001 for a nine
Representation of the above two numbers in the 4-bit number format as follows
0x14 = 0001 0100
0x08 = 0000 1000
1. After performing the addition of the two binary numbers , we will get 0001 110
2. The lower value of BCD is 0000 which is 0 and upper value is1001 which is 9 If the four bit result of addition is greater than 9 and if a carry bit is present in the result then it is invalid and we have to add 6 whose binary equivalent is (0110)2 to the result of addition. Then the resultant that we would get will be a valid binary coded number
The result from the BCD addition is greater than 9,So we need to add to “6” to the result.
0001 1100
0000 0110
--------------
0010 0010 (22)
So, the final resultant number is 22
Question 69
The number 1102 in base 3 is equivalent to 123 in which base system?
A
4
B
5
C
6
D
8
       Digital-Logic-Design       Number-system       ISRO CS 2013
Question 69 Explanation: 
Let us consider the base be ‘x’.
(1102)3 = (123) x
= 1x3x3x3 + 1x3x3 + 2 = 1x2 + 2x + 3
= 27 + 9 + 2 = 1x2 + 2x + 3
= x = 5
Question 70
Any set of boolean operators that is sufficient to represent all boolean expressions is said to be complete. Which of the following is not complete?
A
{NOT, OR}
B
{NOR}
C
{AND, OR}
D
{AND, NOT}
       Digital-Logic-Design       Boolean-functions       ISRO CS 2013
Question 70 Explanation: 
→We can implement any logical gates by using NOR & NAND gates (Universal gates ). →We can’t implement universal gates by using only AND and OR gates combination. →We can implement universal gates (NOT,OR), (NOR) and (AND,NOT) gates combination.
Question 71
How many programmable fuses are required in a PLA which takes 16 inputs and gives 8 outputs? It has to use 8 OR gates and 32 AND gates.
A
1032
B
776
C
1284
D
1536
       Digital-Logic-Design       Logic-Gates       ISRO CS 2013
Question 71 Explanation: 
A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. It has 2N AND Gates for N input variables, and for M outputs from PLA, there should be M OR Gates, each with programmable inputs from all of the AND gates.
Total programmable fuses= fuses required by AND gates + fuses required by OR gates
Fuses required by AND gates = 2* no. of inputs * no. of and gates = 2*16*32= 1024 fuses
Fuses required by OR gates = no. Of outputs * no. Of and gates = 8* 32 = 256
Total fuses = 1024+ 256= 1280
Question 72
In a three stage counter, using RS flip flops what will be the value of the counter after giving 9 pulses to its input? Assume that the value of counter before giving any pulses is 1.
A
1
B
2
C
9
D
10
       Digital-Logic-Design       Flip-flops       ISRO CS 2013
Question 72 Explanation: 
→In RS Flip flops, Three bits are used in a three stage counter
→The total number of values are 8 (23)
→The initial value of counter is 1 So the counter will return to initial stage after 8 pulses.
→At Eight stage, again the counter value is 1
→At Ninth stage, the counter value is 2.
Question 73
The most simplified form of the boolean function, X(A,B,C,D) = Σ (7,8,9,10,11,12,13,14,15) (expressed in sum of minterms) is?
A
A + A’BCD
B
AB + CD
C
A + BCD
D
ABC + D
       Digital-Logic-Design       K-Map       ISRO CS 2013
Question 73 Explanation: 
Following is the solution for the boolean function:
Question 74
Two eight bit bytes 1100 0011 and 0100 1100 are added. What are the values of the overflow, carry and zero flags respectively, if the arithmetic unit of the CPU uses 2’s complement form?
A
0, 1,1
B
1, 1,0
C
1, 0,1
D
0, 1,0
       Digital-Logic-Design       Number-system       ISRO CS 2013
Question 74 Explanation: 
Given data,
Question 75
In the standard IEEE 754 single precision floating point representation, there is 1 bit for sign, 23 bits for fraction and 8 bits for exponent. What is the precision in terms of the number of decimal digits?
A
5
B
6
C
7
D
8
       Digital-Logic-Design       Number-Systems       ISRO CS 2014
Question 75 Explanation: 
A floating-point variable can represent a wider range of numbers than a fixed-point variable of the same bit width at the cost of precision. A signed 32-bit integer variable has a maximum value of 231 − 1 = 2,147,483,647, whereas an IEEE 754 32-bit base-2 floating-point variable has a maximum value of (2 − 2−23) × 2127 ≈ 3.402823 × 1038.
In the IEEE 754-2008 standard, the 32-bit base-2 format is officially referred to as binary32; it was called single in IEEE 754-1985. IEEE 754 specifies additional floating-point types, such as 64-bit base-2 double precision and, more recently, base-10 representations.
We can convert the binary into decimal representation by using the following steps
let the number of digits in decimal digits be ‘x’
2-23 = 10-x
After taking log on both sides
log210-x =log2 2-23
-x log210 = -23log22 (The value of log22=1)
-3.322 x = -23 (The value of log210 = 3.321928)
x = 6.92
Question 76
Consider the logic circuit given below:
A
A’C + BC ‘ + CD
B
ABC + C’D
C
AB + BC’ + BD’
D
AB’ + AC’ + C’D
       Digital-Logic-Design       Logic-Gates       ISRO CS 2014
Question 76 Explanation: 
Q = (((CD)’B)'(AB)’)’
Q = ((CD)’B)” + (AB)”
Q = (CD)’B + AB
Q = (C’ + D’)B + AB
Q = C’B + D’B + AB
Q = AB + BC’ + BD’
Question 77
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4 x 6 array, where each chip is 8K x 4 bits ?
A
13
B
15
C
16
D
17
       Digital-Logic-Design       RAM       ISRO CS 2014
Question 77 Explanation: 
From the given data
Each chip size is = 8K x 4 bits = 23 x 210 x 22 == 215 bits = 212 bits
Given chip array = 6 x 4 = 24 ( 24=16 and 25=32)
So the number bits required for the total chips are 5 bits.
So, total number of bits required = 12 + 5 = 17 bits
Question 78
Consider the following sequential circuit

What are the values of Q0 and Q1 after 4 clock cycles if the initial values are ?  
A
11
B
01
C
10
D
00
       Digital-Logic-Design       Sequential-Circuits       ISRO CS 2014
Question 78 Explanation: 
Question 79
Suppose you want to build a memory with 4-byte words with a capacity of 221 bits.
What is the type of decoder required if the memory is built using 2K x 8 RAM chips?
A
5 to 32
B
6 to 64
C
4 to 64
D
7 to 128
       Digital-Logic-Design       Combinational-Circuit       ISRO CS 2014
Question 79 Explanation: 
In digital electronics, a binary decoder is a combinational logic circuit that converts binary information from the n coded inputs to a maximum of 2n unique outputs.
We need to built memory with 4 byte words with a capacity of 221bits
So, number of 4-byte words memory = total number of bits / number of byte words
= 221/(4*bytes)
= 221/(4*8)
=221/32=221/25
= 216 words
Given RAM chips are of size = 2K x 8
Memory to be built using these RAM chips = 216
Required RAM chips = (216 x 32) / (2K x 8) = 32 x 4
So, RAM chips contains 32 rows and each row with 4 columns.
A Decoder is required to select a specific row and multiplexer is required to select a particular column. 5 to 32 Decoder will be required to select the desired row.
Question 80
Consider the logic circuit given below.

The inverter, AND and OR gates have delays of 6, 10 and 11 nanoseconds respectively. Assuming that wire delays are negligible, what is the duration of glitch for Q before it becomes stable?
A
5
B
11
C
16
D
17
       Digital-Logic-Design       Logic-Gates       ISRO CS 2014
Question 80 Explanation: 
In this circuit, inverter and the AND gate will take total 16 nsecs (6 nsecs will be taken by inverter and another 10 nsecs by AND gate) to reach the XOR gate whereas the OR gate will reach to the XOR gate in only 11 nsecs, which will cause a glitch to happen for 5 nsecs.
Question 81
Which of the following is not valid Boolean algebra rule?
A
X.X = X
B
(X + Y).X = X
C
X̄ + XY = Y
D
(X + Y).(X + Z) = X + YZ
       Digital-Logic-Design       Boolean-Algebra       ISRO CS 2014
Question 81 Explanation: 
i) X.X = X
ii) (X + Y).X
= X.X + X.Y
= X + X.Y
= X(1 + Y)
= X
iii) X' + XY
= (X' + X)(X' + Y)
= (1)(X' + Y)
= (X' + Y)
iv) (X + Y).(X + Z)
= X.X + X.Z + X.Y + Y.Z
= X(1 + Z + Y) + Y.Z
= X + Y.Z
Question 82
How many different BCD numbers can be stored in 12 switches? (Assume two position or on-off switches)
A
212
B
212-1
C
1012
D
103
       Digital-Logic-Design       Number-Systems       ISRO CS 2014
Question 82 Explanation: 
Step-1: A binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where each decimal digit is represented by a fixed number of bits, usually four (or) eight.
Step-2: Decimal number 0 can be represented 0000 and 9 can be represented by using 1001.
Step-3: A switch can store maximum 1 bit data that may be either 0 (or) 1. In switch terminology, 0 means “off” and 1 means “on”. With 4 bit we can represent 10 BCD numbers.
Step-4: A BCD digit can be from 0 to 9 (total 10 possibility).
Step-5: Different possible BCD numbers in 12 switches are = 10*10*10
= 1000
= 103
Question 83

Perform the following operation for the binary equivalent of the decimal numbers

(-14)10 + (-15)10

The solution in 8 bit representation is :

A
11100011
B
00011101
C
10011101
D
11110011
       Digital-Logic-Design       Boolean-Algebra       UGC-NET JUNE Paper-2
Question 83 Explanation: 
(-14)10 + (-15)10 = (-29)10

(29)10 = (11101)2
(29)10 in 8-bit representation = (00011101)2

(-29)10 = (00011101)2
Question 84

Simplify the following using K-map :

 F (A, B, C, D) = Σ (0, 1, 2, 8, 9, 12, 13) 
 d (A, B, C, D) = Σ (10, 11, 14, 15) 
d stands for don’t care condition.
A
B
C
D
       Digital-Logic-Design       K-Map       UGC-NET JUNE Paper-2
Question 84 Explanation: 
Question 85
___ number of gates are required to implement the boolean function (AB+C) with using only 2 input NOR gates.
A
2
B
3
C
4
D
5
       Digital-Logic-Design       Nielit Scentist-B [02-12-2018]
Question 85 Explanation: 
NOR is Complement of OR
AB+C
= (A+C)(B+C) ← Distribution of + over
= ((A+C)’+(B+C)’)’
1st NOR- (A+C)’. Let X = (A+C)’
2nd NOR- (B+C)’. Let Y = (B+C)’
3rd NOR- (X+Y)’
Question 86
(A+C’)(B’+C’) simplifies to ______
A
AC’ +B’
B
C(A’+B’)
C
BC’+A
D
AB’+C’
       Digital-Logic-Design       Nielit Scentist-B [02-12-2018]
Question 86 Explanation: 
Distributive law:
x + ( y. z) = (x + y) . (x + z)
Proof:
Question 87
The hexadecimal representation of (632)8 is:
A
19A
B
198
C
29A
D
291
       Digital-Logic-Design       Nielit Scentist-B [02-12-2018]
Question 87 Explanation: 
(632)8 in binary form (110011010)
Group four bits from right to left to convert into Hexadecimal
So first four bits 1010 means A
1001 means 9
1 means 1
Then final value is (19A)
Question 88
In the truth table, f(x,y) represent the boolean function

A
x ↔ y
B
x ⋀ y
C
x V y
D
x → y
       Digital-Logic-Design       Nielit Scentist-B [02-12-2018]
Question 88 Explanation: 
→ The output of a digital logic Exclusive-NOR gate ONLY goes “HIGH” when its two input terminals, A and B are at the “SAME” logic level which can be either at a logic level “1” or at a logic level “0”.
→ In other words, an even number of logic “1’s” on its inputs gives a logic “1” at the output, otherwise is at logic level “0”.
→ This type of gate gives and output “1” when its inputs are “logically equal” or “equivalent” to each other, which is why an Exclusive-NOR gate is sometimes called an Equivalence Gate
Question 89
Minimum ___ full adders and half adders are required by the BCD adder to add two decimal digits.
A
3,2
B
9,4
C
6,5
D
5,2
       Digital-Logic-Design       Nielit Scentist-B [02-12-2018]
Question 89 Explanation: 
→ Each digit is represented by a 4-bit BCD code.
→ To add two 4-bit number, we need 1 Half Adder(to add LSBs) and 3 Full Adders(remaining three bits of both number along with carry bits).
→ To make the resultant Sum as valid BCD sum, we need to add 0110 to the sum.
→ This can be done with 1 Half adder and 2 Full Adder
(Note: LSB bit of 0110 is always zero. So there is no need of ADDER to add LSBs.
→ Here, Half adder is used to add next significant bits).
Total 5 Full Adders and 2 Half Adders are needed
Question 90
A RAM chip has a capacity of 1024 words of 8 bits each (1K x 8). The number of 2 x 4 decoders with enable line needed to construct a 32K x8 RAM from 1K x8 RAM is:
A
4
B
5
C
6
D
7
       Digital-Logic-Design       Nielit Scentist-B [02-12-2018]
Question 90 Explanation: 
→ The capacity of the RAM needed = 16K
→ Capacity of the chips available = 1K
→ No. of address lines = 16K/1K = 16
→ Hence we can use 4×16 decoder for this. But we were only given 2×4 decoders.
→ So, 4 decoders are required in inner level as from one 2×4 decoder we have only 4 output lines whereas we need 16 output lines.
→ To point to these 4 decoders, another 2×4 decoder is required in the outer level.
→ Hence no. of 2×4 decoders to realize the above implementation of RAM = 1+4 = 5
Question 91
A RAM chip has a capacity of 1024 words of 8 bits each (1K x 8). The number of 2 x 4 decoders with enable line needed to construct a 32K x8 RAM from 1K x8 RAM is:
A
4
B
5
C
6
D
7
       Digital-Logic-Design       Nielit Scentist-B [02-12-2018]
Question 91 Explanation: 
→ The capacity of the RAM needed = 16K → Capacity of the chips available = 1K
→ No. of address lines = 16K/1K = 16
→ Hence we can use 4×16 decoder for this. But we were only given 2×4 decoders.
→ So, 4 decoders are required in inner level as from one 2×4 decoder we have only 4 output lines whereas we need 16 output lines.
→ To point to these 4 decoders, another 2×4 decoder is required in the outer level.
→ Hence no. of 2×4 decoders to realize the above implementation of RAM = 1+4 = 5
Question 92

The Circuit is equivalent to:
A
Ex-OR
B
NAND gate
C
OR gate
D
AND gate
       Digital-Logic-Design       Circuits-Output       Nielit Scientist-B IT 4-12-2016
Question 92 Explanation: 
Given circuit diagram consists of NOR gates.
NOR of “A” is A’
NOR of “A” is B’
We can see that (A’ + B’)’ is same as (A.B) , where + represents OR, represents AND and ' represents complement operation. This is a De Morgan’s law.
((A'+B')')'=(AB)'
Where (AB)' is the NAND of AB
Question 93
How many inputs are required in full adder circuit?
A
2
B
3
C
more than two inputs
D
None of the above
       Digital-Logic-Design       Adder       Nielit Scientist-B IT 4-12-2016
Question 93 Explanation: 
● The difference between a half-adder and a full adder is that the full-adder has three inputs and two outputs, whereas half adder has only two inputs and two outputs.
● The first two inputs are A and B and the third input is an input carry as C-IN. When a full-adder logic is designed, you string eight of them together to create a byte-wide adder and cascade the carry bit from one adder to the next.
● Note: Here, answer they are given ambiguous because it takes minimum 3 input line
Question 94
What will be the final output of D flip-Flop if the input string is 0010011100?
A
1
B
0
C
Don't care
D
none of the above
       Digital-Logic-Design       Sequential-Circuits       Nielit Scientist-B IT 4-12-2016
Question 94 Explanation: 
The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock).
That captured value becomes the Q output. At other times, the output Q does not change.
The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line.
Truth Table for the D-type Flip Flop:

Step-1: D flip flop is nothing data flip flop. It will return what we are given in input.
Step-2: In this question, the LSB and MSB are 1. So final output is 1.
Note: Here, we don’t know what order they are given input.
Question 95

Which will be the equation of simplification of the given K-map?
A
AB' + B'CD' + A'B'C'
B
AB' + A'B'D' + A'B'C'
C
B'D' + AB' + B'C'
D
B'D' + A'B'C' + AB'
       Digital-Logic-Design       K-Map       Nielit Scientist-B IT 4-12-2016
Question 95 Explanation: 
From the given K-map,
Last row Mapping gives AB’
In the first row - from the first and first column mapping gives B’C’
In the first row - from the first and last column mapping gives B’D’.
Then the final equation will be AB’+B’C’+B’D’
Question 96
How many flip-flop are needed to divide the input frequency by 64?
A
4
B
5
C
6
D
8
       Digital-Logic-Design       Sequential-Circuits       Nielit Scientist-C 2016 march
Question 96 Explanation: 
Giving an output frequency of 2​ n where “n” is the number of flip flops used in the sequence. 64=26​ .So the number of flip-flop required are 6.
Question 97
The range of the numbers which can be stored in an eight bit register is
A
-128 to +127
B
-128 to +128
C
-999999 + +999999
D
none of these
       Digital-Logic-Design       Number-Systems       Nielit Scientist-C 2016 march
Question 97 Explanation: 
There are 2​ 8​ (256) different possible values for 8 bits. When unsigned, it has possible values ranging from 0 to 255; when signed, it has -128 to 127.
Question 98
The excess 3 code is also called
A
Cyclomatic redundancy code
B
Weighted code
C
Self complementing code
D
algebraic code
       Digital-Logic-Design       Number-Systems       Nielit Scientist-C 2016 march
Question 98 Explanation: 
Excess-3 is a self-complementing code. This is because in Excess-3 code we get the 9's complement of a number by just complementing each bit that means by replacing a '0' by '1' and '1' by '0'
Question 99
Odd parity of word can be conveniently tested by
A
OR gate
B
AND gate
C
NOR gate
D
XOR gate
       Digital-Logic-Design       Logic-Gates       Nielit Scientist-C 2016 march
Question 99 Explanation: 
● The Odd Parity gate and the XOR gate behave identically with two inputs; similarly, the even parity gate and the XNOR gate behave identically.
● But if there are more than two specified inputs, the XOR gate will emit 1 only when there is exactly one 1 input, whereas the Odd Parity gate will emit 1 if there are an odd number of 1 inputs.
● The XNOR gate will emit 1 only when there is ​ not ​ exactly one 1 input, while the Even Parity gate will emit 1 if there are an even number of 1 inputs.
Question 100
If the input J is Connected through K input of J-K, then flip-flop will behave as a
A
D type flip-flop
B
T type flip-flop
C
S-R flip flop
D
Toggle switch
       Digital-Logic-Design       Sequential-Circuits       Nielit Scientist-C 2016 march
Question 100 Explanation: 
If J=K=1,then Q​ n+1​ = (Q​ n​ )​ ’​ , ​ so that the J-K Flip-Flop is converted into a T-type Flip-Flop. This unit changes state with each clock pulse and hence it acts as a toggle switch.
Question 101
To build a mod-19 counter the number of flip-flop required is
A
3
B
5
C
7
D
8
       Digital-Logic-Design       Sequential-Circuits       Nielit Scientist-C 2016 march
Question 101 Explanation: 
For a mod N counter the number of flip flops required is less than or equal to 2 raised to power n where n is a positive integer.
N<= 2​ n
Hence,
For a mod 10 counter, 10< 2​ 4​ . So 4 flip flops are required.
For a mod 16 counter, 16=2​ 4​ . So again 4 flip flops are required.
For a mod 32 counter, 32=2​ 5​ . So 5 flip flops are required.
Question 102
​ If a clock with time period "T" is used with n stage shift register, then output of final stage will be delayed by
A
nT sec
B
(n-1)T sec
C
n/Tsec
D
(2n-1)T sec
       Digital-Logic-Design       Sequential-Circuits       Nielit Scientist-C 2016 march
Question 102 Explanation: 
Number of stages = Number of flip-flops in register= no.of bits that can be stored in register.
The data can be shifted one position towards left or right in each clock.
Consider right shift operation.
Initially, data in LSB position is read or accessed.
After each shift the next significant bit moves to LSB position and the bit in LSB is read.
After n-1 shifts i.e after T(n-1) seconds, the last element moves to LSB position.
Question 103
​ A sequential circuit outputs a ONE when an even number (>0) of one's are input; Otherwise the output is ZERO. The minimum number of states required is
A
0
B
1
C
2
D
3
       Digital-Logic-Design       Sequential-Circuits       Nielit Scientist-C 2016 march
Question 103 Explanation: 
Let S_e and S_o are the two states with S_0 is the initial state(with zero ones).
Question 104

In computers, subtraction is generally carried out by

A
1’s complement
B
10’s complement
C
2’s complement
D
9’s complement
       Digital-Logic-Design       Number-Systems       UGC-NET DEC Paper-2
Question 104 Explanation: 
• In computers, subtraction is generally carried out by 2’s complement.
• In two's-complement representation, positive numbers are simply represented as themselves, and negative numbers are represented by the two's complement of their absolute value.
• In the subtraction there may possibility of negative number as a result.
Question 105

The boolean expression A'⋅B + A⋅B' + A⋅B is equivalent to

A
A+B
B
A⋅B
C
(A+B)'
D
A'⋅B
       Digital-Logic-Design       Boolean-Algebra       UGC-NET DEC Paper-2
Question 105 Explanation: 
Question 106

The relation ≤ and < on a boolean algebra are defined as :

x ≤ y and only if x ∨ y = y
x < y means x ≤ y but x ≠ y
x ≥ y means y ≤ x and
x > y means y < x

Consider the above definitions, which of the following is not true in the boolean algebra ?

    (i) If x ≤ y and y ≤ z, then x ≤ z
    (ii) If x ≤ y and y ≤ x, then x = y
    (iii) If x < y and y < z, then x ≤ y
    (iv) If x < y and y < z, then x < y

Choose the correct answer from the code given below:

Code:
A
(iv) only
B
(iii) only
C
(i) and (ii) only
D
(ii) and (iii) only
       Digital-Logic-Design       Boolean-Algebra       UGC-NET DEC Paper-2
Question 106 Explanation: 
iii) “If x < y and y < z, then x ≤ y” is not true.
Because x < y means x ≤ y but x ≠ y.
ii) If x ≤ y and y ≤ x, then x = y is true
Because
x ≤ y implies x v y = x
y ≤ x implies x v y = y
x v y = x = y
Question 107

Consider the following boolean equations :

(i) wx + w(x + y) + x(x + y)= x + wy
(ii) (wx’(y + xz’) + w’x’)y = x’y

What can you say about the above equations ?

A
Both (i) and (ii) are true
B
(i) is true and (ii) is false
C
Both (i) and (ii) are false
D
(i) is false and (ii) is true
       Digital-Logic-Design       Boolean-Algebra       UGC-NET DEC Paper-2
Question 107 Explanation: 
(i)
wx + w(x + y) + x(x + y)
= (wx + wx) + wy + (x + xy)
= wx + wy + x(1 + y)
= wx + wy + x
= (w + 1)x + wy
= x + wy
(ii)
Question 108

Find the boolean expression for the logic circuit shown below :

(1-NAND gate, 2-NOR gate, 3-NOR gate)

A
AB
B
AB’
C
A’B’
D
A’B
       Digital-Logic-Design       Boolean-Algebra       UGC-NET DEC Paper-2
Question 108 Explanation: 
Question 109

Which of the following statements are true ?

    (i) Every logic network is equivalent to one using just NAND gates or just NOR gates.
    (ii) Boolean expressions and logic networks correspond to labelled acyclic digraphs.
    (iii) No two Boolean algebras with n atoms are isomorphic.
    (iv) Non-zero elements of finite Boolean algebras are not uniquely expressible as joins of atoms.

Choose the correct answers from the code given below :

Code :
A
(i) and (iv) only
B
(i) and (ii) only
C
(i), (ii) and (iii) only
D
(ii), (iii) and (iv) only
       Digital-Logic-Design       Boolean-Algebra       UGC-NET DEC Paper-2
Question 109 Explanation: 
→ A universal logic gate is a logic gate that can be used to construct all other logic gates.
→ NAND and NOR are universal gates, by using these gates we can construct all gates.
→ An atom of a Boolean algebra is an element x such that there exist exactly two elements y satisfying y ≤ x, namely x and 0. A Boolean algebra is said to be atomic when every element is a sup of some set of atoms (the bottom element is always the empty sup).
→ So, the options (iii) and (iv) are false.
Question 110
The digital multiplexer is basically a combination logic circuit to perform the operation
A
AND-AND
B
OR-OR
C
AND-OR
D
OR-AND
       Digital-Logic-Design       Combinational-Circuits       Nielit Scientist-B CS 22-07-2017
Question 110 Explanation: 
The equation for digital multiplexer includes AND and OR operations . For example AB+CD. So here firstly we have to solve AND operation then OR operation.
Question 111
In digital logic, if A B=C, then which one of the following is true?
A
A ⊕ C=B
B
B ⊕ C=A
C
A ⊕ B ⊕ C=0
D
Both A) and B)
       Digital-Logic-Design       Boolean-Algebra       Nielit Scientist-B CS 22-07-2017
Question 111 Explanation: 
Question 112
To make the following circuit a tautology? marked box should be
A
OR gate
B
AND gate
C
NAND gate
D
EX-OR gate
       Digital-Logic-Design       Logic-Gates       Nielit Scientist-B CS 22-07-2017
Question 112 Explanation: 
The output f = (x+x')+(y+y').
Starting derivation using 'f'.
→ (x+x')+(y+y')
→ (x+y)+(x'+y')
→ (Already a known Input)+(x'+y')
So, the unknown input is (x'+y'). This can be made by :-
x and y fed into a NOT gate and then AND gate to become (x'+y').
So the answer is NAND gate.
Question 113
In the following gate network which gate is redundant?
A
Gate no.1
B
Gate no.2
C
Gate no.3
D
Gate no.4
       Digital-Logic-Design       Logic-Gates       Nielit Scientist-B CS 22-07-2017
Question 113 Explanation: 
Before Gate No. 4 being removed

Question 114
The combinational circuit given below is implemented with two NAND gates. To which of the following individual gates is its equivalent?
A
NOT
B
OR
C
AND
D
XOR
       Digital-Logic-Design       Combinational-Circuits       Nielit Scientist-B CS 22-07-2017
Question 114 Explanation: 
[(a.b)'. (a.b)' ]'= ((a.b)')' + ((a.b)')'
=(a.b)+(a.b)
=(a.b)
Question 115
In comparison with static RAM memory, the dynamic RAM memory has
A
Lower bit density and higher power consumption
B
Higher bit density and lower power consumption
C
Lower bit density and lower power consumption
D
None of the option
       Digital-Logic-Design       Combinational-Circuits       Nielit Scientist-B CS 22-07-2017
Question 115 Explanation: 
Dynamic memory uses capacitor for storing information, so it doesn't need constant power but it has higher bit density due to its configuration.
Question 116
The nature of any number i.e., positive or negative is recognized by its:
A
MSB
B
LSB
C
Bits
D
Nibble
       Digital-Logic-Design       Nielit STA [02-12-2018]
Question 116 Explanation: 
This standard offers a way to code a number using 32 bits, and defines three components:
1.The plus/minus sign is represented by one bit, the highest-weighted bit (furthest to the left or MSB)
2.The exponent is encoded using 8 bits immediately after the sign
3.The mantissa (the bits after the decimal point) with the remaining 23 bits
Question 117
The theory of bubbled input OR gate is interchangeable with a bubbled output AND gate is demonstrated and proved by:
A
Karnaugh map
B
DeMorgan’s second theorem
C
The commutative law of addition
D
The associative law of multiplication
       Digital-Logic-Design       Nielit STA [02-12-2018]
Question 117 Explanation: 
Question 118
Which IC is used for the implementation of 1 to 16 DEMUX?
A
IC 74154
B
IC 74155
C
IC 74139
D
IC 74138
       Digital-Logic-Design       Nielit STA [02-12-2018]
Question 118 Explanation: 
Demultiplexer IC packages available are the TTL 74LS138 1 to 8-output demultiplexer, the TTL 74LS139 Dual 1-to-4 output demultiplexer or the CMOS CD4514 1-to-16 output demultiplexer.
Another type of demultiplexer is the 24-pin, 74LS154 which is a 4-bit to 16-line demultiplexer/decoder.
Question 119
Which of the following logic expression is incorrect?
A
1 ⊕ 0=1
B
1 ⊕ 1 ⊕ 0=1
C
1 ⊕ 1 ⊕ 1=1
D
1 ⊕ 1 =0
       Digital-Logic-Design       Boolean-Algebra       Nielit Scientist-B CS 2016 march
Question 119 Explanation: 
This ​ ⊕ ​ symbol is nothing but Ex-OR

Option A: Here, ​ 1 ⊕ 0=1 true according to truth table.
Option B: 1⊕1=0⊕0=0 false
Option C: 1 ⊕ 1=0 ⊕ 1=1 true
Option D: 1 ⊕ 1 =0 true.
Question 120
In which of the following adder circuits, the carry look ripple delay is eliminated?
A
Half Adder
B
Full Adder
C
Parallel adder
D
Carry-Look-Ahead adder
       Digital-Logic-Design       Adder       Nielit Scientist-B CS 2016 march
Question 120 Explanation: 
A carry-lookahead adder (CLA) or fast adder is a type of adder used in digital logic. A carry-lookahead adder improves speed by reducing the amount of time required to determine carry bits. It can be contrasted with the simpler, but usually slower, ripple-carry adder (RCA), for which the carry bit is calculated alongside the sum bit, and each bit must wait until the previous carry bit have been calculated to begin calculating its own result and carry bits. The carry-lookahead adder calculates one or more carry bits before the sum, which reduces the wait time to calculate the result of the larger-value bits of the adder.
Question 121
The output of a sequential circuit depends on
A
presents inputs only
B
past inputs only
C
both present and past inputs
D
present outputs only
       Digital-Logic-Design       Sequential-Circuits       Nielit Scientist-B CS 2016 march
Question 121 Explanation: 
In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on the sequence of past inputs, the input history as well. This is in contrast to combinational logic, whose output is a function of only the present input.
Question 122
In a ripple counter using edge triggered JK flip-flops, the pulse input is applied to the
A
clock input of all flip-flops
B
clock input of one flip flops
C
J and K inputs of all flip flops
D
J and K inputs of one flip-flop
       Digital-Logic-Design       Sequential-Circuits       Nielit Scientist-B CS 2016 march
Question 122 Explanation: 
In a ripple counter using edge triggered JK flip-flops, the pulse input is applied to the clock input of one flip flops
Question 123
A decimal number has 30 digits. Approximately, how many digits would the binary representation have?
A
30
B
60
C
90
D
120
       Digital-Logic-Design       Number-Systems       Nielit Scientist-B CS 2016 march
Question 123 Explanation: 
Here, 30 digits numbers means 123....30. 10​30​ -1=1000000000000000000000000000000-1=999999999999999999999999999999
Therefore, it takes approximately above 90 binary numbers. So, 120 is correct answer.
Question 124
The result of the subtraction FD​16 - ​8816​ is
A
75​ 16
B
65 16
C
5E 16
D
10 16
       Digital-Logic-Design       Number-Systems       Nielit Scientist-B CS 2016 march
Question 124 Explanation: 
Step-1: Convert Hexadecimal numbers into decimal numbers.
(FD)​ 16<​/sub> = (253)​ 10
(88)​ 16<​/sub> = (136)​ 10
Step-2: Perform subtraction 253-136=(117)​ 10
Step-3: Convert (117)​ 10 ​ =(75)​ 16
Question 125
How many RAM chips of size (256K x 1 bit) are required to build 1M Byte memory?
A
8
B
10
C
24
D
32
       Digital-Logic-Design       Memory-Interfacing       Nielit Scientist-B CS 2016 march
Question 125 Explanation: 
1 MB = 1024 KB = (1024*8) bits
New RAM would be (1024*8) / (256*1) = 32 .
→ 32 RAM chips of size 256 k x 1 bit are required to build 1 MB of memory.
Question 126
Disadvantage of dynamic RAM over static RAM is
A
Higher power consumptions
B
Variable speed
C
need to refresh the capacitor charge every once in two milliseconds
D
higher bit density
       Digital-Logic-Design       RAM       Nielit Scientist-B CS 2016 march
Question 126 Explanation: 
→ Dynamic random access memory, implies, this form of memory technology is a type of random access memory. It stores each bit of data on a small capacitor within the memory cell. The capacitor can be either charged or discharged and this provides the two states, "1" or "0" for the cell.
→ Since the charge within the capacitor leaks, it is necessary to refresh each memory cell periodically. This refresh requirement gives rise to the term dynamic - static memories do not have a need to be refreshed.
Question 127
Which of the following circuit can be used as parallel to serial converter?
A
Multiplexer
B
Demultiplexer
C
Decoder
D
Digital Counter
       Digital-Logic-Design       Combinational-Circuits       NieLit STA 2016 March 2016
Question 127 Explanation: 
In multiplexer, different inputs are inserted parallely and then it gives one output which is in serial form.
Question 128
The number of full and half adders required to add 16-bit numbers is
A
8 half adders, 8 full adders
B
1 half adders, 5 full adders
C
16 half adders, 0 full adders
D
4 half adders, 12 full adders
       Digital-Logic-Design       Adder       NieLit STA 2016 March 2016
Question 128 Explanation: 
One half adder can add the least significant bit of the two numbers whereas full adders are required to add the remaining 15 bits as they all involve adding carries.
Question 129
Which of the following expression is not equivalent to ~x?
A
x NAND x
B
x NOR x
C
x NAND 1
D
X NOR 1
       Digital-Logic-Design       Adder       NieLit STA 2016 March 2016
Question 129 Explanation: 
Question 130
Which one of the following set of gates are best suited for parity checking and parity generation
A
AND,OR,NOT gates
B
EX-NOR or EX-OR gates
C
AND gates
D
NOR gates
       Digital-Logic-Design       Logic-Gates       NieLit STA 2016 March 2016
Question 130 Explanation: 
Parity generation : EXNOR
The XNOR gate will emit 1 only when there is not exactly one 1 input.
This feature can be used for parity generation.
Suppose A wants to send 1001. XNOR gate will give parity as 0.
But if A sends 1000 XNOR gate gives 1 as parity
Parity check: EXOR
B receives: 10010
B computes parity: 1+0+0+1+0 (mod 2) = 0
Question 131
​ In computers, subtraction is generally carried out by
A
1’s complement
B
10’s complement
C
2’s complement
D
9’s complement
       Digital-Logic-Design       Number-System       UGC NET CS 2018-DEC Paper-2
Question 131 Explanation: 
● In computers, subtraction is generally carried out by 2’s complement.
● In two's-complement representation, positive numbers are simply represented as themselves, and negative numbers are represented by the two's complement of their absolute value;
● In the subtraction there may possibility of negative number as a result.
Question 132
​ The boolean expression A’⋅B+A.B’+A.B is equivalent to
A
A+B
B
A.B
C
(A+B)’
D
A’.B
       Digital-Logic-Design       Boolean-aLGEBRA       UGC NET CS 2018-DEC Paper-2
Question 132 Explanation: 
Question 133
The relation​ ​ ≤ and < on a boolean algebra are defined as :
x ≤ y and only if x ∨ y = y
x < y means x ≤ y but x ≠ y
x ≥ y means y ≤ x and
x > y means y <x
Consider the above definitions, which of the following is not true in the boolean algebra ?
(i)If x ≤ y and y ≤ z, then x ≤ z
(ii)If x ≤ y and y ≤ x, then x=y
(iii)If x < y and y < z, then x ≤ y
(iv)If x < y and y < z, then x < y
A
(iv) only
B
(iii) only
C
(i) and (ii) only
D
(ii) and (iii) only
       Digital-Logic-Design       Boolean-Algebra       UGC NET CS 2018-DEC Paper-2
Question 133 Explanation: 
iii) “If x < y and y < z, then x ≤ y” is not true.
Because x < y means x ≤ y but x ≠ y.
ii)If x ≤ y and y ≤ x, then x=y is true
Because
x ≤ y implies x v y =x
y ≤ x implies x v y = y
X v y = x = y
Note: From the given definitions, x In option 3, the condition x≠y is missing.
Key point: y < z has nothing to do with x ≤ y. So, we are ignoring.
Question 134
Consider the following boolean equations :
(i). ​ wx + w(x + y) + x(x + y)=x+wy
(ii). (wx’(y+xz’)+w’x’)y=x’y
What can you say about the above equations ?
A
Both (i) and (ii) are true
B
(i) is true and (ii) is false
C
Both (i) and (ii) are false
D
(i) is false and (ii) is true
       Digital-Logic-Design       Boolean-Expression       UGC NET CS 2018-DEC Paper-2
Question 134 Explanation: 
(i) wx + w(x + y) + x(x + y)
= (wx + wx) + wy + (x + xy)
= wx + wy + x(1 + y)
= wx + wy + x
= (w + 1)x + wy
= x + wy
Question 135
​Find the boolean expression for the logic circuit shown below :
(1-NAND gate, 2-NOR gate, 3-NOR gate)
A
AB
B
AB’
C
A’B’
D
A’B
       Digital-Logic-Design       Boolean-Expression       UGC NET CS 2018-DEC Paper-2
Question 135 Explanation: 
Question 136
The decimal floating point number -40.1 represented using IEEE-754 32-bit representation and written in hexadecimal form is
A
0xC2206000
B
0xC2006666
C
0xC2006000
D
0xC2206666
       Digital-Logic-Design       Number-Systems       UGC NET CS 2018-DEC Paper-2
Question 136 Explanation: 
1. Fraction part can be converted into binary form by multiplying it with 2 and taking non fractional part of the product. Take fractional part and multiply again as explained above.
0.1 x 2= 0.2 → 0
0.2 x 2= 0.4 → 0
0.4 x 2= 0.8 → 0
0.8 x 2= 1.6 → 1
0.6 x 2= 1.2 → 1
(0.1)​ 10​ = (0.00011)​ 2
(40)​ 10​ = (101000)​ 2
101000.00011
Normalize the number
1.0100000011 x 2​ 5
Biased exponent= 5+127= 132=(1000 0100)​ 2
Mantissa= 01000000110000000000000
Sign= 1
Question 137
​Which of the following statements are true ?
(i) Every logic network is equivalent to one using just NAND gates or just NOR gates.
(ii) Boolean expressions and logic networks correspond to labelled acyclic digraphs.
(iii) No two Boolean algebras with n atoms are isomorphic.
(iv) Non-zero elements of finite Boolean algebras are not uniquely expressible as joins of atoms.
A
(i) and (iv) only
B
(i) and (ii) only
C
(i), (ii) and (iii) only
D
(ii), (iii) and (iv) only
       Digital-Logic-Design       Boolean-Algebra       UGC NET CS 2018-DEC Paper-2
Question 137 Explanation: 
→ A universal logic gate is a logic gate that can be used to construct all other logic gates.
→ NAND and NOR are universal gates, by using these gates we can construct all gates.
→ An atom of a Boolean algebra is an element x such that there exist exactly two elements y satisfying y ≤ x, namely x and 0. A Boolean algebra is said to be atomic when every element is a sup of some set of atoms (the bottom element is always the empty sup).
→ So the options (iii) and (iv) are false
Question 138

The Circuit is equivalent to:
A
Ex-Or
B
NAND gate
C
OR gate
D
AND gate
       Digital-Logic-Design       Logic-Gates       Nielit Scientist-B CS 4-12-2016
Question 138 Explanation: 
Step-1: Here, A we are getting A’ and B we are getting B’. So, A’+B’
Step-2: (A’+B’)’=AB
Step-3: (AB)’=A’+B’
Solution: NAND or NOR but in options they are not given NOR. So, Final result is NAND
Question 139
A sinusoidal signal is analog signal, because:
A
It can have a number of values between the negative and positive peaks
B
It is negative for one half cycle
C
It is positive for one half cycle
D
it has positive as well as negative values
       Digital-Logic-Design       Analog-and-Digital-Signal       Nielit Scientist-B CS 4-12-2016
Question 139 Explanation: 
● Analog signal is a continuous signal and digital signal is a discrete signal.
● A sinusoidal signal is a continuous signal with respect to time.
● Therefore, sinusoidal signal is a analog signal.
Question 140
What will be the Excess-3 code for 1001?
A
1001
B
1010
C
1011
D
1100
       Digital-Logic-Design       Number-Systems       Nielit Scientist-B CS 4-12-2016
Question 140 Explanation: 
Excess-3 number starts with 3. Here, 1001 menas decimal number-9. So, we have to add +3.
12 equivalent binary number is 1100.
Question 141
What will be the final output of D flip-flop, if the input string is 11010011?
A
1
B
0
C
Don't Care
D
none of Above
       Digital-Logic-Design       Sequential-Circuits       Nielit Scientist-B CS 4-12-2016
Question 141 Explanation: 
Step-1: D flip flop is nothing data flip flop. It will return what we are given in input.
Step-2: In this question, the LSB and MSB are 1. So final output is 1.
Note: Here, we don’t know what order they are given input.
Question 142
Which will be the equation of simplification of the given K-map?
A
AB' + B'CD' + A'B'C'
B
AB' + A'B'D' + A'B'C'
C
B'D' + AB' + B'C'
D
B'D' + A'B'C' + AB'
       Digital-Logic-Design       K-Map       Nielit Scientist-B CS 4-12-2016
Question 142 Explanation: 
From the given K-map,
Last row Mapping gives AB’
In the first row - from the first and first column mapping gives B’C’
In the first row - from the first and last column mapping gives B’D’
. Then the final equation will be AB’+B’C’+B’D’
Question 143
The Decimal equivalent of the Hexadecimal number (A09D)16 is
A
31845
B
41117
C
41052
D
32546
       Digital-Logic-Design       Number-Systems       Nielit Scientist-B CS 4-12-2016
Question 143 Explanation: 
Given Hexadecimal number is ​ (A09D)16
A decimal number is the sum of the digits multiplied with its power of 10.
(A09D)16​ is equal to each digit multiplied with its corresponding power of 16:
Ax16​ 3​ +0x16​ 2​ +9x16​ 1​ +Dx16​ 0​ =(10x4096+144+13x1) [ Where A=10,D=13]
=40960+144+13=41117
Question 144
Which one of the following is true?
A
NAND gate and AND gate both are universal gates
B
NOR gate and OR gate both are universal gates
C
NAND gate and OR gate both are universal gates
D
NAND gate and NOR gate both are universal gates
       Digital-Logic-Design       Logic-Gates       Nielit Scientist-B IT 22-07-2017
Question 144 Explanation: 
A universal gate is a gate which can implement any Boolean function without need to use any other gate type. The NAND and NOR gates are universal gates.
Question 145
Which one of the following is the function of a multiplexer
A
To decode information
B
To select 1 out of N input data sources and to transmit it to single channel
C
To transmit data on N lines
D
To perform serial to parallel conversion
       Digital-Logic-Design       Combinational-Circuits       Nielit Scientist-B IT 22-07-2017
Question 145 Explanation: 
● A multiplexer (or mux) is a device that combines several analog or digital input signals and forwards them into a single output line.
● A multiplexer of 2​ n inputs has n select lines, which are used to select which input line to send to the output.
● Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth.
Question 146
​ In digital logic, if A ​ ⊕ ​ B=C, then which one of the following is true?
A
A ​ ⊕ ​ C=B
B
B ​ ⊕ ​ C=A
C
A ​ ⊕ ​ B ​ ⊕ ​ C=0
D
Both A) and B)
E
None of these
       Digital-Logic-Design       Boolean-Algebra       Nielit Scientist-B IT 22-07-2017
Question 146 Explanation: 
Given that
XOR:
X ⊕ X= 0
X ⊕ X'= 1
X ⊕ 0 = X
X ⊕ 1 = X'
A) A ⊕ C = B
A ⊕ A ⊕ B = B
0 ⊕ B = B
B= B
B) B ⊕C = A
B ⊕ A ⊕ B = A
A ⊕ 0=A
A=A
C) A⊕B=C
A⊕B⊕ C=C ⊕C ,
A⊕B⊕ C= 0
All are correct
Question 147
Which of the given number has its IEEE-754 32 bit floating point representation as
A
2.5
B
3.0
C
3.5
D
4.5
       Digital-Logic-Design       Number-Systems       ISRO CS 2015
Question 147 Explanation: 
→ Sign bit S = 0 (It means positive number)
→ E=1000 0000B = 128D (in normalized form)
→ Fraction is 1.11B (with an implicit leading 1) = 1 + 1×2-1 + 1×2-2
= 1.75D
→ The number is +1.75 × 2(128-127)
= +3.5D
Question 148
The range of integers that can be represented by an n bit 2’s complement number system is:
A
– 2n – 1 to 2n – 1 – 1
B
– (2n – 1 – 1) to (2n – 1 – 1)
C
– 2n – 1 to 2n – 1
D
– (2n – 1 + 1) to (2n – 1 – 1)
       Digital-Logic-Design       Number-Systems       ISRO CS 2015
Question 148 Explanation: 
In 2’s complement numbers, the range of integers are from -2n-1 to 2n-1 – 1
Question 149
How many 32K X 1 RAM chips are needed to provide a memory capacity of 256K-bytes?
A
8
B
32
C
64
D
128
       Digital-Logic-Design       RAM       ISRO CS 2015
Question 149 Explanation: 
Number of RAM chips required = Memory capacity / RAM chip capacity.
=(256K * 8) / (32K x 1)
=(256*1024*8) / (32*1024*1)
=64
Question 150
A modulus -12 ring counter requires a minimum of
A
10 flip-flops
B
12 flip-flops
C
8 flip-flops
D
6 flip-flops
       Digital-Logic-Design       Sequential-Circuits       ISRO CS 2015
Question 150 Explanation: 
A ring counter is a type of counter composed of flip-flops connected into a shift register, with the output of the last flip-flop fed to the input of the first, making a "circular" or "ring" structure.
The “MODULO” or “MODULUS” of a counter is the number of states the counter counts or sequences through before repeating itself and a ring counter can be made to output any modulo number. A “mod-n” ring counter will require “n” number of flip-flops connected together to circulate a single data bit providing “n” different output states
So, modulus-12 requires , 12 flip-flops.
Question 151
The complement of the Boolean expression AB ( B’C + AC ) is
A
( A’ + B’ ) + ( B + C’ )( A’ + C’ )
B
( A’ + B’ ) + ( BC’ + A’C’ )
C
( A’ + B’ )( B + C’) + ( A + C’ )
D
( A + B )( B’ + C )( A + C )
       Digital-Logic-Design       Boolean-Expression       ISRO CS 2015
Question 151 Explanation: 
→ Finding complement boolean expression, we require Demorgan’s law.
→ DeMorgan’s law and after complementing:
⇒ ( AB ( B’C + AC ))’
⇒ (A + B)’ + (B’C + AC)’
⇒ (A’ + B’) + ( B’C)’ (AC)’
⇒ (A’ + B’) + ( B + C’)(A’ + C’)
Question 152
The code which uses 7 bits to represent a character is
A
ASCII
B
BCD
C
EBCDIC
D
Gray
       Digital-Logic-Design       Number-Systems       ISRO CS 2015
Question 152 Explanation: 
→ ISO/IEC 646, like ASCII, is a 7-bit character set. It does not make any additional codes available, so the same code points encoded different characters in different countries. Escape codes were defined to indicate which national variant applied to a piece of text, but they were rarely used, so it was often impossible to know what variant to work with and, therefore, which character a code represented, and in general, text-processing systems could cope with only one variant anyway.
→ Extended Binary Coded Decimal Interchange Code (EBCDIC) is an 8-bit binary code for numeric and alphanumeric characters.
→ BCD encoding uses 4 bits to represent each digit from the range 0 to 9 in its binary form.
→ In case of Gray codes, any number of bits can be used to represent a character, according to the requirement.
Question 153
If half adders and full adders are implemented using gates, then for the addition of two 17 bit numbers (using minimum gates) the number of half adders and full adders required will be
A
0, 17
B
16, 1
C
1, 16
D
8, 8
       Digital-Logic-Design       Adder       ISRO CS 2015
Question 153 Explanation: 
1. An adder is a digital circuit that performs addition of numbers. The half adder adds two binary digits called as augend and addend and produces two outputs as sum and carry; XOR is applied to both inputs to produce sum and AND gate is applied to both inputs to produce carry.
2. The full adder adds 3 one bit numbers, where two can be referred to as operands and one can be referred to as bit carried in. And produces 2-bit output, and these can be referred to as output carry and sum.
Half adder is used to add two numbers of the least significant bits, so one half adder is required. In order to add remaining 16 bits of two numbers , we require 16 full adders
Question 154
Minimum number of 2x1 multiplexers required to realize the following function,
f = A’B’C + A’B’C’
Assume that inputs are available only in true form and Boolean constant 1 and 0 are available.
A
1
B
2
C
3
D
7
       Digital-Logic-Design       Combinational-Circuit       ISRO CS 2015
Question 154 Explanation: 
Given function f = A’B’C + A’B’C’
=A’B’(C+C’) (C+C’=1)
=A’B’
=(A+B)’
So we can implement with minimum Two number of 2x1 multiplexers
Question 155
The number of 1’s in the binary representation of (3*4096 + 15*256 + 5*16 + 3) are:
A
8
B
9
C
10
D
12
       Digital-Logic-Design       Number-Systems       ISRO CS 2015
Question 155 Explanation: 
Binary expression of (3*4096 + 15*256 + 5*16 + 3)
=(12,288+3840+80+3)
=(16211)10
=‭(0011111101010011‬)2
Total number of 1’s in binary representation is 10.
Question 156
The boolean expression AB + AB’+ A’C + AC is independent of the boolean variable
A
A
B
B
C
C
D
None of these
       Digital-Logic-Design       Boolean-Expression       ISRO CS 2015
Question 156 Explanation: 

→ AB + AB' + A'C + AC
= A(B + B') + C(A + A')
= A+C
As the expression is independent of 'B'
Question 157
The decimal number has 64 digits.The number of bits needed for its equivalent binary representation is?
A
200
B
213
C
246
D
277
       Digital-Logic-Design       Number-Systems       ISRO CS 2015
Question 157 Explanation: 
Consider three digits(1,2,3) of decimal numbers.Maximum number, we can generate by that three digits are 103-1 which is 999.
Then, Decimal number has 64 digits, so maximum number is 1064-1
Similarly, in the binary representation with “n” bits the maximum number is 2n-1
So we can write 1064 –1 = 2n – 1 --->1064 = 2n
After taking log2 on both sides
log22n=log21064
n log22=64 log 210
n=64*(3.322) [ log22=1 & log210 =3.322]
n=212.608
n=213
Question 158

Which of the following Boolean equations is/are correct?

X(X'+ Y) = XY'
X + XY = X
X + X'Y = X + Y
A
only (iii)
B
only (ii)
C
only (i)
D
Both (ii) and (iii)
       Digital-Logic-Design       Boolean-Function       JT(IT) 2018 PART-B Computer Science
Question 158 Explanation: 
Question 159

The following circuit represents the function of a 2–input __________ logic gate.

 
A
Exclusive-OR
B
Exclusive-NOR
C
NAND
D
NOR
       Digital-Logic-Design       Logic-Gates       JT(IT) 2018 PART-B Computer Science
Question 159 Explanation: 
Step-1: A⊕B = (A’⊕B’)
Step-2:

Step-3: We have to apply not operation then we are getting Ex-NOR.
Question 160

The maximum number of boolean functions that can be formed using 3 boolean variable is ____.

A
512
B
256
C
128
D
1024
       Digital-Logic-Design       Boolean-Function       JT(IT) 2018 PART-B Computer Science
Question 160 Explanation: 
→ The set of all Boolean functions of a finite number of Boolean variables. This function assigns a unique integer between 0 and 22n - 1 to each Boolean function of n Boolean variables.
→ For three Boolean variables (n = 3), there are 23 = 8 different cases, giving us a total of 28
= 256 Boolean functions of 3 variables.
Question 161

Which of the following does NOT represent the Exclusive NOR operation over the binary variables A and B?

A
A’ ⊕ B’
B
A ⊕ B’
C
A’ ⊕ B
D
AB + A’B’
       Digital-Logic-Design       Boolean-Algebra       JT(IT) 2018 PART-B Computer Science
Question 161 Explanation: 
A’ ⊕ B’ = Ex-NOR
Question 162

Suppose x and y are floating point variables that have been assigned the values x = 8.8 and y = 3.5. What will be the value of the following arithmetic expression?

2 * x / 3 * y

A
20.33335
B
24.45453
C
16.35353
D
20.53333
       Digital-Logic-Design       Number-Systems       JT(IT) 2018 PART-B Computer Science
Question 162 Explanation: 
x = 8.8 y=3.5
= 1 (equal priority
Associativity (left to Right)
(((2 * x)/3) * y)
((2 x *) / 3) * y)
(2x * 31) * y
2x * 31) y*
(2x * 31 y*
Put the 2 * 8.8 * 3 / 3.5 *
= 20.53333
Question 163

The boolean function X’Y’ + XY + X’Y, where X’ represents the complement of X, is equivalent to ____

A
X + Y’
B
X’ + Y’
C
X’ + Y
D
X + Y
       Digital-Logic-Design       Boolean-Function       JT(IT) 2018 PART-B Computer Science
Question 163 Explanation: 
Question 164

What is the base(radix) of the number system whose numbers 312, 20 and 13.1 satisfy the following equation?

312/20 = 13.1
A
8
B
4
C
5
D
6
       Digital-Logic-Design       Number-Systems       JT(IT) 2018 PART-B Computer Science
Question 164 Explanation: 
Let base of the number system is r.
(3r2 + r + 2) / 2r = (r + 3 + 1/r)
(3r2 + r + 2) / 2r = (r2 + 3r + 1) / r
(3r2 + r + 2) = (2r2 + 6r + 2)
r2 - 5r = 0
Therefore, r = 5
Question 165

What is the hexadecimal representation of the decimal number 8537?

A
(2059)16
B
(2159)16
C
(2195)16
D
(2157)16
       Digital-Logic-Design       Number-Systems       JT(IT) 2018 PART-B Computer Science
Question 165 Explanation: 
Step-1: First convert decimal number into binary number
Step-2: (8537)10 = (0010000101011001)2
Step-3: Divide binary number into 4 segments (0010 0001 0101 1001)2
Step-4: Write equivalent number of hexadecimal (2159)16
Question 166

Which of the following is a recursive algorithm to convert a positive decimal integers into equivalent binary integers?

A
B
C
D
       Digital-Logic-Design       Number-Systems       JT(IT) 2018 PART-B Computer Science
Question 166 Explanation: 
Algorithm:
Take decimal number is 12.
Step-1 → 12%2 which is equal to 0+10*(⌊12/2⌋)%2
Step-2 → 6%2 which is equal to 0+10*(⌊6/2⌋)%2
Step-3 → 3%2 which is equal to 1+10*(⌊3/2⌋)%2
Step-4 → 1%2 which is equal to 1+10*(⌊1/2⌋)%2
Question 167

What is the minimum number of 2 input NOR gates to implement the Boolean function (XY+Z)?

A
8
B
5
C
3
D
7
       Digital-Logic-Design       Boolean-Function       JT(IT) 2018 PART-B Computer Science
Question 167 Explanation: 
XY+Z
= (X+Z)(Y+Z)( Distribute + over .)
= ((X+Z)' +(Y+Z)' )'
Question 168
In a ripple counter using edge-triggered JK flip-flops, the pulse input is applied to
A
Clock input of all flip flops
B
J and K input of one flip flop
C
J and K input of all flip flops
D
Clock input of one flip flops
       Digital-Logic-Design       Sequential-Circuits       Nielit Scientific Assistance IT 15-10-2017
Question 168 Explanation: 
In a ripple counter using edge triggered JK flip-flops, the pulse input is applied to the clock input of one flip flops.
Question 169
How many 2-input multiplexers are required to construct a 2​ 10​ input multiplexer?
A
1023
B
31
C
10
D
127
       Digital-Logic-Design       Combinational-Circuits       Nielit Scientific Assistance IT 15-10-2017
Question 169 Explanation: 
210 x1 MUX has 210 inputs.
Level-1 has 29 (=512) 2x1 multiplexers which take 2*29 = 210 inputs and produces 512 outputs.
Similarly,
Level-2 has 256 MUX.
Level-3 has 128 MUX.
Level-4 has 64 MUX.
Level-5 has 32 MUX.
Level-6 has 16 MUX.
Level-7 has 8 MUX.
Level-8 has 4 MUX.
Level-9 has 2 MUX.
Level-10 has 1 MUX.
Total number of Multiplexers=
512+256+128+64+32+16+8+4+2+1=1023
Question 170
The number of columns in a state table for a sequential circuit with 'm' flip flops and 'n' input is
A
m+n
B
m+2n
C
2m+n
D
2m+2n
       Digital-Logic-Design       Sequential-Circuits       Nielit Scientific Assistance IT 15-10-2017
Question 170 Explanation: 
Its 2m+2n because. If there are m flip-flops, there should be 2m nodes. If there are n inputs, then each node will have 2n.
Question 171
A decimal has 25 digits. the number of bits needed for its equivalent binary representation is approximately
A
50
B
74
C
40
D
60
E
None of these
       Digital-Logic-Design       Number-Systems       Nielit Scientific Assistance IT 15-10-2017
Question 171 Explanation: 
Consider three digits(1,2,3) of decimal numbers.Maximum number, we can generate by that three digits are 10​ 3​ -1 which is 999.
Then, Decimal number has 25 digits, so maximum number is 10​ 25​ -1
Similarly, in the binary representation with “n” bits the maximum number is 2​n​ -1
So we can write 10​ 25​ –1 = 2​ n​ – 1 --->10​ 25​ = 2​ n After taking log​ 2​ on both sides
log​ 2​ 2​ n​ =log ​ 2​ 10​ 25
n log​ 2​ 2=25 log ​ 2​ 10
n=25*(3.322) [ log​ 2​ 2=1 & log​ 2​ 10 =3.322]
n=83
Question 172
A sequential circuit using D flip flop and logic gates is shown in figure, Where X and Y are the inputs and Z is the output. The circuit is
A
S-R flip flop with inputs X=R and Y=S
B
S-R flip flop with inputs X=S and Y=R
C
J-K flip flop with inputs X=J and Y=K
D
J-K flip flop with X=k and Y=J
       Digital-Logic-Design       Sequential-Circuits       Nielit Scientific Assistance IT 15-10-2017
Question 172 Explanation: 
Here, PI=Present Input
PS=Present state
NS=Next State
Q​ n+1​ =D=f(PI,PS)=f(x,y,Q​ n​ )
D=X’Z+YZ


Question 173
A 4 bit ripple counter and a 4 bit synchronous counter are made using flip flops having a propagation delay of 10ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then
A
R=10 ns, S=40ns
B
R=40ns, S=10ns
C
R=10ns, S=30ns
D
R=30 ns, S=10ns
       Digital-Logic-Design       Sequential-Circuits       Nielit Scientific Assistance IT 15-10-2017
Question 173 Explanation: 
● A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop.
● Synchronous Counters are so called because the clock input of all the individual flip-flops within the counter are all clocked together at the same time by the same clock signal.
● In the ripple counter, each flip flop will depending upon the precede flip flop and propagation delay is 10ns.So the propagation delay of 4-bit ripple counter is 4*10=40ns.
● In the synchronous counter,one clock input is enough so the propagation delay is 10ns.
Question 174
The smallest integer that can be represented by an 8-bit number in 2's complement form is:
A
-256
B
-128
C
-127
D
0
       Digital-Logic-Design       Nielit STA 17-12-2017
Question 174 Explanation: 
→ For n bit 2’s complement numbers, range of number is -(2(n-1)) to +(2(n-1)-1)
→ The smallest integer that can be represented by an 8-bit number in 2’s complement form is =-(2(n-1))
= -128
Question 175
The number (25)6 base 6 is equivalent to __ in binary number system
A
11001
B
10001
C
11000
D
10000
       Digital-Logic-Design       Nielit STA 17-12-2017
Question 175 Explanation: 
(25)6=(10001)2
Here, First we have to convert (25)6 into decimal number system. Then we have to convert into binary. (25)6=(17)10=(10001)2
Question 176
To load a byte of data parallelly into a shift register with a synchronous load, there must be__
A
One clock pulse
B
One clock pulse for each 1 in the data
C
Eight clock pulses
D
One clock pulse for each 0 in the data
       Digital-Logic-Design       Sequential-Circuits       KVS 22-12-2018 Part-B
Question 176 Explanation: 
The sequential device loads the data present on its inputs and then moves or “shifts” it to its output once every clock cycle, hence the name Shift Register.
Question 177
Shifting a register content to left by one bit is equivalent to____
A
Division by 2
B
Addition by 2
C
Multiplication by 2
D
Subtraction by 2
       Digital-Logic-Design       Number-Systems       KVS 22-12-2018 Part-B
Question 177 Explanation: 
→ The left-shift operator (<<), which moves the bits of shift-expression to the left.
→ The bit positions that have been vacated by the shift operation are zero-filled.
→ For example a=5 and equivalent binary value is 101 and shifting one bit left side means the result binary value is 1010 whose decimal value is 10
Question 178
What shall be the 2’s complement represented of -24 in a 16 bit computer?
A
1111 1111 1110 1011
B
1111 1111 1110 1001
C
1111 1111 1110 0111
D
1111 1111 1110 1000
       Digital-Logic-Design       Number-Systems       KVS 22-12-2018 Part-B
Question 178 Explanation: 
Negative numbers are represented in 2’s complement form.
The binary equivalent of 24 is 0000 0000 0001 1000
One’s complement is 1111 1111 1110 0111 (Flipping the bits 1 by 0 and 0 by 1)
Two’s complement is 1111 1111 1110 1000 (adding 1 to the LSB bit)
Question 179
Which of the following is/are wrong?
a) RAM and ROM are volatile memories
b) ROMs,PROMs and EPROMs are non volatile memories
c) RAM and Dynamic RAM are same
d) A random access memory(RAM) is a read write memory
A
(a) and (b)
B
(a) and (c)
C
(a) and (d)
D
(c) and (d)
       Digital-Logic-Design       RAM       KVS 22-12-2018 Part-B
Question 179 Explanation: 
Statements b and d are correct.
Random Access Memory (RAM) –
→ It is also called as read write memory or the main memory or the primary → memory.
→ The programs and data that the CPU requires during execution of a program are stored in this memory.
→ It is a volatile memory as the data loses when the power is turned off.

ROM
→ Stores crucial information essential to operate the system, like the program essential to boot the computer.
→ It is non-volatile memory.
Question 180
Exclusive OR(XOR) is a special gate whose output is 1 only if:
A
All inputs are 0
B
All inputs are 1
C
Odd numbers of inputs are 1
D
Even number of inputs are 1
       Digital-Logic-Design       Logic-Gates       KVS 22-12-2018 Part-B
Question 180 Explanation: 
→Exclusive OR gate or XOR gate is a is a digital logic gate that implements an exclusive OR, that is, a true output (1/HIGH) results if one, and only one, of the inputs to the gate is true.
→If both inputs are false (0/LOW) or both are true, a false output results. XOR represents the inequality function, i.e., the output is true if the inputs are not alike otherwise the output is false.
Question 181
Which of the following flipflops does not have a problem of race condition?
A
T flip flop
B
JK flip flop
C
Clocked-RS flip flop
D
Clocked D flip flop
       Digital-Logic-Design       Sequential-Circuits       KVS 22-12-2018 Part-B
Question 181 Explanation: 
In JK flip flop as long as clock is high for the input conditions J&K equals to the output changes or complements its output from 1–>0 and 0–>1. This is called toggling output or uncontrolled changing or racing condition.
Question 182
A device which converts BCD to seven segment is called____
A
Encoder
B
Decoder
C
Decoder
D
Demultiplexer
       Digital-Logic-Design       Combinational-Circuit       KVS 22-12-2018 Part-B
Question 182 Explanation: 
A Display Decoder is a combinational circuit which decodes and n-bit input value into a number of output lines to drive a display
Question 183
In single-precision, double-precision and extended-precision representation of floating point numbers, as defined by ANSI/IEEE standard 754-1985, the no.of bits used are____ respectively.
A
32,64 and 80
B
32,64 and 128
C
16,32 and 64
D
16,32 and 80
       Digital-Logic-Design       Number-Systems       KVS 22-12-2018 Part-B
Question 183 Explanation: 

Extended precision, the third format, is usually an 80-bit word, with 1 bit sign, 15 bit exponent and 64 bit significand, with leading bit of a normalized number not hidden
Question 184
The simplified form of the boolean expression: (AB’(C+BD)+A’B’)C is:
A
B’C
B
A’B’C
C
AB’C
D
A’BC
       Digital-Logic-Design       Boolean-Expression       KVS 22-12-2018 Part-B
Question 184 Explanation: 
(AB’(C+BD)+A’B’)C
(AB'C + AB'BD + A'B')C
(AB'C + A'B')C
AB'C + A'B'C
(A+A') B'C
B'C
Question 185
A decimal has 25 digits. the number of bits needed for its equivalent binary representation is approximately
A
50
B
74
C
40
D
None of the above
       Digital-Logic-Design       Number-Systems       Nielit Scientific Assistance CS 15-10-2017
Question 185 Explanation: 
Consider three digits(1,2,3) of decimal numbers.Maximum number, we can generate by that three digits are 10​ 3​ -1 which is 999.
Then, Decimal number has 25 digits, so maximum number is 10​ 25​ -1
Similarly, in the binary representation with “n” bits the maximum number is 2​ 25​ -1
So we can write 10​ 25​ –1 = 2​ n​ – 1 → 10​ 25​ = 2​ n
After taking log​ 2​ on both sides
log​ 2​ 2​ n​ =log ​ 2​ 10​ 25
n log​ 2​ 2=25 log ​ 2​ 10
n = 25 log ​ 2​ 10
n = 25 x 3.3 [ log​ 2​ 2=1 & log​ 2​ 10 =3.322]
n = 82.5
Note: Original question paper given option D is 60. But actual answer is 82.5.
Question 186
Which of the following is minimum error code?
A
Octal code
B
Binary Code
C
Gray code
D
Excess-3 Code
       Digital-Logic-Design       Number-Systems       Nielit Scientific Assistance CS 15-10-2017
Question 186 Explanation: 
→ "Gray code" as an alternative name is "reflected binary code". one of those also lists "minimum error code" and "cyclic permutation code" among the names.
→ Gray codes are widely used to facilitate error correction in digital communications such as digital terrestrial television and some cable TV systems.
Question 187
The possible number of boolean function of 3 variables X,Y and Z such that f(X,Y,Z)=f(X',Y',Z')
A
8
B
16
C
64
D
32
       Digital-Logic-Design       Boolean-Function       Nielit Scientific Assistance CS 15-10-2017
Question 187 Explanation: 

→ Like above other input combinations also repeat after these inputs.
→ We have 4 input pairs and produces output either 0 or 1.
→ Total functions possible=2*2*2*2 (or) 2​ 4 =16
Question 188
If the original size of data is 40 then after adding error detection redundancy bit the size of data length is
A
26
B
36
C
46
D
56
       Digital-Logic-Design       Number-Systems       Nielit Scientific Assistance CS 15-10-2017
Question 188 Explanation: 
→ Imagine that we want to design a code with m message bits and r check bits that will allow all single errors to be corrected.
→ Each of the 2​ m​ legal messages has n illegal codewords at a distance of 11 from it.
→ These are formed by systematically inverting each of the n bits in the n-bit codeword formed from it. Thus, each of the 2​ m​ legal messages requires n+1 bit patterns dedicated to it.
→ Since the total number of bit patterns is 2​ n​ ,​ We must have (n+1)2​ m​ ≤ 2​ n​ .
→ Using n=m+r, this requirement becomes
= (m+r+1) ≤ 2​ r
= 40+6+1 ≤ 26
= 47 ≤ 2
r=6
Message size will be 6+40=46
Question 189
A sequential circuit using D flip flop and logic gates is shown in figure, Where X and Y are the inputs and Z is the output. The circuit is
A
S-R flip flop with inputs X=R and Y=S
B
S-R flip flop with inputs X=S and Y=R
C
J-K flip flop with inputs X=J and Y=K
D
J-K flip flop with X=k and Y=J
       Digital-Logic-Design       Sequential-Circuits       Nielit Scientific Assistance CS 15-10-2017
Question 189 Explanation: 
Here, PI=Present Input
PS=Present state
NS=Next State
Q​ n+1​ =D=f(PI,PS)=f(x,y,Q​ n​ )
D=X’Z+YZ

Question 190
A 4 bit ripple counter and a 4 bit synchronous counter are made using flip flops having a propagation delay of 10ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then
A
R=10 ns, S=40ns
B
R=40ns, S=10ns
C
R=10ns, S=30ns
D
R=30 ns, S=10ns
       Digital-Logic-Design       Sequential-Circuits       Nielit Scientific Assistance CS 15-10-2017
Question 190 Explanation: 
→ In synchronous counter time delay is constant while in Ripple it is additive.
→ In Ripple counter (or) Asynchronous counter each flip flop waits for its previous flip flops output.
R= bit size*propagation delay
= 4*10ns
= 40ns
→ In Synchronous counter all flip flops are triggered by same clock. It will gives output of all four flip flops at the same time.
S=10ns
Question 191
In a ripple counter using edge-triggered JK flip-flops, the pulse input is applied to
A
Clock input of all flip flops
B
j and K input of one flip flop
C
J and K input of all flip flops
D
Clock input of one flip flops
       Digital-Logic-Design       Sequential-Circuits       Nielit Scientific Assistance CS 15-10-2017
Question 191 Explanation: 
A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock.
→ All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are also called ripple-counters because of the way the clock pulse ripples it way through the flip-flops.

So, answer is clock input of one flip-flop.
Question 192
Consider an arbitrary number system with the independent digits as 0,1 and X. What is the radix of this number system?
A
1
B
2
C
3
D
4
       Digital-Logic-Design       Number-Systems       KVS DEC-2013
Question 192 Explanation: 
→ The radix of a number system is the number of unique digits, including, zero, that are used to represent larger numbers. In the decimal system that would be 0 to 9.
→ In the question, the unique digits are 0,1 and X(possible x value is 2) then number system is 3;
Question 193
The following diagram shows a
A
Exclusive NOR gate
B
NAND gate
C
AND gate
D
OR gate
       Digital-Logic-Design       Logic-Gates       KVS DEC-2013
Question 193 Explanation: 
→ The XNOR gate is a digital logic gate whose function is the logical complement of the exclusive OR gate.
→ The two-input version implements logical equality, behaving according to the truth table to the right, and hence the gate is sometimes called an "equivalence gate"
Question 194
The diagram below shows a
A
Half adder
B
Half subtractor
C
Full adder
D
Full Subtractor
       Digital-Logic-Design       Logic-Gates       KVS DEC-2013
Question 194 Explanation: 
The above diagram gives the following expressions
Difference (D) = (A’B + AB’) = A ⊕ B
Borrow (B) = A’B
Question 195
A/an _____, also called a dta selector, is a combinational circuit with more than on input line, one output line and more than one selection line.
A
De multiplexer
B
Multiplexer or MUX
C
Operational amplifier
D
Integrated circuit
       Digital-Logic-Design       Combinational-Circuits       KVS DEC-2013
Question 195 Explanation: 
● A multiplexer (or mux) is a device that combines several analog or digital input signals and forwards them into a single output line.
● A multiplexer of 2​ n​ inputs has n select lines, which are used to select which input line to send to the output.
● A multiplexer is also called a data selector. Multiplexers can also be used to implement Boolean functions of multiple variables.
Question 196
Determine the function performed by the combinational circuit of the given figure.
A
4 to 1 multiplexer
B
8 to 1 multiplexer
C
16 to 1 multiplexer
D
32 to 1 multiplexer
       Digital-Logic-Design       Combinational-Circuits       KVS DEC-2013
Question 196 Explanation: 
Four input lines I​ 0​ ,I​ 1​ ,I​ 2​ and I​ 3​ and Two Selection lines S​ 0 and S​ 1
One output line F
Question 197
Determine the size of PROM required for implementing the 16 to 1 multiplexer
A
1Mx1
B
2Mx1
C
8Mx1
D
32mx1
       Digital-Logic-Design       Combinational-Circuits       KVS DEC-2013
Question 197 Explanation: 
●Programmable read-only memory (PROM) is read-only memory ( ​ ROM​ ) that can be modified once by a user.
● PROM is a way of allowing a user to tailor a microcode program using a special machine called a PROM programmer.
● PROM consists of n input and m output lines and which can be represented as 2​ n ​ x m PROM
● In order to implement an n-input , m-output circuit we need 2​ n​ x m size PROM
● From the given question we need to implement 16:1 Mux. So inputs are 16 + (4 selection lines in 16x1 mux) =20
● n=20 and m=1
● PROM size =2​ 20​ =1M
Question 198
The hamming(7,4) code for 0000 using even parity is
A
0000000
B
1111111
C
2222222
D
12121212
       Digital-Logic-Design       Number-Systems       KVS DEC-2013
Question 198 Explanation: 
● Hamming(7,4) is a linear error-correcting code that encodes four bits of data into seven bits by adding three parity bits.
● The data is ​ 0000 and Hamming(7,4) transmitted is 0000000
Question 199
Determine the number of programmable inter connections in the following programmable logic device-PAL device with eight input variables, 16 AND gates and four OR gates
A
384
B
512
C
256
D
128
       Digital-Logic-Design       Logic-Gates       KVS DEC-2013
Question 199 Explanation: 
PAL has only AND plane.
Number of connections
= 2*Inputs * #AND gates
= 2*8*16
= 256
Question 200
The reduced expression for the following expression using a karnaugh map F(W,X,Y,Z)=Σ(0,4,8,12) is:
A
YZ
B
Y’Z’
C
Y+Z
D
Y’+Z’
       Digital-Logic-Design       K-Map       KVS DEC-2013
Question 201
The following diagram depicts ____ logic
A
Diode
B
Transistor
C
Diode transistor
D
Resistor
       Digital-Logic-Design       Logic-Families       KVS DEC-2013
Question 201 Explanation: 
The given diagram is combination of both Diode and Transistor
Question 202
The reduced expression for the following expression using a karnaugh map F(W,X,Y,Z)=Σ(0,4,8,12) is:
A
YZ
B
Y’Z’
C
Y+Z
D
Y’+Z’
       Digital-Logic-Design       K-Map       KVS DEC-2013
Question 202 Explanation: 
Question 203
In a Schmitt trigger inverter circuit, the two trip points are observed to occur ar 1.8 and 2.8V. At what input voltage levels will this device make
(a) HIGH-to-LOW transition and
(b) LOW-to-HIGH transition?
A
2.8V & 1.8V
B
3V & 2V
C
4V & 2.2V
D
2.6V & 1.5V
       Digital-Logic-Design       Schmitt-Trigger-Inverter       KVS DEC-2013
Question 203 Explanation: 
Two trips are 1.8 and 2.8.
1.8 is low and 2.8 is high.
Schmitt trigger inverter circuit makes circuit low to high and high to low.
(a) is 2.8V
(b) is 1.8V
Question 204
A combinational logic circuit that is used when it is desired to send data from two more source through a single transmission line is known as__
A
Demultiplexer
B
Encoder
C
Decoder
D
Multiplexer
       Digital-Logic-Design       Combinational-Circuits       KVS DEC-2017
Question 204 Explanation: 
→ In electronics, a multiplexer (or mux) is a device that combines several analog or digital input signals and forwards them into a single output line.
→ A multiplexer of 2​ n​ inputs has n select lines, which are used to select which input line to send to the output. Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth.
→ A multiplexer is also called a data selector. Multiplexers can also be used to implement Boolean functions of multiple variables.
Question 205
The number of bits required to represent decimal number 4096 in binary form is___
A
16
B
10
C
12
D
13
       Digital-Logic-Design       Number-Systems       KVS DEC-2017
Question 205 Explanation: 
(4098)​ 10​ =(1000000000010)​ 2
So, total 13 bits required to represent 4096 decimal number.
Question 206
How many gate(s) would be required to implement the following boolean expression after simplification Expression:AC+ABC
A
4
B
1
C
2
D
3
       Digital-Logic-Design       Boolean-Function       KVS DEC-2017
Question 206 Explanation: 
Step-1: We have to check whether we can minimize the boolean expression or not
Step-2: AC+ABC
AC common in both.
=AC(1+B)
=AC
Step-3: It requires one AND gate is enough.
Question 207
The term sum of product in boolean algebra means
A
The AND function of several AND functions
B
The AND function of several OR functions
C
The OR function of several AND functions
D
The OR function of several OR functions
       Digital-Logic-Design       Boolean-Algebra       KVS DEC-2017
Question 207 Explanation: 
Sum of product: A boolean expression consisting purely of Minterms (product terms) is said to be in canonical sum of products form.
Example: F=AB+AC+AD Product of sum: A boolean expression consisting purely of Maxterms (sum terms) is said to be in canonical product of sums form.
Example: F=(A+B).(A+C).(A+D)
Question 208
Based on the current technology,___ is the fastest logic family
A
CMOS
B
TTL
C
MOS
D
ECL
       Digital-Logic-Design       Logic-Families       KVS DEC-2017
Question 208 Explanation: 
Question 209
How many bits are used in the exponent part of IEEE single precision for the representation of floating point numbers?
A
32 bits
B
8 bits
C
16 bits
D
24 bits
       Digital-Logic-Design       Number-Systems       KVS DEC-2017
Question 209 Explanation: 
The IEEE 754 standard specifies a binary floating point format(binary32) as having:
→ Sign bit: 1 bit
→ Exponent width: 8 bits
→ Significand precision: 24 bits (23 explicitly stored)
Question 210
In a positive edge triggered JK flip flop, a low J and a low K produces
A
no change
B
low state
C
high state
D
toggle state
       Digital-Logic-Design       Sequential-Circuits       KVS DEC-2017
Question 210 Explanation: 
→ In JK Flip Flop if J=K=0 then it holds its current state. There will be no change.
Question 211
The boolean expression (A+C)(AB'+AC)(AC'+B') can be simplified as
A
A'B+BC
B
AB'
C
AB+BC
D
AB+A'C
       Digital-Logic-Design       Boolean-Algebra       KVS DEC-2017
Question 211 Explanation: 
(A+C)(AB'+AC)(AC'+B')
First compute one and primes
(AAB'+AAC+AB'C+ACC)(AC'+B')
to take common AC then we get
(AB'+AC+AB'C+AC)(AC'+B')
To take common AB'
(AB'(1+C)+AC)(AC'+B')
(AB'+AC)(AC'+B')
AB'AC'+AB'B'+ACAC'+ACB'
AB'C'+AB'+0+ACB'
AB'(C'+1)+ACB'
AB'+ACB'
AB'(1+C)
AB'
(or)
We can also use truth table to get same solution.
Question 212
What is the octal equivalent of the hexadecimal number 132A?
A
46252
B
11450
C
11452
D
45250
       Digital-Logic-Design       Number-Systems       KVS DEC-2017
Question 212 Explanation: 
Step-1: Convert hexadecimal number in binary format. It is nothing but representing 4 binary values of each character.
Step-2: (132A)​ 16​ =(0001 0011 0010 1010)​ 2 Step-3: Divide 4 binary numbers in to 3 binary numbers from right to left.
Step-4: (0 001 001 100 101 010)​ 2
(0 1 1 4 5 2)​ 8
Question 213
The logic circuits binary adder which is used to add two 4-bits binary numbers, requires___half adder(s) and _____full adder(s).
A
4,0
B
1,3
C
2,2
D
3,1
       Digital-Logic-Design       Adder       KVS DEC-2017
Question 213 Explanation: 
Half Adder takes two input bits and output sum and carry. Full Adder takes three input bits(which includes one carry bit) and output sum and carry.
One Half- Adder adds least significant bits of the two numbers. Three Full Adders
Question 214

The signed 2’s complement representation of -33 is:

A
11011111
B
00100001
C
01011111
D
10100001
       Digital-Logic-Design       Number-Systems       JT(IT) 2016 PART-B Computer Science
Question 214 Explanation: 
Step-1: -33 corresponding positive number 00100001
Step-2: Perform 2’s complement.
Question 215

Using signed 2’s complement subtraction the result of 11111010-11110011 is:

A
10000111
B
00000111
C
10001101
D
00001101
       Digital-Logic-Design       Number-Systems       JT(IT) 2016 PART-B Computer Science
Question 215 Explanation: 
11111010 → 250(Decimal)
-11110011 → -243(Decimal)
Step1: convert signed number into 2’s complement
11110011
00001100 → (1’s complement)
+1
-------------
00001101 → (2’s complement)
Step 2: Add 11111010 into 2’s complement number
11111010
00001101
--------------
00000111 → solution
Question 216

In boolean algebra, (x ⋀ y)’ = x’ V y’ and (x V y)’ = x’ ⋀ y’ is known as ___ law.

A
Demorgan’s law
B
Absorption
C
Dominance
D
Idempotent
       Digital-Logic-Design       Boolean-Algebra       JT(IT) 2016 PART-B Computer Science
Question 216 Explanation: 
The rules can be expressed in English as:
1. The negation of a disjunction is the conjunction of the negations.
2. The negation of a conjunction is the disjunction of the negations.
Question 217
Convert the following octal number into its decimal equivalent: 2 3 7 4 in octal
A
(10208)10
B
(1276)10
C
(2374)10
D
(1272)10
       Digital-Logic-Design       Number-Systems       KVS 30-12-2018 Part B
Question 217 Explanation: 
(2374)8=2x83+3x82+7x81+4x80=1024+192+56+4=1276
Question 218
Which of the following statement/s is/are correct?
  1. With on-chip decoding, 8 address lines can access 64 memory locations
  2. With on-chip decoding, 4 address lines can access 64 memory locations
  3. With on-chip decoding, 8 address lines can access 256 memory locations
  4. With on-chip decoding, 4 address lines can access 128 memory locations
A
Only a
B
A and b
C
Only c
D
C and d
       Digital-Logic-Design       Combinational-Circuits       KVS 30-12-2018 Part B
Question 218 Explanation: 
->The n address lines consists of 2n memory locations
->8 address lines can access 28 =256 memory locations
Question 219
Represent the decimal number 3.248*104 into a single precision floating point binary number(using standard format).
A
0|10001101|11111011100000000000000
B
0|11001101|11111011100000000000000
C
1|11001101|11111011100000000000000
D
0|10001110|11111011100000000000000
       Digital-Logic-Design       Number-Systems       KVS 30-12-2018 Part B
Question 219 Explanation: 
Given number is in base 10. Convert it to base-10.
3.248x104 =32480= 1111110111
= 1.111110111 x 214
Mantissa = 11111011100...00
Biased exponent = 14 +127= 141 = 10001101
Question 220
When used with IC, what does he term QUAD indicate?
A
2 circuits
B
4 circuits
C
6 circuits
D
8 circuits
       Digital-Logic-Design       Logic-Families       KVS 30-12-2018 Part B
Question 220 Explanation: 
→A quad gate is an IC (integrated circuit or chip) containing four logic gates. The gates can be of any type: AND, OR, XOR, NOT, NAND, NOR, and XNOR. Within any given quad gate, all four of the individual gates are normally of the same type.
→A logic gate is an elementary building block of a digital circuit.
Question 221
Data can be changed from special code to temporal code by using
A
Shift Registers
B
Counters
C
Combinational circuits
D
A/D converters
       Digital-Logic-Design       Shift-Register       KVS 30-12-2018 Part B
Question 221 Explanation: 
By shift registers , data is can be changed from one code to another code.
Question 222
Words having 8 bits are to be stored in computer memory. The number of lines required for writing into the memory are
A
1
B
2
C
4
D
8
       Digital-Logic-Design       Combinational-Circuits       KVS 30-12-2018 Part B
Question 222 Explanation: 
Each line carries one bit of information.
Question 223
Words having 8 bits are to be stored in computer memory. The number of lines required for writing into the memory are
A
1
B
2
C
4
D
8
       Digital-Logic-Design       Combinational-Circuits       KVS 30-12-2018 Part B
Question 223 Explanation: 
Each line carries one bit of information.
Question 224
Which is the hexadecimal number equivalent to the octal number 46250
A
4AC8
B
4CA8
C
CCA8
D
4CA4
       Digital-Logic-Design       Number-Systems       KVS 30-12-2018 Part B
Question 224 Explanation: 
Given octal number is 46250 and the corresponding binary number we will get by writing each decimal digit into three binary digits form which is 100110010101000
Now group the four digits from LSB and write corresponding equivalent of Hexadecimal digit of binary digits.
The Hexadecimal number of 100(4) 1100(C) 1010(A) 1000(8) which is nothing but 4CA8
Question 225
If a 3-input NOR gate has 8 input possibilities, how many of those possibilities will result in a HIGH output?
A
1
B
3
C
7
D
8
       Digital-Logic-Design       Logic-Gates       KVS 30-12-2018 Part B
Question 225 Explanation: 
3-input NOR gate produces output 1 if input is 000.
Question 226
A full binary adder to add 4 bits requires_____ full adder(s) and ___half adder(s).
A
1,3
B
2,2
C
3,1
D
4,0
       Digital-Logic-Design       Adder       KVS 30-12-2018 Part B
Question 226 Explanation: 
Half Adder takes two input bits and output sum and carry. Full Adder takes three input bits(which includes one carry bit) and output sum and carry.
There is no carry in to the least significant bits. So one Half- Adder adds least significant bits of the two numbers.
Three Full Adders are used to add remaining bits along with carries.
Question 227
How many gates would be required to implement the following boolean expression after simplification? Expression:
A
4
B
6
C
8
D
10
       Digital-Logic-Design       Boolean-Algebra       KVS 30-12-2018 Part B
Question 227 Explanation: 
Given expression is =A’+B’+C’+A’C+B’C+A’BC’+AB’+AC’+AB’C
=A’+A’C+B’+B’C+C’+AC’+A’BC’+AB’+AB’C
=A’ (1+C)+B’(1+C)+C’(1+A)+A’BC’+AB’(1+C) [ 1+X=1]
=A’+B’+C’+A’BC’+AB’
=A’+C’+A’BC’+B’ (1+A)
=A’+C’+A’BC’+B’
=A’+B’+C’ (1+A’B)
=A’+B’+C’
Total four gates required three not gates and one OR gate.
Question 228
A boolean operator θ is defined as follows:
1θ1=1
1θ0=0
0θ1=0
0θ0=1
What will be the truth value of the expression (XθY)θZ=Xθ(YθZ)?
A
Always false
B
Always true
C
Sometimes true
D
Sometimes false
       Digital-Logic-Design       Boolean-Algebra       KVS 30-12-2018 Part B
Question 228 Explanation: 
(XθY)θZ=Xθ(YθZ) is always true if θ is associative.
From the given table, we can infer that θ is Ex-NOR operator.
Ex-NOR is associative. Hence (XθY)θZ=Xθ(YθZ) is always true
Question 229
In RS flip-flop, which of the following values of R and S causes race condition?
A
R=0,S=0
B
R=0,S=1
C
R=1,S=0
D
R=1,S=1
       Digital-Logic-Design       Sequential-Circuits       KVS 30-12-2018 Part B
Question 229 Explanation: 
→A race condition is a timing-related phenomenon. A standard S-R FF (two cross-coupled NAND or NOR gates) is stable for any stable input.
→Race around condition in digital circuits occur when the final state of the output depends on how the inputs arrive.
→The 'function' is in the S=1 R=1 input, the memory situation. The state of the FF depends on which state came before the 11, if it was 01 the FF is in Q=1 state, if it was 10 the FF is in the Q=0 state. This is the classical memory effect of a FF.
Question 230
The Octal equivalent of the binary number 1011101011 is :
A
7353
B
1353
C
5651
D
5657
       Digital-Logic-Design       Number-Systems       UGC NET CS 2017 Nov- paper-2
Question 230 Explanation: 
We have to divide binary number into 3 bit pairs from LSB.
1 011 101 011
1 3 5 3
(1011101011)​ 2​ = (1353)​ 8
Question 231
The output of the following combinational circuit is F.
A
P1+P’2P3
B
P1+P’2P’3
C
P​ 1​ +P​ 2​ P’​ 3
D
P​’ 1​ +P​ 2​ P​ 3
       Digital-Logic-Design       Combinational-Circuits       UGC NET CS 2017 Nov- paper-2
Question 231 Explanation: 
Method1: Simplification by expansion.
F= (P1+P'2+P'3 )( P1+ P'2+ P3 )( P1+P2+P'3) ← POS
=(P1+ P1P'2 +P1P3 + P'2P1 + P'2 P'2 + P'2P3 + P'3P1+ P'3P'2+P'3P3 )(P1+P2+P'3)
=(P1(1+P'2+P3 + P'2 + P'3)+P'2 (1+P3+P'3) + 0)(P1+P2+P'3 =(P1+P'2)(P1+P2+P'3)
=P1(1+P2+P'3+P'2)+P'2P2+P'2P'3
=P1 + 0 + P'2P'3
=P1 + P'2P'3
Method2:
This can also be solved by using K-Map. F= (P1+P'2+P'3 )( P1+ P'2+ P3 )( P1+P2+P'3)
F= π(3,2,1)
Express above function as sum of minterms and simplify.
F =Σ(0,4,5,6,7)=P1 + P'2P'3
Question 232
Let m=(313)​ 4​ and n=(322)​ 4​ . Find the base 4 expansion of m+n.
A
(635)​ 4
B
(32312)​ 4
C
(21323)​ 4
D
(1301)​ 4
       Digital-Logic-Design       Number-Systems       UGC NET CS 2017 Nov- paper-2
Question 232 Explanation: 
In this problem, they are asking to find (m+n)​ 4
→ We are using addition for decimal number system. But in this problem m and n values are base 4. So, we can’t add directly.
Step-1: We have to perform base 4 into decimal values of m and n.
m = 3*42 + 1*41 + 3*40
m = 48 + 4 + 3
m = 55
n= 3*42 + 2*41 +2*40
n= 48 + 8 +2
n= 58
Step-2: The resultant decimal values should perform addition.
m+n = 55 + 58
m+n = 113
Step-3: Finally we have to convert decimal value into base 4 value.
(1301)4
Question 233
Consider the graph given below :

Use Kruskal’s algorithm to find a minimal spanning tree for the graph. The List of the edges of the tree in the order in which they are chosen is?
A
AD, AE, AG, GC, GB, BF
B
GC, GB, BF, GA, AD, AE
C
GC, AD, GB, GA, BF, AE
D
AD, AG, GC, AE, GB, BF
       Digital-Logic-Design       Boolean-Algebra       UGC NET CS 2017 Nov- paper-2
Question 233 Explanation: 
Kruskal’s algorithm will sort all edge weight first and according to spanning tree rules it construct Minimum cost spanning tree.
Here, some edges have same weight. This situation, we can get many number of spanning trees.
We have to connect strictly below order.
Note: DB not given edge weight. GC, AD, BG, AE, BF
Edge weight 2= AD or GC
Edge weight 3= AG or GB
Edge weight 4= AE or DG or BC or BF
Edge weight 5= ED or CF
Edge weight 6: AC
Question 234
The Boolean function with the Karnaugh map
A
(A+C).D+B
B
(A+B).C+D
C
(A+D).C+B
D
(A+C).B+D
       Digital-Logic-Design       K-Map       UGC NET CS 2017 Nov- paper-2
Question 234 Explanation: 
B + DA + CD
We can write into (A + C)・D + B
Question 235
A binary 3 bit down counter uses J-K flip-flops, FF​ i​ with inputs J​ i​ , K​ i​ and outputs Q​ i​ , i=0,1,2 respectively. The minimized expression for the input from following, is
I. J​ 0​ = K​ 0​ = 0
II. J​ 0​ = K​ 0​ = 1
III. J​ 1​ = K​ 1​ = Q​ 0
IV. J​ 1​ = K​ 1​ =Q’0
V. J​ 2​ = K​ 2​ = Q​ 1​ Q​ 0
VI. J​ 2​ = K​ 2​ = Q’​ 1​ Q’​ 0
A
I,III,V
B
I,IV,VI
C
II,III,V
D
II,IV,VI
       Digital-Logic-Design       Sequential-Circuits       UGC NET CS 2017 Jan -paper-2
Question 235 Explanation: 
In a JK flip-flop, Qn=Q(bar) iff J=K=1.
State sequence of down counter is as follows:
Question 236
Convert the octal number 0.4051 into its equivalent decimal number.
A
0.5100098
B
0.2096
C
0.52
D
0.4192
       Digital-Logic-Design       Number-Systems       UGC NET CS 2017 Jan -paper-2
Question 236 Explanation: 
Question 237
The hexadecimal equivalent of the octal number 2357 is :
A
2EE
B
2FF
C
4EF
D
4FE
       Digital-Logic-Design       Number-Systems       UGC NET CS 2017 Jan -paper-2
Question 237 Explanation: 
Step-1: Convert octal number into binary number
(2357)​ 8​ = (010 011 101 111)​ 2
Step-2: Divide 4 bits from LSB then will get hexadecimal number
0100 1110 1111
2 E F
(2EF)​ 16​ = (2357)​ 8
Question 238
If X is a binary number which is power of 2, then the value of X & (X – 1) is :
A
11....11
B
00.....00
C
100.....0
D
000......1
       Digital-Logic-Design       Number-Systems       UGC NET CS 2017 Jan -paper-2
Question 238 Explanation: 
Given data,
→ X is binary number which is power of 2. It means, we have to take powers of 2 numbers only.
Ex: 1,2,4,8,16,32,..,
Let X=4
X=4 equivalent binary number is 100
X-1=3 equivalent binary number is 011
100
011
-----
000 (AND operation)
-----
Ex-2:
X=8 and X-1=7
8 binary value is
1000
7 binary number is 0111
--------
0000(AND operation)
--------
So, Option B is correct answer.
Question 239
The Boolean function [~(~p ∧ q) ∧ ~( ~p ∧ ~q)] ∨ (p ∧ r) is equal to the Boolean function:
A
q
B
p ∧ r
C
p ∨ q
D
p
       Digital-Logic-Design       Boolean-Algebra       UGC NET CS 2016 Aug- paper-2
Question 239 Explanation: 
Question 240
The octal number 326.4 is equivalent to
A
(214.2)​ 10​ and (D6.8))​ 16
B
(212.5)​ 10​ ​ and (D6.8))​ ​ 16
C
(214.5)​ 10​ and (D6.8))​ ​ 16
D
(214.5)​ 10​ and (D6.4))​ ​ 16
       Digital-Logic-Design       Number-Systems       UGC NET CS 2016 Aug- paper-2
Question 240 Explanation: 
(326.4) 8 = ( ?)
Step1: First convert given octal no. to binary number because it will be easier to solve this way.

Step 2: Now convert above binary no. into decimal .
(011010110.100) 2
= ( 1 * 2 7 ) + ( 1 × 2 6 ) + ( 1 × 2 4 ) + ( 1 × 2 2 ) + ( 1 × 2 1 ) · [ 1 × ( 1/2) ]
= (214.5) 10
(326.4) 8 = (?) 16 Step 1: Convert given octal no. into binary no.

Step 2: Now convert above binary no. into decimal .
(011010110.100) 2
= ( 1 * 2 7 ) + ( 1 × 2 6 ) + ( 1 × 2 4 ) + ( 1 × 2 2 ) + ( 1 × 2 1 ) · [ 1 × ( 1/2) ]
= (214.5) 10
(326.4) 8 = (?) 16

Question 241
Which of the following is the most efficient to perform arithmetic operations on the numbers?
A
Sign-magnitude
B
1’s complement
C
2’s complement
D
9’s complement
       Digital-Logic-Design       Number-Systems       UGC NET CS 2016 Aug- paper-2
Question 241 Explanation: 
2’s complement has single representation for zero , but Sign-magnitude, 1’s complement and 9’s complement have two representations for 0 (i.e., both positive zero and negative zero). While doing arithmetic operations like addition or subtraction using 1's complement(or 9's complement), we have to add an extra carry bit, i.e 1 to the result to get the correct answer. 2's complement doesn't require such extra calculation.
Question 242
The Karnaugh map for a Boolean function is given as

The simplified Boolean equation for the above Karnaugh Map is
A
AB + CD + AB’ + AD
B
AB + AC + AD + BCD
C
AB + AD + BC + ACD
D
AB + AC + BC + BCD
       Digital-Logic-Design       K-Map       UGC NET CS 2016 Aug- paper-2
Question 242 Explanation: 
Question 243
Which of the following logic operations is performed by the following given combinational circuit?
A
EXCLUSIVE-OR
B
EXCLUSIVE-NOR
C
NAND
D
NOR
       Digital-Logic-Design       Combinational-Circuits       UGC NET CS 2016 Aug- paper-2
Question 243 Explanation: 

Question 244
Match the following:
A
a-iii, b-ii, c-iv, d-i
B
a-ii, b-iv, c-i, d-iii
C
a-ii, b-i, c-iv, d-iii
D
a-iii, b-i, c-iv, d-ii
       Digital-Logic-Design       Match-the-following       UGC NET CS 2016 Aug- paper-2
Question 244 Explanation: 
a. Controlled Inverter : A circuit that transmits a binary word or its1’s complement.
b. Full adder : A circuit that can add 3 bits. It adds two data bits(ai,bi) and also carry bit(ci).
c. Half adder : A logic circuit that adds 2 bits(ai,bi).
d. Binary adder : A circuit that can add two binary numbers(A and B). Collection of Full adders form a binary adder.
Question 245
Which of the following logic expressions is incorrect?
A
1 ⊕ 0 = 1
B
1 ⊕ 1 ⊕ 1 = 1
C
1 ⊕ 1 ⊕ 0 = 1
D
1 ⊕ 1 = 0
       Digital-Logic-Design       Boolean-Algebra       UGC NET CS 2016 July- paper-2
Question 245 Explanation: 
Here, ⊕ is nothing but Ex-OR operator. The truth table for Ex-OR is

According to truth table,
Option-A is TRUE
Option-B is a 1 ⊕ 1 is 0.
0 ⊕ 1 is 1(TRUE)
Option-C is 1 ⊕ 1 is 0.
0 ⊕ 0 = 0 but given 1. So, FALSE
Option-D is TRUE.
Question 246
The IEEE-754 double-precision format to represent floating point numbers, has a length of _____ bits.
A
16
B
32
C
48
D
64
       Digital-Logic-Design       UGC NET CS 2016 July- paper-2
Question 246 Explanation: 
→ The IEEE-754 double-precision format to represent floating point numbers has a length of 64 bits
→ In the IEEE 754-2008 standard, the 64-bit base-2 format is officially referred to as binary64 called double in IEEE 754-1985.
→ IEEE 754 specifies additional floating-point formats, including 32-bit base-2 single precision and, more recently, base-10 representations.
Question 247
Simplified Boolean equation for the following truth table is:

A
F = yz’ + y’z
B
F = xy’ + x’y
C
F = x’z + xz’
D
F = x’z + xz’ + xyz
       Digital-Logic-Design       Boolean-Algebra       UGC NET CS 2016 July- paper-2
Question 247 Explanation: 
Method-1: Using K-Map

Method-2: Using boolean simplification
= x’y’z+x’yz+xy’z’+xyz’
= x'z(y'+y)+ xz'(y'+y)
= x'z+xz' (Since y'+y=1)
Question 248
The simplified form of a Boolean equation (AB’ + AB’C + AC) (A’C’ + B’) is :
A
AB’
B
AB’C
C
A’B
D
ABC
       Digital-Logic-Design       Boolean-Algebra       UGC NET CS 2016 July- paper-2
Question 248 Explanation: 
(AB’ + AB’C + AC) (A’C’ + B’)
= (AB'+AC) (A'C'+B')
= AB'A'C' + AB'B' + ACA'C' + ACB'
= AB'B' + ACB'
= AB'(C+1)
= AB'
Question 249
In a positive-edge-triggered JK flip-flop, if J and K both are high then the output will be _____ on the rising edge of the clock.
A
No change
B
Set
C
Reset
D
Toggle
       Digital-Logic-Design       Flip-flops       UGC NET CS 2016 July- paper-2
Question 249 Explanation: 
Positive-edge-triggered JK flip-flop is

The Truth Table for the JK Function

When J = 1 and K = 1 , The output continuously Toggles from 1 to 0 and 0 to 1. At the end Output is indeterminate. This condition is called as Race around Condition. This happens when Propagation Delay is less than the Pulse width.
Question 250
Consider the following statements :
(a)Boolean expressions and logic networks correspond to labelled acyclic digraphs.
(b)Optimal boolean expressions may not correspond to simplest networks.
(c)Choosing essential blocks first in a Karnaugh map and then greedily choosing the largest remaining blocks to cover may not give an optimal expression.
Which of these statement(s) is/are correct ?
A
(a) only
B
(b) only
C
(a) and (b)
D
(a), (b) and (c)
       Digital-Logic-Design       K-Map       UGC NET CS 2015 Jun- paper-2
Question 250 Explanation: 
→ An acyclic digraph is a directed graph containing no directed cycles, also known as a directed acyclic graph or a "DAG.",We can represent the boolean expressions and logic networks by using DAG.
→ Karnaugh maps reduce logic functions more quickly and easily compared to Boolean algebra. By reduce we mean simplify, reducing the number of gates and inputs.
Question 251
Consider a full - adder with the following input values:
(a)x = 1, y = 0 and C​ i​ (carry input) = 0
(b)x = 0, y = 1 and C​ i​ = 1 Compute the values of S(sum) and C​ o​ (carry output) for the above input values.
A
S = 1, C​ o​ = 0 and S = 0, C​ o​ = 1
B
S = 1, C​ o​ = 0 and S = 1, C​ o​ = 1
C
S = 1, C​ o​ = 1 and S = 1, C​ o​ = 0
D
S0 = 1, C​ o​ = 1 and S = 1, C​ o​ = 0
       Digital-Logic-Design       Adder       UGC NET CS 2015 Jun- paper-2
Question 251 Explanation: 

For the given x and y values, the correct option is A
Question 252
An example of a binary number which is equal to its 2​ ’s complement is :
A
1100
B
1001
C
1000
D
1111
       Digital-Logic-Design       Number-Systems       UGC NET CS 2004 Dec-Paper-2
Question 252 Explanation: 
Option-A: 1100 convert into 2’s complement is
1100
1’s complement: 0011
2’s complement: 1
--------
0100
Option-B: 1001 convert into 2’s complement is
1001
1’s complement: 0110
2’s complement:
1
--------
0111
---------
Option-C: 1000 convert into 2’s complement is
1000
1’s complement: 0111
2’s complement:
1
--------
1000
---------
Option-D: 1111 convert into 2’s complement is
1111
1’s complement: 0000
2’s complement:
1
--------
0001
---------
So, Option-C is correct answer.
Question 253
An example of a connective which is not associative is :
A
AND
B
OR
C
EX-OR
D
NAND
       Digital-Logic-Design       Logic-Gates       UGC NET CS 2004 Dec-Paper-2
Question 253 Explanation: 
→ ​ OR is associative:
(i) (0 OR 1)OR 1
= 1 OR 1
= 1
(ii). 0 OR (1 OR 1)
= 0 OR 1
= 1
→ NAND is not associative
(i). (0 NAND 1)NAND 1
= 1 NAND 1
= 0
(ii). 0 NAND (1 NAND 1)
= 0 NAND 0
= 1
→ ​ Ex-OR is associative
(i). (0 XOR 1) XOR 1
= 1 XOR 1
= 0
(ii). 0 XOR(1 XOR 1)
= 0 XOR 0
= 0
→ ​ AND is associative:
(i) (0 AND 1) AND 1
= 0 AND 1
= 0
(ii). 0 AND (1 AND 1)
= 0 AND 1
= 0
Question 254
Essential hazards may occur in :
A
Combinational logic circuits
B
Synchronous sequential logic circuits
C
Asynchronous sequential logic circuits working in the fundamental mode
D
Asynchronous sequential logic circuits working in the pulse mode
       Digital-Logic-Design       Sequential-Circuits       UGC NET CS 2004 Dec-Paper-2
Question 254 Explanation: 
→ Essential hazards may occur in asynchronous sequential logic circuits working in the fundamental mode.
→ Asynchronous circuits is called essential hazard ​ is caused by unequal delays along two or more paths that originate from the same same input.
→ It​ cannot be corrected by adding redundant gates and it can only be corrected by adjusting the amount of delay in the affected path.
Question 255
The characteristic equation of a T flip-flop is:__[Note: The symbols used have the usual meaning]
A
Q​ n+1​ =T Q n​ + T Q​ n
B
Q​ n+1​ =T+Q​ n
C
Q​ n+1​ =TQ​ n
D
Q​ n+1​ = T Q n
       Digital-Logic-Design       Sequential-Circuits       UGC NET CS 2004 Dec-Paper-2
Question 255 Explanation: 
T-Flip flop Truth Table:

T-Flip-Flop Characteristic Table:

T-Flip-Flop Characteristic equation:
Q​ next​ = TQ' + T'Q
Question 256
Which of the following is divisible by 4 ?
A
100101100
B
1110001110001
C
11110011
D
10101010101010
       Digital-Logic-Design       Number-Systems       UGC NET CS 2005 Dec-Paper-2
Question 256 Explanation: 
Option-A: (100101100)​ 2​ = (300)​ 10
300 is divisible by 4
Option-B: (1110001110001)​ 2​ = (7281)​ 10
7281 is not divisible by 4
Option-C: (11110011)​ 2​ = (243)​ 10
243 is not divisible by 4
Option-D: (10101010101010)​ 2​ = (10,922)​ 10
10,922 is not divisible by 4.
Question 257
A half-adder is also known as :
A
AND Circuit
B
NAND Circuit
C
NOR Circuit
D
EX-OR Circuit
       Digital-Logic-Design       Combinational-Circuit       UGC NET CS 2005 Dec-Paper-2
Question 257 Explanation: 
→ The half adder adds two single binary digits A and B. It has two outputs, sum (S) and carry (C). The carry signal represents an overflow into the next digit of a multi-digit addition. The value of the sum is 2C + S. The simplest half-adder design incorporates an XOR gate for S and an AND gate for C. The Boolean logic for the sum (in this case S) will be A′B + AB′ whereas for the carry (C) will be AB.
Question 258
Consider the following sequence of instructions :
a=a⊕b, b=a⊕b, a=b⊕a
This Sequence
A
retains the value of the a and b
B
complements the value of a and b
C
swap a and b
D
negates values of a and b
       Digital-Logic-Design       Boolean-Expression       UGC NET CS 2005 Dec-Paper-2
Question 258 Explanation: 
⇒ a=a⊕b
⇒ b=a ⊕b
= a⊕b ⊕b (Substitute (1))
= 0 ⊕ b
= b
⇒ a = b⊕a
= b⊕a⊕b (Substitute (1))
= a⊕b⊕b
= a⊕0
= a
Question 259
Consider the following circuit :

to make it a Tautology the ​ ? ​ should be :
A
NAND gate
B
AND gate
C
OR gate
D
EX-OR gate
       Digital-Logic-Design       Logic-Gates       UGC NET CS 2005 Dec-Paper-2
Question 259 Explanation: 
Method 1:
(X+Y) + (XY)’
= X+Y+X’+Y’
= (X+X’)+(Y+Y’)
= 1
Method 2:
Question 260
When an inventor is placed between both inputs of an S-R flip flop, the resulting flip flop is :
A
JK flip-flop
B
D-flip-flop
C
T flip-flop
D
None of these
       Digital-Logic-Design       Sequential-Circuits       UGC NET CS 2005 Dec-Paper-2
Question 260 Explanation: 
Given question is ambiguous. It is not mentioned how the inverter is connected. Placing NOT gate in different positions gives different solutions.
Question 261
(101011)​ 2​ =(53)​ b​ , then ‘b’ is equal to :
A
4
B
8
C
10
D
16
       Digital-Logic-Design       Number-Systems       UGC NET CS 2005 june-paper-2
Question 261 Explanation: 
We are dividing binary number into 3 then
101 011
5 3
(101011)​ 2 = (53)​ 8
Suppose, we are dividing binary digits into 4 then
0010 1011
2 B
So, it is not hexadecimal number.
Question 262
The logic expression x’yz’+x’yz+xyz’+xyz reduces to :
A
x’z
B
xyz
C
y
D
yz
       Digital-Logic-Design       Boolean-Expression       UGC NET CS 2005 june-paper-2
Question 262 Explanation: 
We can use two methods to solve this problem.
Method-1 using K-Maps:

Method-2 using boolean simplification:
x’yz’+x’yz+xyz’+xyz
= x’y(z’+z)+xy(z’+z)
= x’y + xy
= y(x’+x)
= y
Question 263
Which of the following binary number is the same as its 2’s complement :
A
1010
B
0101
C
1000
D
1001
       Digital-Logic-Design       Number-Systems       UGC NET CS 2005 june-paper-2
Question 263 Explanation: 
Option-A: 1010 convert into 2’s complement is
1010
1’s complement: 0101
2’s complement: 1
--------
0110
--------- Option-B: 0101 convert into 2’s complement is
0101
1’s complement: 1010
2’s complement: 1
--------
1011
---------
Option-C: 1000 convert into 2’s complement is
1000
1’s complement: 0111
2’s complement: 1
--------
1000
---------
Option-D: 1001 convert into 2’s complement is
1001
1’s complement: 0110
2’s complement: 1
--------
0111
---------
So, Option-C is correct answer.
Question 264
Identify the logic function performed by the circuit shown
A
Exclusive-OR
B
AND
C
Exclusive-NOR
D
NOR
       Digital-Logic-Design       Logic-Gates       UGC NET CS 2005 june-paper-2
Question 264 Explanation: 
Question 265
The hexadecimal equivalent of (10111)​ 2​ ×(1110)​ 2 is :
A
150
B
241
C
142
D
101011110
       Digital-Logic-Design       Number-Systems       UGC NET CS 2006 Dec-paper-2
Question 265 Explanation: 
Step-1: First convert binary number into decimal number
(10111)​ 2​ = (23)​ 10
(1110)​ 2​ = (14)​ 10
Step-2: Perform multiplication 23*14=(322)​ 10
Step-3: Convert (322)​ 10​ into hexadecimal number (322)​ 10​ = (142)​ 16
Question 266
An example of a self complementing code is :
A
8421 code
B
Gray code
C
Excess-3 code
D
7421 code
       Digital-Logic-Design       Number-Systems       UGC NET CS 2006 Dec-paper-2
Question 266 Explanation: 
→ Excess-3 code is also called Self-Complementing Code. Because 1’s complement of excess-3 number is equivalent to 9’s complement of corresponding decimal digit.
→ In excess-3 code, each of the 4-bit number represents decimal digit which is 3 less than actual decimal digit. So the bits have no fixed weight.
→ Excess-3 code is ​ neither​ CRC ​ nor​ Algebraic Code which are used for error detection and/or correction.
Question 267
A sum of products expression can be implemented with __________ logic gates.
A
AND − OR
B
NAND − OR
C
AND − NOT
D
OR − AND
       Digital-Logic-Design       Logic-Gates       UGC NET CS 2006 Dec-paper-2
Question 267 Explanation: 
A sum of products expression can be implemented with AND-OR logic gates.
Ex: (AB)+(BC)+(CD)
Question 268
The characteristic equation of the D flip-flop is :
A
Not option given
B
Q=D
C
Q=1
D
Q=0
E
Q​ t+1​ =D
       Digital-Logic-Design       Sequential-Circuits       UGC NET CS 2006 Dec-paper-2
Question 268 Explanation: 
D flip flop characteristic equation truth table:

Q​ t+1​ = DQ' + DQ
Q​ t+1​ =D
Question 269
The number of 1​ ’s present in the binary representation of (3*512 + 7*64 +5*8 +3)​ 10​ is :
A
8
B
9
C
10
D
11
       Digital-Logic-Design       Number-Systems       UGC NET CS 2006 June-Paper-2
Question 269 Explanation: 
(3*512 + 7*64 +5*8 +3) =2027
(2027)​ 10​ = (111 1110 1011)​ 2
Here, total number of 1’s are 9.
Question 270
Which of the following expression removes static hazard from a two level AND - OR gate implementation of xy +zx’
A
xy +zx’
B
xy + zx’+ wxy
C
xy +zx’ +yz
D
xy + zx’ +wz
       Digital-Logic-Design       Combinational-Circuit       UGC NET CS 2006 June-Paper-2
Question 270 Explanation: 
→ A static hazard occurs if a circuit produces incorrect output value momentarily before stabilizing to its correct value.
→ Generally Hazard occurs due to different delays in different paths of the circuit.
→ In the expression xy +zx’ the variable x is in true form in one term(xy) and in complement in other term(zx').
→ Delay occurs due to the presence of NOT gate. If input xyz=111 then output is 1. If input xyz=011 then output stays momentarily in state 0 then settles in state 1.
→ Adding the term yz(select y from xy and z from zx') eliminates the hazard.
Question 271
​ In a weighted code with weight 6, 4, 2, -3 the decimal 5 is represented by :
A
0101
B
0111
C
1011
D
1000
       Digital-Logic-Design       Number-Systems       UGC NET CS 2006 June-Paper-2
Question 271 Explanation: 
The decimal value 5 is represented by 1011.
= 6*1 + 4*0 + 2*1 + -3*1
= 6+2-3
=5
Question 272
Upto how many variables, can the Karnaugh map be used ?
A
3
B
4
C
5
D
6
       Digital-Logic-Design       K-Map       UGC NET CS 2006 June-Paper-2
Question 272 Explanation: 
The Karnaugh map provides a simple and straightforward method of minimising boolean expressions. With the Karnaugh map Boolean expressions having up to four and even six variables can be simplified.
Question 273
The range of representable normalized numbers in the floating point binary fractional representation in a 32-bit word with 1-bit sign, 8-bit excess 128 biased exponent and 23-bit mantissa is
A
2​ -128​ to (1 – 2​ –23​ ) * 2​ 127
B
(1 – 2​ –23​ ) * 2​ ​ -127 ​ to 2​ 128
C
(1 – 2​ –23​ ) * 2​ –127​ to 2​ 23>
D
2​ –129​ to (1 – 2​ –23​ ) * 2​ 127
       Digital-Logic-Design       Number-Systems       UGC NET CS 2014 Dec-Paper-2
Question 273 Explanation: 
The range of representable normalized numbers in the floating point binary fractional representation in a 32-bit word with 1-bit sign, 8-bit excess 128 biased exponent and 23-bit mantissa is​ ​ 2 –129 to (1 – 2​ –23​ ) * 2​ 127
Question 274
The BCD adder to add two decimal digits needs minimum of
A
6 full adders and 2 half adders
B
5 full adders and 3 half adders
C
4 full adders and 3 half adders
D
5 full adders and 2 half adders
       Digital-Logic-Design       Number-Systems       UGC NET CS 2014 Dec-Paper-2
Question 274 Explanation: 
→ Each digit is represented by a 4-bit BCD code.
→ To add two 4-bit number, we need 1 Half Adder(to add LSBs) and 3 Full Adders(remaining three bits of both number along with carry bits).
→ To make the resultant Sum as valid BCD sum, we need to add 0110 to the sum.
→ This can be done with 1 Half adder and 2 Full Adder
(Note: LSB bit of 0110 is always zero. So there is no need of ADDER to add LSBs.)
→ Here, Half adder is used to add next significant bits.
Total 5 Full Adders and 2 Half Adders are needed
Question 275
The Excess-3 decimal code is a self-complementing code because
A
The binary sum of a code and its 9’s complement is equal to 9.
B
It is a weighted code
C
Complement can be generated by inverting each bit pattern
D
The binary sum of a code and its 10’s complement is equal to 9
       Digital-Logic-Design       Number-Systems       UGC NET CS 2014 Dec-Paper-2
Question 275 Explanation: 
The Excess-3 decimal code is a self-complementing code because complement can be generated by inverting each bit pattern.
Question 276
How many different truth tables of the compound propositions are there that involve the propositions p & q ?
A
2
B
4
C
8
D
16
       Digital-Logic-Design       Truth-Table       UGC NET CS 2014 June-paper-2
Question 276 Explanation: 
→ The total number of possibilities are 2^4=16. Here, number of different functions will be the number of ways this 4 rows will be assigned values.
Question 277
A Boolean function F is called self-dual if and only if F(x1, x2, … xn) = F(͞x1,͞x2, …͞xn) How many Boolean functions of degree n are self-dual ?
A
2n
B
(2)2^n
C
(2)n^2
D
(2)(2^(n-1))
       Digital-Logic-Design       Boolean-Function       UGC NET CS 2014 June-paper-2
Question 277 Explanation: 
→ Number of possible minterms = 2n.
→ Number of mutually exclusive pairs of minterms = 2n-1.
→ There are 2 choices for each pair i.e., we can choose one of the two minterms from each pair of minterms for the function.
Therefore number of functions = 2*2* …. 2n-1 times.
= 2(2^(n-1))
Question 278
Which of the following statement(s) is (are) not correct ?
i. The 2’s complement of 0 is 0.
ii. In 2’s complement, the left most bit cannot be used to express a quantity.
iii. For an n-bit word (2’s complement) which includes the sign bit, there are 2n–1 positive
integers, 2n+1 negative integers and one 0 for a total of 2n unique states.
iv. In 2’s complement the significant information is contained in the 1’s of positive numbers and 0’s of the negative numbers.
A
i & iv
B
i & ii
C
iii
D
iv
       Digital-Logic-Design       UGC NET CS 2014 June-paper-2
Question 278 Explanation: 
With n-bit 2's complement number we can represent
2n–1 -1 positive integers,
2n-1 negative integers
and
zero.
Total=2n–1 -1+ 2n-1 +1= 2n unique states for 2n unique integers
Question 279
The IEEE single-precision and double-precision format to represent floating-point numbers, has a length of ______ and ______ respectively.
A
8 bits and 16 bits
B
16 bits and 32 bits
C
32 bits and 64 bits
D
64 bits and 128 bits
       Digital-Logic-Design       Number-Systems       UGC NET CS 2013 Sep-paper-2
Question 279 Explanation: 
The IEEE single-precision and double-precision format to represent floating-point numbers, has a length of 32 bits and 64 bits respectively.
Question 280
Which one of the following set of gates is best suited for ‘parity’ checking and ‘parity’ generation ?
A
AND, OR, NOT
B
NAND, NOR
C
EX-OR, EX-NOR
D
None of the above
       Digital-Logic-Design       Logic-Gates       UGC NET CS 2013 Sep-paper-2
Question 280 Explanation: 
‘parity’ checking using EX-OR and ‘parity’ generation using EX-NOR
Example:
Even parity Check using EX-OR

Question 281
If F and G are Boolean functions of degree n. Then, which of the following is true ?
A
F ≤ F + G and F G ≤ F
B
G ≤ F + G and F G ≥ G
C
F ≥ F + G and F G ≤ F
D
G ≥ F + G and F G ≤ F
       Digital-Logic-Design       Boolean-Function       UGC NET CS 2013 Sep-paper-2
Question 281 Explanation: 
Given data,
-- F and G are boolean functions of degree n.
Step-1: Let n=4
Using n=22^n formula, we can find number of boolean functions
= 22^4
= 256
Stp-2: First consider F4→ F & G4→ G
F having 256 boolean functions and G having 256 boolean functions.
Option-A: F + G= 512 boolean functions and F*G= 14336 boolean functions.
F ≤ F + G and F G ≤ F FALSE because F G ≤ F is wrong
Option-B: G ≤ F + G and F G ≥ G TRUE
F + G= 512 boolean functions and F*G= 14336 boolean functions.
Option-C: F ≥ F + G and F G ≤ F FALSE because both are wrong
Option-D: G ≥ F + G and F G ≤ F FALSE because F G ≤ F is wrong.
Question 282
What type of logic circuit is represented by the figure shown below ?
A
XOR
B
XNOR
C
XAND
D
XNAND
       Digital-Logic-Design       Logic-Gates       UGC NET CS 2013 Sep-paper-2
Question 282 Explanation: 

Question 283
Consider the circuit shown below. In a certain steady state, Y is at logical ‘1’. What are possible values of A, B, C ?
A
A = 0, B = 0, C = 1
B
A = 0, B = C = 1
C
A = 1, B = C = 0
D
A = B = 1, C = 1
E
A and D correct
       Digital-Logic-Design       Logic-Gates       UGC NET CS 2012 Dec-Paper-2
Question 283 Explanation: 
The output f of the circuit is given as feedback input which should always be 1.
From the given circuit
f= (A+B')C (Assuming that feedback input is 1)
So, the output remains 1 iff C=1 and (A+B')=1.
A=1, B=0, C=1
A=1, B=1, C=1
A=0, B=0, C=1
Hence option A and D are correct.
Question 284
Identify the operation which is commutative but not associative ?
A
OR
B
NOR
C
EX-OR
D
NAND
E
None of the above
       Digital-Logic-Design       Boolean-Operator       UGC NET CS 2012 Dec-Paper-2
Question 284 Explanation: 
OR is associative:
(i) (0 OR 1)OR 1
= 1 OR 1
= 1
(ii). 0 OR (1 OR 1)
= 0 OR 1
= 1
NAND is not associative
(i). (0 NAND 1)NAND 1
= 1 NAND 1
= 0
(ii). 0 NAND (1 NAND 1)
= 0 NAND 0
= 1
Ex-OR is associative
(i). (0 XOR 1) XOR 1
= 1 XOR 1
= 0
(ii). 0 XOR(1 XOR 1)
= 0 XOR 0
= 0
NOR is Not associative:
(i) (0 NOR 1) NOR 1
= 0 NOR 1
= 0
(ii). 0 NOR(1 NOR 1)
= 0 NOR 0
= 1
Note: Every logic gate is commutative.
Question 285
Consider a Boolean function of ‘n’ variables. The order of an algorithm that determines whether the Boolean function produces a output 1 is :
A
Logarithmic
B
Linear
C
Quadratic
D
Exponential
       Digital-Logic-Design       Boolean-Function       UGC NET CS 2018 JUNE Paper-2
Question 285 Explanation: 

Set 1 have “n” variables and each variable in set 1 can be mapped with one boolean value in
set 2 i.e. each variable in set 1 have 2 choices and we have “n” such variables in set 1.
→ So, total number of choices we get maximum 2​ n​ . It means exponential.
Question 286
In RS flip-flop, the output of the flip-flop at time (t+1) is same as the output at time t, after the occurrence of a clock pulse if :
A
S=R=1
B
S=0, R=1
C
S=1, R=0
D
S=R=0
       Digital-Logic-Design       Flip-Flops       UGC NET CS 2018 JUNE Paper-2
Question 286 Explanation: 
Characteristic table of SR flip-flop where the Next State remains same when S=R=0
Question 287
Match the terms in List - I with the options given in List - II :
A
(a)-(ii), (b)-(i), (c)-(iii)
B
(a)-(ii), (b)-(iii), (c)-(i)
C
(a)-(ii), (b)-(i), (c)-(iv)
D
(a)-(iv), (b)-(ii), (c)-(i)
       Digital-Logic-Design       Match-The-Following       UGC NET CS 2018 JUNE Paper-2
Question 287 Explanation: 
Decoder:
Question 288
What does the following logic diagram represent ?
A
Synchronous Counter
B
Ripple Counter
C
Combinational Circuit
D
Mod 2 Counter
       Digital-Logic-Design       Combinational-Circuits       UGC NET CS 2018 JUNE Paper-2
Question 288 Explanation: 
→ A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock.
→ All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are also called ripple-counters because of the way the clock pulse ripples it way through the flip-flops.
→ The MOD of the ripple counter or asynchronous counter is 2​ n​ if n flip-flops are used.
Question 289
The hexadecimal equivalent of the binary integer number 110101101 is :
A
D24
B
1 B D
C
1 A E
D
1 A D
       Digital-Logic-Design       Number-System       UGC NET CS 2018 JUNE Paper-2
Question 289 Explanation: 
(110101101) 2 = ( ? ) 16 2 4 = 1 6
So, 4-bits in binary will represent one integer in Hexadecimal.
So,
Question 290
​ Perform the following operation for the binary equivalent of the decimal numbers (-14)10+(15)10 The solution in 8 bit representation is :
A
11100011
B
00011101
C
10011101
D
11110011
       Digital-Logic-Design       Number-System       UGC NET CS 2018 JUNE Paper-2
Question 290 Explanation: 
(− 1 4) 10 + (− 1 5) 10 = (− 2 9) 10

(29) 10 = (11101) 2
(29) 10 in 8-bit representation = (00011101) 2

(− 2 9) 10 = (00011101) 2
Question 291
Match the items in List - I and List - II :
A
(a)-(ii), (b)-(i), (b)-(iv)
B
(a)-(ii), (b)-(iv), (b)-(iii)
C
(a)-(iii), (b)-(i), (b)-(ii)
D
(a)-(iii), (b)-(iv), (b)-(ii)
       Digital-Logic-Design       Match-the-following       UGC NET CS 2018 JUNE Paper-2
Question 291 Explanation: 
Maskable Interrupt : Maskable Interrupts are those which can be masked/delayed when a higher priority interrupt occurs.
Exception : Exception are the unplanned interrupts that occur while executing a program. Divide by zero is an example of Exception.
Synchronous: Synchronous clocks will regularly synchronize their time with a master clock. The connection can be direct (wired), or over the air (radio, wifi or similar). The connections can be at a regular intervals, on demand or a mix.
Question 292
The dual of a Boolean expression is obtained by interchanging
A
Boolean sums and Boolean products
B
Boolean sums and Boolean products or interchanging 0’s and 1’s
C
Boolean sums and Boolean products and interchanging 0’s & 1’s
D
Interchanging 0’s and 1’s
       Digital-Logic-Design       Boolean-Expression       UGC NET CS 2013 Dec-paper-2
Question 292 Explanation: 
→ The dual of a Boolean expression is obtained by interchanging boolean sums and boolean products and interchanging 0’s & 1’s.
→ Dual of a Boolean expressions are generated by simply replacing AND(product) with OR(sum) and OR(sum) with AND(product).
→ Even compliments themselves are unaffected, where as the complement of an expression is the negation of the variables with the replacement of AND(product) with OR(sum) and vice versa.
Example: A+B
Complement: AB
Dual: AB
Question 293
Given that (292)10 = (1204)x in some number system x. The base x of that number system is
A
2
B
8
C
10
D
None of the above
       Digital-Logic-Design       Number-Systems       UGC NET CS 2013 Dec-paper-2
Question 293 Explanation: 
Option-A: It is false because it is equivalent to (292)10 =(100100100)2 Option-B: It is false because it is equivalent to (292)10 =(444)8 Option-B: It is false because it is equivalent to (292)10 =(292)10 So, option-D is the correct answer. The actual x value is 6.