Computer-Organization

Question 1
 Consider the following instruction sequence where registers R1, R2 and R3 are general purpose and MEMORY[X] denotes the content at the memory location X.

Assume that the content of the memory location 5000 is 10, and the content of the register R3 is 3000. The content of each of the memory locations from 3000 to 3010 is 50. The instruction sequence starts from the memory location 1000. All the numbers are in decimal format. Assume that the memory is byte addressable.
After the execution of the program, the content of memory location 3010 is _______
A
50
Question 1 Explanation: 

Register R1 will get value 10 from location 5000. So the loop in the given program will run for 10 times as the loop condition is based on ‘Dec R1’. When R1 is 0 then the loop terminates.

 

In these 10 iterations of the loop contents of memory locations 3000 to 3009 are changed as initial value of R3 is 3000 and in each iteration we update M[R3] ← R2 and the value of R3 is incremented to the next location 3001, 3002 etc.

 

But the value in location 3010 is unchanged and it will be the same as the initial value which is 50.

Question 2
A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds. The registers that are used between the pipeline stages have a delay of 5 nanoseconds each. The total time to execute 100 independent instructions on this pipeline, assuming there are no pipeline stalls, is ______ nanoseconds.
A
17160
Question 2 Explanation: 

In a pipeline with k-stages, number of cycles to execute n instructions = (k+n-1) cycles

Here k = 5, n = 100

So we need a total of 5+100-1 = 104 cycles.

Clock cycle time = maximum of all stage delays + register delay

                           = max(150, 120, 150, 160, 140) + 5 = 160+5 = 165 ns

 

Time in ns = 104*165 = 17160ns

Question 3
Consider a computer system with a byte-addressable primary memory of size 232bytes. Assume the computer system has a direct-mapped cache of size 32 KB (1 KB = 210bytes), and each cache block is of size 64 bytes. The size of the tag field is ______ bits.
A
17
Question 3 Explanation: 

Given that the main memory is 2^32 bytes. So the physical address is 32 bits long.

 

Since it is a direct mapped cache the physical address is divided into  fields as (TAG, LINE, OFFSET).

 

Cache size is 32KB = 2^15 Bytes. 

Block size is 64 bytes = 2^6 bytes, so OFFSET needs 6 bits.

 

Number of blocks in the cache = 2^15//2^6 = 2^9, So LINE number needs 9 bits.

 

TAG bits = 32 - 9 - 6 = 17 bits.

Question 4

A single instruction to clear the lower four bits of the accumulator in 8085 assembly language?

A
XRI OFH
B
ANI FOH
C
XRI FOH
D
ANI OFH
Question 4 Explanation: 
Here, we use the AND as a accumulator with immediate. F leaves the high nibble whatever it is, 0 clears the lower nibble.
→ The XOR's don't reliably clear random bits and ANI OF clears the upper nibble, not the lower nibble.
Question 5

In a vectored interrupt

A
the branch address is assigned to a fixed location in memory
B
the interrupt source supplies the branch information to the processor through an interrupt vector
C
the branch address is obtained from a register in the processor
D
none of the above
Question 5 Explanation: 
A vectored interrupt is a processing technique in which the interrupting device directs the processor to the appropriate interrupt service routine vector.
Question 6

The principle of locality justifies the use of

A
interrupts
B
DMA
C
Polling
D
Cache Memory
Question 6 Explanation: 
The locality of reference is also known as principle of locality.
→ The things which are used more frequently those are stored in locality of reference.
→ For this purpose we use the cache memory.
Question 7

What are x and y in the following macro definition?

 macro Add x,y
 Load y
 Mul x
 Store y
 end macro  
A
Variables
B
Identifiers
C
Actual parameters
D
Formal parameters
Question 7 Explanation: 
Formal arguments (or) formal parameters is a special kind of variables used in subroutine to refer to one of pieces of data provided as input to the subroutine.
Question 8

The capacity of a memory unit is defined by the number of words multiplied by the number of bits/word. How many separate address and data lines are needed for a memory of 4K × 16?

A
10 address, 16 data lines
B
11 address, 8 data lines
C
12 address, 16 data lines
D
12 address, 12 data lines
Question 8 Explanation: 
ROM memory size = 2m × n
m = no. of address lines
n = no. of data lines
Given, 4K × 16 = 212 × 16
Address lines = 12
Data lines = 16
Question 9

A computer system has a 4K word cache organized in block-set-associative manner with 4 blocks per set, 64 words per block. The number of its in the SET and WORD fields of the main memory address format is:

A
15, 40
B
6, 4
C
7, 2
D
4, 6
Question 9 Explanation: 
No. of sets = 4K/ (64×4) = 212/ 28 = 24
So we need 4 set bits.
And,
64 words per block means WORD bit is 6-bits.
So, answer is option (D).
Question 10

If the overhead for formatting a disk is 96 bytes for 4000 byte sector,
(a) Compute the unformatted capacity of the disk for the following parameters:

 Number of surfaces: 8
 Outer diameter of the disk: 12 cm
 Inner diameter of the disk: 4 cm
 Inter track space: 0.1 mm 
 Number of sectors per track: 20 

(b) if the disk in (a) is rotating at 360 rpm, determine the effective data transfer rate which is defined as the number of bytes transferred per second between disk and memory.

A
Theory Explanation.
Question 11

The following is an 8085 assembly language program:

     MVI B, OAH
     MVI A, 05H
     LXI H, IC40H
     CALL SUB
     HLT
 SUB CMP M
     RZ
     INX H
     DCR B
     JNZ SUB
     RET 

(a) What does the program do?
(b) What are the contents of registers A and B initially?
(c) What are the contents of HL register pair after the execution of the program?

A
Theory Explanation.
Question 12

A sequence of two instructions that multiplies the contents of the DE register pair by 2 and stores the result in the HL register pair (in 8085 assembly language) is:

A
XCHG and DAD B
B
XTHL and DAD H
C
PCHL and DAD D
D
XCHG and DAD H
Question 13

Consider the following statements.

    I. Daisy chaining is used to assign priorities in attending interrupts.
    II. When a device raises a vectored interrupt, the CPU does polling to identify the source of the interrupt.
    III. In polling, the CPU periodically checks the status bits to know if any device needs its attention.
    IV. During DMA, both the CPU and DMA controller can be bus masters at the same time.

Which of the above statements is/are TRUE?

A
I and IV only
B
I and II only
C
III only
D
I and III only
Question 13 Explanation: 
Statement-I is true as daisy chaining is used to assign priorities in attending interrupts.
Statement-II is false as vectored interrupt doesn’t involve polling but non-vectored interrupt involves polling.
Statement-III is true as polling means that CPU periodically checks the status bits to know if any device needs attention.
Statement-IV is false as during DMA only one of the CPU or DMA can be bus master at a time.
Question 14

A direct mapped cache memory of 1 MB has a block ize of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the first word of a block from the main memory, while each subsequent word takes 5 ns. The word size is 64 bits. The average memory access time in ns (round off to 1 decimal place) is _____.

A
13.5
Question 14 Explanation: 
Cache access time = 3 ns
Hit ratio of cache = 0.94
Word size is 64 bits = 8 bytes.
  Cache line size = 256 bytes = 32 words
Main memory access time = 20ns(time for first word) + 155ns(time for remaining 31 words, 31*5 = 155ns) = 175 ns
Average access time = h1*t1 + (1-h1)(t1+t2) = t1 +(1-h1)t2
⇒ 3 + (0.06)(175) = 13.5 ns
Question 15

Consider the following data path diagram.

Consider an instruction: R0 ← R1 + R2. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts r and w indicate read and write operations, respectively.

1. R2r, TEMP1r, ALUadd, TEMP2w
2. R1r, TEMP1w
3. PCr, MARw, MEMr
4. TEMP2r, ROw
5. MDRr, IRw 

Which one of the following is the correct order of execution of the above steps?

A
3, 5, 1, 2, 4
B
3, 5, 2, 1, 4
C
1, 2, 4, 3, 5
D
2, 1, 4, 5, 3
Question 15 Explanation: 
To execute the given instruction R0 ← R1 + R2.
First the PC value has to be moved into MAR (step-3 from the given sequence), then the instruction has to be fetched(step-5 from the given sequence). Then Temp1 is loaded with the value of R1 (step-2 from the given sequence), then the addition operation is performed by accessing the R2 value directly and adding it to Temp1 value and storing the result in Temp2 (step-1 from the given sequence).
Finally the result from Temp2 is stored in R0 (step-4 from the given sequence).
Hence the correct sequence is (3, 5, 2, 1, 4).
Question 16

Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined processor at 2 GHz. In a given program, assume that 30% are memory instructions, 60% are ALU instructions and the rest are branch instructions. 5% of the memory instructions cause stalls of 50 clock cycles each due to cache misses and 50% of the branch instructions cause stalls of 2 cycles each. Assume that there are no stalls associated with the execution of ALU instructions. For this program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to 2 decimal places) is _____.

A
2.16
Question 16 Explanation: 
In the non-pipelined architecture the clock cycle time = 1/(2.5)G = 0.4 ns
It is given that each instruction takes 5 clock cycles to execute in the non-pipelined architecture, so time taken to execute each instruction = 5 * 0.4 = 2ns
In the pipelined architecture the clock cycle time = 1/2G = 0.5 ns
In the pipelined architecture there are stalls due to memory instructions and branch instructions.
In the pipeline, the updated clocks per instruction CPI = (1 + stall frequency due to memory operations * stalls of memory instructions + stall frequency due to branch operations * stalls due to branch instructions)
Out of the total instructions , 30% are memory instructions. Out of those 30%, only 5% cause stalls of 50 cycles each.
Stalls per instruction due to memory operations = 0.3*0.05*50 = 0.75
Out of the total instructions 10% are branch instructions. Out of those 10% of instructions 50% of them cause stalls of 2 cycles each.
Stalls per instruction due to branch operations = 0.1*0.5*2 = 0.1
The updated CPI in pipeline = 1 + 0.75 + 0.1 = 1.85
The execution time in the pipeline = 1.85 * 0.5 = 0.925 ns
The speed up = Time in non-pipelined architecture / Time in pipelined architecture = 2 / 0.925 = 2.16
Question 17

A computer system with a word length of 32 bits has a 16 MB byte-addressable main memory and a 64 KB, 4-way set associative cache memory with a block size of 256 bytes. Consider the following four physical addresses represented in hexadecimal notation.

 A1 = 0x42C8A4,  A2 = 0x546888,  A3 = 0x6A289C,  A4 = 0x5E4880 

Which one of the following is TRUE?

A
A1 and A4 are mapped to different cache sets.
B
A1 and A3 are mapped to the same cache set.
C
A3 and A4 are mapped to the same cache set.
D
A2 and A3 are mapped to the same cache set.
Question 17 Explanation: 
Main memory is 16MB in size.
The word length is given as 32 bits and the physical addresses mentioned are all contain 6 hexadecimal digits, so the the physical address is 32 bits long.
Block size is 256 bytes, block offset = 8 bits as it is a byte addressable memory.
Cache size = 64KB
Number of blocks in the cache = 64KB/256B = 256
It is a 4-way set associative cache, so no. of sets in the cache = 256/4 = 64 = 26
In the physical address we need 6 bits for the SET number.
TAG bits = 32 - 6 - 8 = 18
So the 32 bits physical address is divided as (18 TAG bits + 6 SET number bits + 8 OFFSET bits)
Since in all the options we are asked about SET numbers of the given addresses, we need to find the SET number of each of the addresses.
A1 = 0x42C8A4, here SET number is (00 1000) which includes the last 2 bits of C(1100) and binary representation of 8 (1000).
A2 = 0x546888, here SET number is (10 1000) which includes the last 2 bits of 6(0110) and binary representation of 8 (1000).
A3 = 0x6A289C here SET number is (10 1000) which includes the last 2 bits of 2(0010) and binary representation of 8 (1000).
A4 = 0x5E4880 here SET number is (00 1000) which includes the last 2 bits of 4 (0100) and binary representation of 8 (1000).
From the given options option-4 is TRUE as A2, A3 are mapped to the same cache SET.
Question 18

A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a 4-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are 8 distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _____.

A
14
Question 18 Explanation: 
Instruction is of size 16-bits.
All possible binary combinations = 216
There are 64 registers, so no. of bits needed to identify a register = 6
I-type instruction has (Opcode+Register+4-bit immediate value). There are 8 distinct I-type instructions.
All the binary combinations possible with the I-type instructions are = 8*26*24 = 213
R-type instructions have 2 register operands.
Let x be the number of R-type instructions.
All the possible binary combinations of R-type instructions = x*26*26 = x*212
The sum of I-type and R-type binary combinations should be equal to 216.
x*212 + 213 = 216
212 (x+2) = 216
x+2 = 24
x = 16 - 2 = 14
Question 19

Relative mode of addressing is most relevant to writing

A
coroutines
B
position – independent code
C
shareable code
D
interrupt handlers
Question 19 Explanation: 
The main advantage of PC- relative addressing is that code may be position independent, i.e., it can be loaded anywhere in memory without the need to adjust any address.
Question 20

Number of machine cycles required for RET instruction in 8085 microprocessor is

A
1
B
2
C
3
D
5
Question 20 Explanation: 
1 for instruction fetch.
2 for stack operation.
Total no. of cycles = 2+1 = 3
Question 21

For the daisy chain scheme of connecting I/O devices, which of the following statements is true?

A
It gives non-uniform priority to various devices.
B
It gives uniform priority to all devices
C
It is only useful for connecting slow devices to a processor device.
D
It requires a separate interrupt pin on the processor for each device.
Question 21 Explanation: 
Daisy chaining technique tells the processor in which order the interrupt should be handle by providing priority devices.
→ In this all devices connected serially.
→ High priority devices placed first, followed by low priority devices.
Question 22

A micro program control unit is required to generate a total of 25 control signals. Assume that during any microinstruction, at most two control signals are active. Minimum number of bits required in the control word to generate the required control signals will be

A
2
B
2.5
C
10
D
12
Question 22 Explanation: 
To generate 1 out of 25 different control signals we need 5 bits. But at any time atmost 2 signals can be active. So control word length
= 5+5
= 10 bits
Question 23

An 8052 based system has an output port with address 00H. Consider the following assembly language program.

     ORG    0100H
     MVI    A, 00H
     LXI    H, 0105H
     OUT    00H
     INR    A
     PCHL
     HLT   

(a) What does the program do with respect to the output port 00H?
(b) Show the wave forms at the three least significant bits of the port 00H.

A
Theory Explanation.
Question 24

Consider the following program in pseudo-pascal syntax. What is printed by the program if parameter a in procedure test 1 is passed as
(i) call-by-reference parameter
(ii) call-by-value-result parameter

     program Example (input, output)
     var b: integer;
     procedure test2:
     begin b:=10; end
    procedure test1 (a:integer):
     begin 	a:=5;
                writeln ('point 1: ', a, b);
                test2;
                writeln ('point 2: ', a, b);
     end
     begin(*Example*)
     b:=3; test1(b);
     writeln('point3:', b);
     end 
A
Theory Explanation.
Question 25

A hard disk is connected to a 50 MHz processor through a DMA controller. Assume that the initial set-up of a DMA transfer takes 1000 clock cycles for the processor, and assume that the handling of the interrupt at DMA completion requires 500 clock cycles for the processor. The hard disk has a transfer rate of 2000 Kbytes/sec and average block transferred is 4 K bytes. What fraction of the processor time is consumed by the disk, if the disk is actively transferring 100% of the time?

A
Theory Explanation.
Question 26

A computer system has a three level memory hierarchy, with access time and hit ratios as shown below:

(a) What should be the minimum sizes of level 1 and 2 memories to achieve an average access time of less than 100 nsec?
(b) What is the average access time achieved using the chosen sizes of level 1 and level 2 memories?

A
Theory Explanation.
Question 27

RST 7.5 interrupt in 8085 microprocessor executes the interrupt service routine from interrupt vector location

A
0000H
B
0075H
C
003CH
D
0034H
Question 27 Explanation: 
RST7.5 then location is = 7.5*8 = 60 (8085 is 8 bit processor)
→ 60 in hexa decimal is 003CH.
Question 28

Purpose of a start bit in RS 232 serial communication protocol is

A
to synchronize receiver for receiving every byte
B
to synchronize receiver for receiving a sequence of bytes
C
a parity bit
D
to synchronize receiver for receiving the last byte
Question 28 Explanation: 
RS-232 needs a start before each byte transmission for synchronization.
Question 29

The correct matching for the following pairs is

(A) DMA I/O                    (1) High speed RAM
(B) Cache                      (2) Disk
(C) Interrupt I/O              (3) Printer
(D) Condition Code Register    (4) ALU 
A
A – 4 B – 3 C – 1 D – 2
B
A – 2 B – 1 C – 3 D – 4
C
A – 4 B – 3 C – 2 D – 1
D
A – 2 B – 3 C – 4 D – 1
Question 29 Explanation: 
DMA I/O → Disk
Cache → High speed RAM
Interrupt I/O → Printer
Condition code register → ALU
Question 30

When an interrupt occurs, an operating system

A
ignores the interrupt
B
always changes state of interrupted process after processing the interrupt
C
always resumes execution of interrupted process after processing the interrupt
D
may change state of interrupted process to 'blocked’ and schedule another process
Question 30 Explanation: 
Option A: Based on the priority.
Option B: Not always.
Option C: Not always. If some high priority interrupt comes during execution of current interrupt then it fails.
Option D: It is True always.
Question 31

The expression (a*b)* c op....
where 'op' is one of '+', '*' and '↑' (exponentiation) can be evaluated on a CPU with a single register without storing the value of (a * b) if

A
‘op’ is ’+’ or ‘*’
B
‘op’ is ’↑’ or ‘*’
C
‘op’ is ’↑’ or ‘+’
D
not possible to evaluate without storing
Question 31 Explanation: 
Lets say, the expression is one of the below:
(a*b)*c + d
(a*b)*c * d
(a*b)*c ∧ d
In any case, brackets has the highest priority always. So I have to compute brackets first. Now, for + and *, I can do the rest of the operation and save results in the same register. But for exponentiation, I have to store the result of a*b, then do the computation of c∧d, then multiply these two results.
Hence, (A) is correct.
Question 32

Contents of A register after the execution of the following 8085 microprocessor program is

MVI  A, 55 H
MVI  C, 25 H
ADD  C
DAA 
A
7AH
B
80H
C
50H
D
22H
Question 32 Explanation: 
Note: Out of syllabus.
Question 33

A micro instruction into be designed to specify

    (a) none or one of the three micro operations of one kind and
    (b) none or upto six micro operations of another kind

The minimum number of bits in the micro-instruction is

A
9
B
5
C
8
D
None of the above
Question 33 Explanation: 
(a) This is a vertical microprogramming because at any given time atmost one micro-operations will be activated.
So, no. of bits required
⌈log2 (3)⌉ = 2
(b) This is a horizontal micro-programming because at any given time atmost six micro-operations will be activated.
So, no. of bits required = 6
So, total minimum no. of bits required = 6+2 = 8
Question 34

State whether the following statements are TRUE or FALSE with reason:

The data transfer between memory and I/O devices using programmed I/O is faster than interrupt-driven I/O.
A
True
B
False
Question 34 Explanation: 
In programmed I/0, no interface register is there but in interrupt driven I/0 interface register is used. So interrupt driven is faster than programmed I/0.
Question 35

State whether the following statements are TRUE or FALSE with reason:

The flags are affected when conditional CALL or JUMP instructions are executed.
A
True
B
False
Question 35 Explanation: 
Flags are tested during conditional call and jumps not affected or changed.
Question 36

State whether the following statements are TRUE or FALSE with reason:

Transferring data in blocks from the main memory to the cache memory enables an interleaved main memory unit to operate at its maximum speed.
A
True
B
False
Question 36 Explanation: 
Main memory transfer the data in the form of block to cache and cache transfer the data in the form of words, so it enables the interleaved main memory unit to operate unit at maximum speed.
Question 37

In serial communication employing 8 data bits, a parity bit and 2 stop bits, the minimum band rate required to sustain a transfer rate of 300 characters per second is

A
2400 band
B
19200 band
C
4800 band
D
1200 band
Question 37 Explanation: 
Stop bit is given, it is asynchronous communication and 1 start bit also implied then
(8+2+1+1) * 300
= 3600
Minimum band rate required is 4800 band.
Question 38

Which of the following devices should get higher priority in assigning interrupts?

A
Hard disk
B
Printer
C
Keyboard
D
Floppy disk
Question 38 Explanation: 
Hard disk has the higher priority in assigning interrupts.
Question 39

Which of the following addressing modes permits relocation without any change whatsoever in the code?

A
Indirect addressing
B
Indexed addressing
C
Base register addressing
D
PC relative addressing
Question 39 Explanation: 
In PC relative addressing there is no change in the code.
Question 40

Which of the following is true?

A
Unless enabled, a CPU will not be able to process interrupts.
B
Loop instructions cannot be interrupted till they complete.
C
A processor checks for interrupts before executing a new instruction.
D
Only level triggered interrupts are possible on microprocessors.
Question 40 Explanation: 
Option B & D are false.
Option 'C' also false. A processor checks for the interrupt before fetching an instruction.
Question 41

Formatting for a floppy disk refers to

A
arranging the data on the disk in contiguous fashion
B
writing the directory
C
erasing the system area
D
writing identification information on all tracks and sectors
Question 41 Explanation: 
The formatted disk capacity is always less than the 'raw' unformatted capacity specified by the disk manufacturers, because some portion of each track is used for sector identification and for gaps between sectors and at the end of track.
Question 42

The address space of 8086 CPU is

A
one Megabyte
B
256 Kilobytes
C
1 K Megabytes
D
64 Kilobytes
Question 42 Explanation: 
Note: Out of syllabus.
Question 43

(a) Draw the schematic of an 8085 based system that can be used to measure the width of a pulse. Assume that the pulse is given as a TTL compatible signal by the source which generates it.

(b) Write the 8085 Assembly Language program to measure the width of the pulse. State all your assumption clearly.

A
Theory Explanation.
Question 44

Calculate the total time required to read 35 sectors on a 2-sided floppy disk. Assume that each track has 8 sectors and the track-to-track step time is 8 milliseconds. The first sector to be read is sector 3 on track 10. Assume that the diskette is soft stored and the controller has a 1-sector buffer. The diskette spins at 300 RPM and initially, the head is on track 10.

A
Theory Explanation.
Question 45

For a set-associative Cache Organization, the parameters are as follows:

    tc -- Cache access tine
    tm -- Main memory access time
    l -- number of sets
    b -- block size
    k*b -- set size

Calculate the hit ratio for a loop executed 100 times where the size of the loop is n * b and n= k * m is a non-zero integer and 1 < m ≤ l.
Given the value of the hit ratio for l = 1.

A
Theory Explanation.
Question 46

The main memory of a computer has 2 cm blocks while the cache has 2c blocks. If the cache uses the set associative mapping scheme with 2 blocks per set, then block k of the main memory maps to the set

A
(k mod m) of the cache
B
(k mod c) of the cache
C
(k mod 2c) of the cache
D
(k mod 2 cm) of the cache
Question 46 Explanation: 
No. of sets in cache = No. of blocks in cache/No. of blocks per set
= 2c/c
= c
∴ Cache set no. to which block k of main memory maps to
= (Main memory block no.) mod (Total set in cache)
= k mod c
Question 47

Raid configurations of the disks are used to provide

A
Fault-tolerance
B
High speed
C
High data density
D
None of the above
Question 47 Explanation: 
Raid is a way of storing the same data in different places on multiple hard disks to protect data in the case of drive failure.
So, we can say that RAID is used to provide fault tolerance.
Question 48

Arrange the following configuration for CPU in decreasing order of operating speeds: Hard wired control, vertical microprogramming, horizontal microprogramming.

A
Hard wired control, vertical micro-programming, horizontal micro- programming.
B
Hard wired control, horizontal micro-programming, vertical micro- programming.
C
Horizontal micro-programming, vertical micro-programming, Hard wired control.
D
Vertical micro-programming, horizontal micro-programming, hard wired control.
Question 48 Explanation: 
Hardwired control involves only hardware which is definitely faster than microprogramming approach.
Now between horizontal and vertical microprogramming, the signals in vertical microprogramming are in encoded form which has to be decoded first using decoder. So, horizontal microprogramming is faster than vertical microprogramming.
Question 49

The main differences(s) between a CISC and A RISC processor is/are that a RISC processor typically

A
has fewer instructions
B
has fewer addressing modes
C
has more registers
D
is easier to implement using hard-wired control logic
E
All the above
Question 49 Explanation: 
All are properties of RISC processor.
Question 50

A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor?

A
Pointers
B
Arrays
C
Records
D
Recursive procedures with local variable
E
All the above
Question 50 Explanation: 
A) Cannot be implemented because pointers need indirect addressing mode.
B) Cannot be implemented because arrays need Register indexing.
C) Records also needs pointers which needs indirect addressing modes, so this also cannot be implemented.
D) Recursive procedures needs stack, and so it needs stack pointers which in turn needs indirect addressing. So this also cannot be implemented.
There are 50 questions to complete.

Access subject wise (1000+) question and answers by becoming as a solutions adda PRO SUBSCRIBER with Ad-Free content

Register Now