solutions adda
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Question 1 |
Consider a system with 2 level caches. Access times of Level 1 cache, Level 2 cache and main memory are 1 ns, 10ns, and 500 ns, respectively. The hit rates of Level 1 and Level 2 caches are 0.8 and 0.9, respectively. What is the average access time of the system ignoring the search time within the cache?
A | 13.0 ns |
B | 12.8 ns |
C | 12.6 ns |
D | 12.4 ns |
Question 2 |
If we use internal data forwarding to speed up the performance of a CPU (R1, R2 and R3 are registers and M[100] is a memory reference), then the sequence of operations
R1 → M[100] M[100] → R2 M[100] → R3can be replaced by
A | R1 → R3 R2 → M[100] |
B | M[100] → R2 R1 → R2 R1 → R3 |
C | R1 → M[100] R2 → R3 |
D | R1 → R2 R1 → R3 R1 → M[100] |
Question 3 |
Consider the following statements.
Which of the above statements is/are TRUE?
A | I and IV only |
B | I and II only
|
C | III only |
D | I and III only
|
Question 4 |
A direct mapped cache memory of 1 MB has a block ize of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the first word of a block from the main memory, while each subsequent word takes 5 ns. The word size is 64 bits. The average memory access time in ns (round off to 1 decimal place) is _____.
A | 13.5 |
Question 5 |
Consider the following data path diagram.
Consider an instruction: R0 ← R1 + R2. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts r and w indicate read and write operations, respectively.
1. R2r, TEMP1r, ALUadd, TEMP2w 2. R1r, TEMP1w 3. PCr, MARw, MEMr 4. TEMP2r, ROw 5. MDRr, IRw
Which one of the following is the correct order of execution of the above steps?
A | 3, 5, 1, 2, 4
|
B | 3, 5, 2, 1, 4
|
C | 1, 2, 4, 3, 5 |
D | 2, 1, 4, 5, 3
|
Question 6 |
Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined processor at 2 GHz. In a given program, assume that 30% are memory instructions, 60% are ALU instructions and the rest are branch instructions. 5% of the memory instructions cause stalls of 50 clock cycles each due to cache misses and 50% of the branch instructions cause stalls of 2 cycles each. Assume that there are no stalls associated with the execution of ALU instructions. For this program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to 2 decimal places) is _____.
A | 2.16 |
Question 7 |
A computer system with a word length of 32 bits has a 16 MB byte-addressable main memory and a 64 KB, 4-way set associative cache memory with a block size of 256 bytes. Consider the following four physical addresses represented in hexadecimal notation.
A1 = 0x42C8A4, A2 = 0x546888, A3 = 0x6A289C, A4 = 0x5E4880
Which one of the following is TRUE?
A | A1 and A4 are mapped to different cache sets. |
B | A1 and A3 are mapped to the same cache set. |
C | A3 and A4 are mapped to the same cache set. |
D | A2 and A3 are mapped to the same cache set. |
Question 8 |
A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a 4-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are 8 distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _____.
A | 14 |
Question 9 |
A | DMA based I/O transfer |
B | Interrupt driven I/O transfer |
C | Polling based I/O transfer |
D | Programmed I/O transfer |
Question 10 |
A | Each cache block in WB and WT has a dirty bit. |
B | Every write hit in WB leads to a data transfer from cache to main memory. |
C | Eviction of a block from WT will not lead to data transfer from cache to main memory |
D | A read miss in WB will never lead to eviction of a dirty block from WB. |
Question 11 |
A | 0.85 |
Question 12 |
A | The TLB performs an associative search in parallel on all its valid entries using page number of incoming virtual address. |
B | If the virtual address of a word given by CPU has a TLB hit, but the subsequent search for the word results in a cache miss, then the word will always be present in the main memory. |
C | The memory access time using a given inverted page table is always same for all incoming virtual addresses. |
D | In a system that uses hashed page tables, if two distinct virtual addresses V1 and V2 map to the same value while hashing, then the memory access time of these addresses will not be the same. |
Question 13 |
A | Every access to S is a hit. |
B | Once P is brought to the cache it is never evicted. |
C | At the end of the execution only R and S reside in the cache. |
D | Every access to R evicts Q from the cache. |
Question 14 |
A | 1.43 |
Question 15 |
Relative mode of addressing is most relevant to writing
A | coroutines |
B | position – independent code |
C | shareable code |
D | interrupt handlers |
Question 16 |
Number of machine cycles required for RET instruction in 8085 microprocessor is
A | 1 |
B | 2 |
C | 3 |
D | 5 |
Question 17 |
For the daisy chain scheme of connecting I/O devices, which of the following statements is true?
A | It gives non-uniform priority to various devices. |
B | It gives uniform priority to all devices |
C | It is only useful for connecting slow devices to a processor device. |
D | It requires a separate interrupt pin on the processor for each device. |
Question 18 |
A micro program control unit is required to generate a total of 25 control signals. Assume that during any microinstruction, at most two control signals are active. Minimum number of bits required in the control word to generate the required control signals will be
A | 2 |
B | 2.5 |
C | 10 |
D | 12 |
Question 19 |
An 8052 based system has an output port with address 00H. Consider the following assembly language program.
ORG 0100H MVI A, 00H LXI H, 0105H OUT 00H INR A PCHL HLT
(a) What does the program do with respect to the output port 00H?
(b) Show the wave forms at the three least significant bits of the port 00H.
A | Theory Explanation. |
Question 20 |
Consider the following program in pseudo-pascal syntax. What is printed by the program if parameter a in procedure test 1 is passed as
(i) call-by-reference parameter
(ii) call-by-value-result parameter
program Example (input, output) var b: integer; procedure test2: begin b:=10; end procedure test1 (a:integer): begin a:=5; writeln ('point 1: ', a, b); test2; writeln ('point 2: ', a, b); end begin(*Example*) b:=3; test1(b); writeln('point3:', b); end
A | Theory Explanation. |
Question 21 |
A hard disk is connected to a 50 MHz processor through a DMA controller. Assume that the initial set-up of a DMA transfer takes 1000 clock cycles for the processor, and assume that the handling of the interrupt at DMA completion requires 500 clock cycles for the processor. The hard disk has a transfer rate of 2000 Kbytes/sec and average block transferred is 4 K bytes. What fraction of the processor time is consumed by the disk, if the disk is actively transferring 100% of the time?
A | Theory Explanation. |
Question 22 |
A computer system has a three level memory hierarchy, with access time and hit ratios as shown below:
(a) What should be the minimum sizes of level 1 and 2 memories to achieve an average access time of less than 100 nsec?
(b) What is the average access time achieved using the chosen sizes of level 1 and level 2 memories?
A | Theory Explanation. |
Question 23 |
RST 7.5 interrupt in 8085 microprocessor executes the interrupt service routine from interrupt vector location
A | 0000H |
B | 0075H |
C | 003CH |
D | 0034H |
Question 24 |
Purpose of a start bit in RS 232 serial communication protocol is
A | to synchronize receiver for receiving every byte |
B | to synchronize receiver for receiving a sequence of bytes |
C | a parity bit |
D | to synchronize receiver for receiving the last byte |
Question 25 |
The correct matching for the following pairs is
(A) DMA I/O (1) High speed RAM (B) Cache (2) Disk (C) Interrupt I/O (3) Printer (D) Condition Code Register (4) ALU
A | A – 4 B – 3 C – 1 D – 2 |
B | A – 2 B – 1 C – 3 D – 4
|
C | A – 4 B – 3 C – 2 D – 1 |
D | A – 2 B – 3 C – 4 D – 1 |
Question 26 |
When an interrupt occurs, an operating system
A | ignores the interrupt |
B | always changes state of interrupted process after processing the interrupt |
C | always resumes execution of interrupted process after processing the interrupt
|
D | may change state of interrupted process to 'blocked’ and schedule another process
|
Question 27 |
The expression (a*b)* c op....
where 'op' is one of '+', '*' and '↑' (exponentiation) can be evaluated on a CPU with a single register without storing the value of (a * b) if
A | ‘op’ is ’+’ or ‘*’ |
B | ‘op’ is ’↑’ or ‘*’ |
C | ‘op’ is ’↑’ or ‘+’ |
D | not possible to evaluate without storing |
Question 28 |
Contents of A register after the execution of the following 8085 microprocessor program is
MVI A, 55 H MVI C, 25 H ADD C DAA
A | 7AH |
B | 80H |
C | 50H |
D | 22H |
Question 29 |
A micro instruction into be designed to specify
The minimum number of bits in the micro-instruction is
A | 9 |
B | 5 |
C | 8 |
D | None of the above |
Question 30 |
In serial communication employing 8 data bits, a parity bit and 2 stop bits, the minimum band rate required to sustain a transfer rate of 300 characters per second is
A | 2400 band |
B | 19200 band |
C | 4800 band |
D | 1200 band |
Question 31 |
Which of the following devices should get higher priority in assigning interrupts?
A | Hard disk |
B | Printer |
C | Keyboard |
D | Floppy disk |
Question 32 |
Which of the following addressing modes permits relocation without any change whatsoever in the code?
A | Indirect addressing |
B | Indexed addressing |
C | Base register addressing |
D | PC relative addressing |
Question 33 |
Which of the following is true?
A | Unless enabled, a CPU will not be able to process interrupts. |
B | Loop instructions cannot be interrupted till they complete. |
C | A processor checks for interrupts before executing a new instruction. |
D | Only level triggered interrupts are possible on microprocessors. |
Question 34 |
Formatting for a floppy disk refers to
A | arranging the data on the disk in contiguous fashion |
B | writing the directory |
C | erasing the system area |
D | writing identification information on all tracks and sectors |
Question 35 |
The address space of 8086 CPU is
A | one Megabyte |
B | 256 Kilobytes |
C | 1 K Megabytes |
D | 64 Kilobytes |
Question 36 |
(a) Draw the schematic of an 8085 based system that can be used to measure the width of a pulse. Assume that the pulse is given as a TTL compatible signal by the source which generates it.
(b) Write the 8085 Assembly Language program to measure the width of the pulse. State all your assumption clearly.
A | Theory Explanation. |
Question 37 |
Calculate the total time required to read 35 sectors on a 2-sided floppy disk. Assume that each track has 8 sectors and the track-to-track step time is 8 milliseconds. The first sector to be read is sector 3 on track 10. Assume that the diskette is soft stored and the controller has a 1-sector buffer. The diskette spins at 300 RPM and initially, the head is on track 10.
A | Theory Explanation. |
Question 38 |
For a set-associative Cache Organization, the parameters are as follows:
Calculate the hit ratio for a loop executed 100 times where the size of the loop is n * b and n= k * m is a non-zero integer and 1 < m ≤ l.
Given the value of the hit ratio for l = 1.
A | Theory Explanation. |
Question 39 |
The main memory of a computer has 2 cm blocks while the cache has 2c blocks. If the cache uses the set associative mapping scheme with 2 blocks per set, then block k of the main memory maps to the set
A | (k mod m) of the cache |
B | (k mod c) of the cache |
C | (k mod 2c) of the cache |
D | (k mod 2 cm) of the cache |
Question 40 |
Raid configurations of the disks are used to provide
A | Fault-tolerance |
B | High speed |
C | High data density |
D | None of the above |
Question 41 |
Arrange the following configuration for CPU in decreasing order of operating speeds: Hard wired control, vertical microprogramming, horizontal microprogramming.
A | Hard wired control, vertical micro-programming, horizontal micro- programming. |
B | Hard wired control, horizontal micro-programming, vertical micro- programming. |
C | Horizontal micro-programming, vertical micro-programming, Hard wired control. |
D | Vertical micro-programming, horizontal micro-programming, hard wired control. |
Question 42 |
The main differences(s) between a CISC and A RISC processor is/are that a RISC processor typically
A | has fewer instructions |
B | has fewer addressing modes |
C | has more registers |
D | is easier to implement using hard-wired control logic
|
E | All the above |
Question 43 |
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor?
A | Pointers |
B | Arrays |
C | Records |
D | Recursive procedures with local variable |
E | All the above |
Question 44 |
An instruction pipeline consists of 4 stages: Fetch(F), Decode operand field (D), Execute (E), and Result-Write (W). The five instructions in a certain instruction sequence need these stages for the different number of clock cycles as shown by the table below.
Find the number of clock cycles needed to perform the 5 instructions.
A | Theory Explanation. |
Question 45 |
Consider the following program fragment in the assembly language of a certain hypothetical processor. The processor has three general purpose registers R1, R2 and R3. The meanings of the instructions are shown by comments (starting with 😉 after the instructions.
X: CMP R1, 0 ; Compare R1 and 0, set flags appropriately in status register JZ Z ; Jump if zero to target Z MOV R2, R1 ; Copy contents of R1 to R2 SHR R1 ; Shift right R1 by 1 bit SHL R1 ; Shift left R1 by 1 bit CMP R2, R1 ; Compare R2 and R1 and set flag in status register JZ Y ; Jump if zero to target Y INC R3 ; Increment R3 by 1; Y: SHR R1 ; Shift right R1 by 1 bit JMP X ; Jump to target X Z:...
(a) Initially R1, R2 and R3 contain the value 5, 0 and 0 respectively. What are the final values of R1 and R3 when control reaches Z?
(b) In general, if R1, R2 and R3 initially contain the values n, 0 and 0 respectively. What is the final value of R3 when control reaches Z?
A | Theory Explanation. |
Question 46 |
Design a 2K x 8 (2048 locations, each 8 bit wide) memory system mapped at addresses (1000)16 to (17FF)16 for the 8085 processor using four 1K x 4 memory chips. Each of these chips has the following signal pins:
A | Theory Explanation. |
Question 47 |
To put the 8085 microprocessor in the wait state
A | lower the HOLD input |
B | lower the READY input |
C | raise the HOLD input |
D | raise the READY input |
Question 48 |
Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non-pipelined but identical CPU, we can say that
A | T1 ≤ T2 |
B | T1 ≥ T2 |
C | T1 < T2 |
D | T1 is T2 plus the time taken for one instruction fetch cycle |
Question 49 |
The 8085 microprocessor responds to the present of an interrupt
A | as soon as the TRAP pin becomes ‘high’ |
B | by checking the TRAP pin for ‘high’ status at the end of each instruction each |
C | by checking the TRAP pin for ‘high’ status at the end of the execution of each instruction |
D | by checking the TRAP pin for ‘high’ status at regular intervals |
Question 50 |
The most appropriate matching for the following pairs
X: Indirect addressing 1 : Loops Y: Immediate addressing 2 : Pointers Z: Auto decrement addressing 3: Constants
is
A | X – 3 Y – 2 Z - 1 |
B | X – 1 Y – 3 Z - 2 |
C | X – 2 Y – 3 Z - 1 |
D | X – 3 Y – 1 Z - 2 |