Computer-Organization
Question 1 |
Micro program is
The name of a source program in microcomputers | |
Set of micro instructions that define the individual operations in response to a machine-language instruction | |
A primitive form of macros used in assembly language programming | |
A very small segment of machine code |
Question 1 Explanation:
→ The Microprogram is computing a sequence of microinstructions that controls the operation of an arithmetic and logic unit so that machine code instructions are executed.
→ The Microprogram is set of microinstructions that define the individual operations in response to a machine-language instruction
→ The Microprogram is set of microinstructions that define the individual operations in response to a machine-language instruction
Question 2 |
A particular disk unit uses a bit string to record the occupancy or vacancy of its tracks, with 0 denoting vacant and 1 for occupied. A 32-bit segment of this string has hexadecimal value D4FE2003. The percentage of occupied tracks for the corresponding part of the disk, to the nearest percentage is
12 | |
25 | |
38 | |
44 |
Question 3 |
Of the following, which best characterizes computers that use memory-mapped I/O?
The computer provides special instructions for manipulating I/O ports | |
I/O ports are placed at addresses on the bus and are accessed just like other memory locations | |
To perform I/O operations, it is sufficient to place the data in an address register and call channel to perform the operation | |
I/O can be performed only when memory management hardware is turned on |
Question 3 Explanation:
→ Memory-mapped I/O uses the same address space to address both memory and I/O devices.
→ The memory and registers of the I/O devices are mapped to (associated with) address values.
→ So when an address is accessed by the CPU, it may refer to a portion of physical RAM, or it can instead refer to the memory of the I/O device. Thus, the CPU instructions used to access the memory can also be used for accessing devices.
→ Each I/O device monitors the CPU's address bus and responds to any CPU access of an address assigned to that device, connecting the data bus to the desired device's hardware register.
→ To accommodate the I/O devices, areas of the addresses used by the CPU must be reserved for I/O and must not be available for normal physical memory.
→ The reservation may be permanent, or temporary (as achieved via bank switching).
→ The memory and registers of the I/O devices are mapped to (associated with) address values.
→ So when an address is accessed by the CPU, it may refer to a portion of physical RAM, or it can instead refer to the memory of the I/O device. Thus, the CPU instructions used to access the memory can also be used for accessing devices.
→ Each I/O device monitors the CPU's address bus and responds to any CPU access of an address assigned to that device, connecting the data bus to the desired device's hardware register.
→ To accommodate the I/O devices, areas of the addresses used by the CPU must be reserved for I/O and must not be available for normal physical memory.
→ The reservation may be permanent, or temporary (as achieved via bank switching).
Question 4 |
A byte addressable computer has a memory capacity of 2m KB( kbytes ) and can perform 2n operations. An instruction involving 3 operands and one operator needs maximum of
3m bits | |
3m + n bits | |
m + n bits | |
None of the above |
Question 4 Explanation:
Step-1: Memory capacity is 2m KB = 230m Bytes
Step-2: Total number of operations 2n
Step-3: Every instruction involving 3 operands and 1 operator
Step-4: Number of bits needed by instruction is= 3*(m+10)+n
=3m+n+30 bits
Step-2: Total number of operations 2n
Step-3: Every instruction involving 3 operands and 1 operator
Step-4: Number of bits needed by instruction is= 3*(m+10)+n
=3m+n+30 bits
Question 5 |
For a multiprocessor architecture, In which protocol a write transaction is forwarded to only those processors that are known to possess a copy of newly altered cache line ?
Snoopy bus protocol | |
Cache coherence protocol | |
Directory-based protocol | |
None of the above |
Question 5 Explanation:
→ Directory based coherence is a mechanism to handle Cache coherence problem in Distributed shared memory (DSM).
→ Non-Uniform Memory Access (NUMA). Another popular way is to use a special type of computer bus between all the nodes as a "shared bus" (System bus).
→ Directory-based coherence uses a special directory to serve instead of the shared bus in the bus based coherence protocols.
→ In directory-based cache coherence, this is done by using this directory to keep track of the status of all cache blocks, the status of each block includes in which cache coherence "state" that block is, and which nodes are sharing that block at that time, which can be used to eliminate the need to broadcast all the signals to all nodes, and only send it to the nodes that are interested in this single block.
→ Non-Uniform Memory Access (NUMA). Another popular way is to use a special type of computer bus between all the nodes as a "shared bus" (System bus).
→ Directory-based coherence uses a special directory to serve instead of the shared bus in the bus based coherence protocols.
→ In directory-based cache coherence, this is done by using this directory to keep track of the status of all cache blocks, the status of each block includes in which cache coherence "state" that block is, and which nodes are sharing that block at that time, which can be used to eliminate the need to broadcast all the signals to all nodes, and only send it to the nodes that are interested in this single block.
Question 6 |
A read bit can be read
and written by CPU | |
and written by peripheral | |
by peripheral and written by CPU | |
by CPU and written by the peripheral |
Question 6 Explanation:
The read and write functionality depends on the type of microcontroller peripheral. Generally, the status bits have a read only status and can be modified by peripherals only.
So, read bit can be read by CPU and written by the peripheral.
Question 7 |
The principal of the locality of reference justifies the use of
virtual memory | |
interrupts | |
main memory
| |
cache memory |
Question 7 Explanation:
Spatial Locality of reference – this says that there is chance that element will be present in the close proximity to the reference point and next time if again searched then more close proximity to the point of reference.
Temporal Locality of reference – In this Least recently used algorithm will be used. Whenever there is page fault occurs within word will not only load word in main memory but complete page fault will be loaded because spatial locality of reference rule says that if you are referring any word next word will be referred in
its register that’s why we load complete page table so complete block will be loaded.
Principle of locality of reference justifies the use of cache.
Temporal Locality of reference – In this Least recently used algorithm will be used. Whenever there is page fault occurs within word will not only load word in main memory but complete page fault will be loaded because spatial locality of reference rule says that if you are referring any word next word will be referred in
its register that’s why we load complete page table so complete block will be loaded.
Principle of locality of reference justifies the use of cache.
Question 8 |
Assume that each character code consists of 8 bits. The number of characters that can be transmitted per second through an synchronous serial line at 2400 baud rate, and with two stop bits is
109 | |
216 | |
300 | |
219 |
Question 8 Explanation:
Synchronous communication requires that the clocks in the transmitting and receiving devices are synchronized – running at the same rate – so the receiver can sample the signal at the same time intervals used by the transmitter. No start or stop bits are required. For this reason “synchronous communication permits more information to be passed over a circuit per unit time.
2400 baud means that the serial port is capable of transferring a maximum of 2400 bits per second.
Number of 8-bit characters that can be transmitted per second = 2400/8 = 300
2400 baud means that the serial port is capable of transferring a maximum of 2400 bits per second.
Number of 8-bit characters that can be transmitted per second = 2400/8 = 300
Question 9 |
In the Big-Endian system, the computer stores
MSB of data in the lowest memory address of data unit | |
LSB of data in the lowest memory address of data unit | |
MSB of data in the highest memory address of data unit | |
LSB of data in the highest memory address of data uni |
Question 9 Explanation:
Big-endian is an order in which the “big end” i.e. the most significant value in the sequence is stored first at the lowest storage address.
Question 10 |
The most appropriate matching for the following pairs :
X − 3, Y − 2, Z −1 | |
X − 2, Y − 3, Z −1 | |
X − 3, Y −1, Z − 2 | |
X − 2, Y −1, Z − 3 |
Question 10 Explanation:
Indirect addressing:
Indirect addressing means that the address of the data is held in an intermediate location so that the address is first 'looked up' and then used to locate the data itself.
Immediate addressing:
Immediate Addressing. An immediate operand has a constant value or an expression. When an instruction with two operands uses immediate addressing, the first operand may be a register or memory location, and the second operand is an immediate constant. Auto increment or decrements: can be one by using loops.
Indirect addressing means that the address of the data is held in an intermediate location so that the address is first 'looked up' and then used to locate the data itself.
Immediate addressing:
Immediate Addressing. An immediate operand has a constant value or an expression. When an instruction with two operands uses immediate addressing, the first operand may be a register or memory location, and the second operand is an immediate constant. Auto increment or decrements: can be one by using loops.
Question 11 |
Which interrupt in 8085 Microprocessor is unmaskable?
RST 5.5 | |
RST 7.5 | |
TRAP | |
Both (a) and (b) |
Question 11 Explanation:
Interrupts are the signals generated by the external devices to request the microprocessor to perform a ask. There are 5 interrupt signals. Given low priority to high is
1. INTR
2. RST 5.5
3. RST 6.5
4. RST 7.5
5. TRAP
Maskable Interrupts: They can be enabled or disabled by software INTR,RST 5.5,RST 6.5 and RST 7.5
Un maskable Interrupts: TRAP
1. INTR
2. RST 5.5
3. RST 6.5
4. RST 7.5
5. TRAP
Maskable Interrupts: They can be enabled or disabled by software INTR,RST 5.5,RST 6.5 and RST 7.5
Un maskable Interrupts: TRAP
Question 12 |
A cache memory needs an access time of 30 ns and main memory 150 ns, what is the average access time of CPU (assume hit ratio = 80%)?
60 | |
30 | |
150 | |
70 |
Question 12 Explanation:
Step-1: Hit ratio 80%=0.8 and Miss ratio=20%=0.2
Access time=30ns
Main memory=150ns
Step-2: CPU access time = (Hit ratio*access time) + (Miss ratio*access time+Main memory)
= (0.8*30) + (0.2*(30+150))
= 60 ns
Access time=30ns
Main memory=150ns
Step-2: CPU access time = (Hit ratio*access time) + (Miss ratio*access time+Main memory)
= (0.8*30) + (0.2*(30+150))
= 60 ns
Question 13 |
Which one of these is characteristic of RAID 5?
Dedicated Parity | |
Double Parity | |
Hamming code Parity | |
Distributed Parity |
Question 13 Explanation:
RAID 0: Disk Striping or non-redundant striping
RAID 1: Disk Mirroring
RAID 2: Memory style error correcting codes
RAID 3: Bit interleaved parity
RAID 4: Block interleaved parity
RAID 5: Block interleaved distributed parity
RAID 6: P+Q redundancy
RAID 1: Disk Mirroring
RAID 2: Memory style error correcting codes
RAID 3: Bit interleaved parity
RAID 4: Block interleaved parity
RAID 5: Block interleaved distributed parity
RAID 6: P+Q redundancy
Question 14 |
Consider a disk system with 100 cylinders. The request to access the cylinders occur in the following sequences
4, 34, 10, 7, 19, 73, 2, 15, 6, 20
Assuming the head is currently at cylinder 50, what is the time taken to satisfy all requests if it takes 1 ms to move from one cylinder to adjacent one and shortest seek time first algorithm is used.
95 msec | |
119 msec | |
233 msec | |
276 msec |
Question 14 Explanation:
The given sequence is
4, 34, 10,7, 19, 73, 2, 15, 6, 20
Arrange the sequence in order
2, 4, 6, 10, 15, 19, 20, 34, 73
⇒ 1 ms to move from one cylinder to adjacent one
⇒ (16*1)+(14*1)+(1*1)+(4*1)+(5*1)+(3*1)+(1*1)+(2*1)+(2*1)+(71*1)
⇒ 16+14+1+4+5+3+1+2+2+71
⇒ 119 ms
4, 34, 10,7, 19, 73, 2, 15, 6, 20
Arrange the sequence in order
2, 4, 6, 10, 15, 19, 20, 34, 73
⇒ 1 ms to move from one cylinder to adjacent one⇒ (16*1)+(14*1)+(1*1)+(4*1)+(5*1)+(3*1)+(1*1)+(2*1)+(2*1)+(71*1)
⇒ 16+14+1+4+5+3+1+2+2+71
⇒ 119 ms
Question 15 |
The address space of 8086 CPU is
one Megabyte | |
256 Kilobytes | |
1 K Megabytes | |
64 Kilobytes |
Question 15 Explanation:
In 8086 architecture there are 16 bit data lines and 20 bit address lines.
16 bit data lines means that the word size must be 2 bytes and these 2 bytes can be read in a single memory cycle.
20 bit address lines corresponds that the memory size is 220 Bytes = 1 Megabyte
16 bit data lines means that the word size must be 2 bytes and these 2 bytes can be read in a single memory cycle.
20 bit address lines corresponds that the memory size is 220 Bytes = 1 Megabyte
Question 16 |
The performance of a pipelined processor suffers if
the pipeline stages have different delays | |
consecutive instructions are dependent on each other | |
the pipeline stages share hardware resources | |
All of the above |
Question 16 Explanation:
1. Pipelining is one way of improving the overall processing performance of a processor.
2. This architectural approach allows the simultaneous execution of several instructions.
3. Pipelining is transparent to the programmer; it exploits parallelism at the instruction level by overlapping the execution process of instructions.
4. It is analogous to an assembly line where workers perform a specific task and pass the partially completed product to the next worker.
2. This architectural approach allows the simultaneous execution of several instructions.
3. Pipelining is transparent to the programmer; it exploits parallelism at the instruction level by overlapping the execution process of instructions.
4. It is analogous to an assembly line where workers perform a specific task and pass the partially completed product to the next worker.
Question 17 |
More than one word are put in one cache block to
exploit the temporal locality of reference in a program | |
exploit the spatial locality of reference in a program | |
reduce the miss penalty | |
none of these |
Question 17 Explanation:
Temporal locality refers to the reuse of specific data and/or resources within relatively small time durations. Spatial locality refers to the use of data elements within relatively close storage locations.
To exploit the spatial locality, more than one word are put into cache block.
To exploit the spatial locality, more than one word are put into cache block.
Question 18 |
An interrupt in which the external device supplies its address as well as the interrupt requests is known as
vectored interrupt | |
maskable interrupt | |
non-maskable interrupt | |
designated interrupt |
Question 18 Explanation:
→ A vectored interrupt is a processing technique in which the interrupting device directs the processor to the appropriate interrupt service routine.
→ A non-maskable interrupt (NMI) is a hardware interrupt that standard interrupt-masking techniques in the system cannot ignore. It typically occurs to signal attention for non-recoverable hardware errors.
→ Maskable Interrupts - Those interrupts whose request can be denied by microprocessor. eg- RST 1, RST2, RST 5, RST 6.5 etc.
Question 19 |
Consider the following Assembly language program
MVIA 30 H
ACI 30 H
XRA A
POP H
After the execution of the above program, the contents of the accumulator will
MVIA 30 H
ACI 30 H
XRA A
POP H
After the execution of the above program, the contents of the accumulator will
30 H | |
60 H | |
00 H | |
contents of stack |
Question 19 Explanation:
MVI (move immediate) instruction is to be used when directly adding a hexadecimal value MVI A, 30H means the data 30H will be moved to A register.
ACI: – Add immediate to accumulator with carry.
XRA: – Exclusive OR register or memory with the accumulator
So after first instruction execution, Accumulator value will be A = 30H = 0011 0000
After second Instruction A = 30 + 30 = 0110 0000
After third Instruction A = A⊕A = 0110 0000 ⊕ 0110 0000 = 0000 0000 = 00H
Question 20 |
Which of the following architecture is/are not suitable for realising SIMD?
Vector processor | |
Array processor | |
Von Neumann | |
All of the above |
Question 20 Explanation:
→ Single instruction, multiple data (SIMD) is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data points simultaneously. Such machines exploit data level parallelism, but not concurrency: there are simultaneous (parallel) computations, but only a single process (instruction) at a given moment
→ The von Neumann architecture is also known as the von Neumann model or Princeton architecture consists of the following components:
A processing unit that contains an arithmetic logic unit and processor registers
A control unit that contains an instruction register and program counter
Memory that stores data and instructions
External mass storage
Input and output mechanisms
→ The von Neumann architecture is also known as the von Neumann model or Princeton architecture consists of the following components:
A processing unit that contains an arithmetic logic unit and processor registers
A control unit that contains an instruction register and program counter
Memory that stores data and instructions
External mass storage
Input and output mechanisms
Question 21 |
The device which is used to connect a peripheral to bus is known as
control register | |
interface | |
communication protocol | |
none of these |
Question 21 Explanation:
1. A control register is a processor register which changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control.
2. Interface is the device which is used to connect a peripheral to bus.
3. In telecommunication, a communication protocol is a system of rules that allow two or more entities of a communications system to transmit information via any kind of variation of a physical quantity. The protocol defines the rules, syntax, semantics and synchronization of communication and possible error recovery methods. Protocols may be implemented by hardware, software, or a combination of both.
2. Interface is the device which is used to connect a peripheral to bus.
3. In telecommunication, a communication protocol is a system of rules that allow two or more entities of a communications system to transmit information via any kind of variation of a physical quantity. The protocol defines the rules, syntax, semantics and synchronization of communication and possible error recovery methods. Protocols may be implemented by hardware, software, or a combination of both.
Question 22 |
The TRAP is one of the interrupts available in INTEL 8085. Which one of the following statements is true of TRAP ?
it is level triggered | |
it is negative edge triggered | |
it is +ve edge triggered | |
it is both +ve and -ve edges triggered |
Question 22 Explanation:
The TRAP interrupt is edge and level sensitive. Hence, to initiate TRAP, the interrupt signal has to make a low to high transition and then it has to remain high until the interrupt is recognized.
Question 23 |
The Memory Address Register
is a hardware memory device which denotes the location of the current instruction being executed. | |
is a group of electrical circuit, that performs the intent of instructions fetched from memory | |
contains the address of the memory location that is to be read from or stored into | |
contains a copy of the designated memory location specified by the MAR after a “read” or the new contents of the memory prior to a “write” |
Question 23 Explanation:
In a computer, the Memory Address Register (MAR) is the CPU register that either stores the memory address from which data will be fetched from the CPU, or the address to which data will be sent and stored.
Question 24 |
Which of the following is/are true of the auto-increment addressing mode?
I. It is useful in creating self-relocating code
II. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation
III. The amount of increment depends on the size of the data item accessed
I. It is useful in creating self-relocating code
II. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation
III. The amount of increment depends on the size of the data item accessed
I only | |
II only | |
III only | |
) II only |
Question 24 Explanation:
After determining the effective address, the value in the base register is incremented by the size of the data item that is to be accessed.
For example, (A7)+ would access the content of the address register A7, then increase the address pointer of A7 by 1 (usually 1 word). Within a loop, this addressing mode can be used to step through all the elements of an array or vector.
For example, (A7)+ would access the content of the address register A7, then increase the address pointer of A7 by 1 (usually 1 word). Within a loop, this addressing mode can be used to step through all the elements of an array or vector.
Question 25 |
In which addressing mode, the effective address of the operand is generated by adding a constant value to the content of a register?
Absolute mode
| |
Indirect mode
| |
Immediate mode
| |
Index mode |
Question 25 Explanation:
1. An absolute address is represented by the contents of a register. This addressing mode is absolute in the sense that it is not specified relative to the current instruction address.
2. Indirect addressing is a scheme in which the address specifies which memory word or register contains not the operand but the address of the operand.
Immediate Operand:
The simplest way for an instruction to specify an operand is for the address part of the instruction actually to contain the operand itself rather than an address or other information describing where the operand is. Such an operand is called an immediate operand because it is automatically fetched from memory at the same time the instruction itself is fetched. It is immediately available for use.
Index mode:
The address of the operand is obtained by adding to the contents of the general register (called index register) a constant value. The number of the index register and the constant value are included in the instruction code
2. Indirect addressing is a scheme in which the address specifies which memory word or register contains not the operand but the address of the operand.
Immediate Operand:
The simplest way for an instruction to specify an operand is for the address part of the instruction actually to contain the operand itself rather than an address or other information describing where the operand is. Such an operand is called an immediate operand because it is automatically fetched from memory at the same time the instruction itself is fetched. It is immediately available for use.
Index mode:
The address of the operand is obtained by adding to the contents of the general register (called index register) a constant value. The number of the index register and the constant value are included in the instruction code
Question 26 |
A certain microprocessor requires 4.5 microseconds to respond to an interrupt. Assuming that the three interrupts I1, I2 and I3 require the following execution time after the interrupt is recognized:
i. I1 requires 25 microseconds
ii. I2 requires 35 microseconds
iii. I3 requires 20 microseconds
I1 has the highest priority and I3 has the lowest. What is the possible range of time for I3 to be executed assuming that it may or may not occur simultaneously with other interrupts?
i. I1 requires 25 microseconds
ii. I2 requires 35 microseconds
iii. I3 requires 20 microseconds
I1 has the highest priority and I3 has the lowest. What is the possible range of time for I3 to be executed assuming that it may or may not occur simultaneously with other interrupts?
24.5 microseconds to 39.5 microseconds | |
24.5 microseconds to 93.5 microseconds | |
4.5 microseconds to 24.5 microseconds | |
29.5 microseconds 93.5 microseconds |
Question 26 Explanation:
Consider case-1: I3 is executed without other interrupts:
Time interval = Interrupt processing time(I3) + Execution time(I3) = 4.5 + 20 microseconds = 24.5 microseconds
Consider case-2: I3 is executed simultaneously with other interrupts:
Time interval =( Interrupt processing time + Execution time) for I1, I2, I3 = 4.5 + 25 + 4.5 + 35 + 4.5 + 20 = 93.5 microseconds
Time interval = Interrupt processing time(I3) + Execution time(I3) = 4.5 + 20 microseconds = 24.5 microseconds
Consider case-2: I3 is executed simultaneously with other interrupts:
Time interval =( Interrupt processing time + Execution time) for I1, I2, I3 = 4.5 + 25 + 4.5 + 35 + 4.5 + 20 = 93.5 microseconds
Question 27 |
The process of organizing the memory into two banks to allow 8 and 16-bit data operation is called
Bank switching | |
Indexed mapping | |
Two-way memory interleaving | |
Memory segmentation |
Question 27 Explanation:
Interleaved memory is a design made to compensate for the relatively slow speed of dynamic random-access memory (DRAM) or core memory, by spreading memory addresses evenly across memory banks.
Contiguous memory reads and writes are using each memory bank in turn, resulting in higher memory throughputs due to reduced waiting for memory banks to become ready for desired operations.
Two-Way Interleaved : Two memory blocks are accessed at same time for writing and reading operations
Contiguous memory reads and writes are using each memory bank in turn, resulting in higher memory throughputs due to reduced waiting for memory banks to become ready for desired operations.
Two-Way Interleaved : Two memory blocks are accessed at same time for writing and reading operations
Question 28 |
The micro instructions stored in the control memory of a processor have a width of 26 bits. Each micro instruction is divided into three fields. a micro operation field of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX. How many bits are there in the X and Y fields, and what is the size of the control memory in number of words
10, 3, 1024 | |
8, 5, 256 | |
5, 8, 2048
| |
10, 3, 512 |
Question 28 Explanation:
The number of bits in Control memory =26.
From the given data each instruction divided into op field (13)+X(next address field)+Y(MUX)
8(23) status bits in the inputs of the MUX then three bits in the MUX select field.
No. of bits in control memory next address field=26-13-3 =10
size of the control memory in number of words is 210=1024 words
From the given data each instruction divided into op field (13)+X(next address field)+Y(MUX)
8(23) status bits in the inputs of the MUX then three bits in the MUX select field.
No. of bits in control memory next address field=26-13-3 =10
size of the control memory in number of words is 210=1024 words
Question 29 |
A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)?
400 | |
500 | |
600 | |
700 |
Question 29 Explanation:
C.P.U will use 24- bit instructions and instructions size(bytes) is 24/8 = 3 bytes
Program execution will start from address at 300 and from there on words every operation will takes 3- bytes and so on , So the address should be multiple of “3”. From the given options only 600 address value is valid.
Program execution will start from address at 300 and from there on words every operation will takes 3- bytes and so on , So the address should be multiple of “3”. From the given options only 600 address value is valid.
Question 30 |
Consider a disk pack with 16 surfaces, 128 tracks per surface and 256 sectors per track. 512 bytes of data are stored in a bit serial manner in a sector. The capacity of the disk pack and the number of bits required to specify a particular sector in the disk are respectively
256 Mbyte, 19 bits | |
256 Mbyte, 28 bit | |
512 Mbyte, 20 bits | |
64 Gbyte, 28 bits |
Question 30 Explanation:
Number of surfaces =16
Tracks per surface=128
Sectors per track=256
Data which will store per sector=512 bytes
Capacity of the disk = 16 surfaces X 128 tracks X 256 sectors X 512 bytes = 256 Mbytes.
The number of bits required to access a sector =Total number of sectors.
= 16 surfaces X 128 tracks X 256 sectors
=24x27x28=219
Tracks per surface=128
Sectors per track=256
Data which will store per sector=512 bytes
Capacity of the disk = 16 surfaces X 128 tracks X 256 sectors X 512 bytes = 256 Mbytes.
The number of bits required to access a sector =Total number of sectors.
= 16 surfaces X 128 tracks X 256 sectors
=24x27x28=219
Question 31 |
Which of the following statements about relative addressing mode is FALSE?
It enables reduced instruction size | |
It allows indexing of array element with same instruction | |
It enables easy relocation of data | |
It enables faster address calculation than absolute addressing |
Question 31 Explanation:
Relative address means an address specified by indicating its distance from another address, called the base address.
In absolute addressing, you specify the actual address (called the absolute address) of a memory location.
In absolute addressing, you specify the actual address (called the absolute address) of a memory location.
Question 32 |
On receiving an interrupt from an I/O device,the CPU
Halts for a predetermined time | |
Branches off to the interrupt service routine after completion of the current instruction
| |
Branches off to the interrupt service routine immediately
| |
Hands over control of address bus and data bus to the interrupting device |
Question 32 Explanation:
1. The CPU then performs a state save, and transfers control to the interrupt handler routine at a fixed address in memory. ( The CPU catches the interrupt and dispatches the interrupt handler)
2. The interrupt handler determines the cause of the interrupt, performs the necessary processing, performs a state restore, and executes a return from interrupt instruction to return control to the CPU. ( The interrupt handler clears the interrupt by servicing the device. )
2. The interrupt handler determines the cause of the interrupt, performs the necessary processing, performs a state restore, and executes a return from interrupt instruction to return control to the CPU. ( The interrupt handler clears the interrupt by servicing the device. )
Question 33 |
Compared to CISC processors,RISC processors contain:
More registers and smaller instruction set | |
larger instruction set | |
less registers and smaller instruction set | |
more transistor elements |
Question 33 Explanation:
A reduced instruction set computer, or RISC , is one whose instruction set architecture (ISA) allows it to have fewer cycles per instruction (CPI) than a complex instruction set computer (CISC).
In RISC architecture, the instruction set of the computer is simplified to reduce the execution time. It uses small and highly optimized set of instructions which are generally register to register operations
In RISC architecture, the instruction set of the computer is simplified to reduce the execution time. It uses small and highly optimized set of instructions which are generally register to register operations
Question 34 |
Which of the following statements about synchronous and asynchronous I/O is NOT true?
An ISR is invoked on completion of I/O in synchronous I/O but not in asynchronous I/O | |
In both synchronous and asynchronous I/O, an ISR (Interrupt Service Routine) is invoked after completion of the I/O | |
A process making a synchronous I/O call waits until I/O is complete, but a process making an asynchronous I/O call does not wait for completion of the I/O | |
In the case of synchronous I/O, the process waiting for the completion of I/O is woken up by the ISR that is invoked after the completion of I/O |
Question 34 Explanation:
→ Synchronous I/O mean that some flow of execution (such as a process or thread) is waiting for the operation to complete.
Asynchronous I/O means that nothing is waiting for the operation to complete and the completion of the operation itself causes something to happen.
→ Synchronous I/O -- some execution vehicle (like a process or thread) that initiates the I/O also waits for the I/O to complete (and perhaps completes it). When the I/O completes, that same execution vehicle goes on to do something else, perhaps using the results of the I/O.
→ Asynchronous I/O -- no execution vehicle waits for the I/O to complete. When the I/O completes, whatever execution vehicle happens to complete the I/O may arrange for later things to happen.
Option B is not true, because both synchronous and asynchronous I/O, an ISR (Interrupt Service Routine) is not invoked after completion of the I/O.
Asynchronous I/O means that nothing is waiting for the operation to complete and the completion of the operation itself causes something to happen.
→ Synchronous I/O -- some execution vehicle (like a process or thread) that initiates the I/O also waits for the I/O to complete (and perhaps completes it). When the I/O completes, that same execution vehicle goes on to do something else, perhaps using the results of the I/O.
→ Asynchronous I/O -- no execution vehicle waits for the I/O to complete. When the I/O completes, whatever execution vehicle happens to complete the I/O may arrange for later things to happen.
Option B is not true, because both synchronous and asynchronous I/O, an ISR (Interrupt Service Routine) is not invoked after completion of the I/O.
Question 35 |
Consider a pipelined processor with the following four stages:
IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute
WB: Write Back
The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
ADD R2, R1, R0 R2 ← R1 + R0
MUL R4, R3, R2 R4 ← R3 * R2
SUB R6, R5, R4 R6 ← R5 - R4
IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute
WB: Write Back
The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
ADD R2, R1, R0 R2 ← R1 + R0
MUL R4, R3, R2 R4 ← R3 * R2
SUB R6, R5, R4 R6 ← R5 - R4
7 | |
8 | |
10 | |
14 |
Question 35 Explanation:
Since operand forwarding is there, by default we consider the operand forwarding from EX stage to EX stage.
Question 36 |
The use of multiple register windows with overlap causes a reduction in the number of memory accesses for
- Function locals and parameters
- Register saves and restores
I only | |
II only | |
III only | |
I, II and III |
Question 36 Explanation:
→ I is true because when we make a function call there are some input registers and some output registers. If function F() is calling function G(), we can make the caller function F()'s output registers the same as the called procedure G()'s input registers this is done using overlapping register windows.This will reduce the memory accesses so that F()'s output need not be put into memory for G() to access again from memory.
→ II is false as register saves and restores would still be required for each and every variable.
→ III is also false as instruction fetch is not affected by memory access using multiple register windows.
→ II is false as register saves and restores would still be required for each and every variable.
→ III is also false as instruction fetch is not affected by memory access using multiple register windows.
Question 37 |
Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is
3.2 | |
3.0 | |
2.2 | |
2.0 |
Question 37 Explanation:
→ Given that the processor clock rate = 2.5 GHz, the processor takes 2.5 G cycles in one second.
→ Time taken to complete one cycle = (1 / 2.5 G) seconds
→ Since it is given that average number of cycles per instruction = 4, the time taken for completing one instruction=(4/2.5 G) = 1.6 ns
→ In the pipelined case we know in the ideal case CPI = 1, and the clock speed = 2 GHz.
→ Time taken for one instruction in the pipelined case = (1 / 2 G) = 0.5 ns
→ Speedup = 1.6/0.5 = 3.2
→ Time taken to complete one cycle = (1 / 2.5 G) seconds
→ Since it is given that average number of cycles per instruction = 4, the time taken for completing one instruction=(4/2.5 G) = 1.6 ns
→ In the pipelined case we know in the ideal case CPI = 1, and the clock speed = 2 GHz.
→ Time taken for one instruction in the pipelined case = (1 / 2 G) = 0.5 ns
→ Speedup = 1.6/0.5 = 3.2
Question 38 |
Consider a disk pack with 16 surfaces, 128 tracks per surface and 256 sectors per track. 512 bytes of data are stored in a bit serial manner in a sector. The capacity of the disk pack and the number of bits required to specify a particular sector in the disk are respectively:
256 Mbyte, 19 bits | |
256 Mbyte, 21 bits | |
512 Mbyte, 20 bits | |
64 GB, 28 bits |
Question 38 Explanation:
→ Given that the disk pack has 16 surfaces, 128 tracks per surface, 256 sectors per track and each sector size is 512 bytes.
→ So the disk pack capacity = 16*128*256*512 bytes = 256 MB
→ To specify a sector we need the information about surface number, track number and sector number within a track.
→ Surface number needs 4 bits as there are 16 surfaces(24), track number needs 7 bits as there are 128 tracks(27) within a surface, within a track the sector number needs 8 bits as there are 256 sectors (28).
→ Total number bits needed to specify a particular sector = 4+7+8 = 19 bits.
→ So the disk pack capacity = 16*128*256*512 bytes = 256 MB
→ To specify a sector we need the information about surface number, track number and sector number within a track.
→ Surface number needs 4 bits as there are 16 surfaces(24), track number needs 7 bits as there are 128 tracks(27) within a surface, within a track the sector number needs 8 bits as there are 256 sectors (28).
→ Total number bits needed to specify a particular sector = 4+7+8 = 19 bits.
Question 39 |
Register renaming is done in pipelined processors
as an alternative to register allocation at compile time | |
for efficient access to function parameters and local variables | |
to handle certain kinds of hazards | |
as part of address translation |
Question 39 Explanation:
→ Register renaming is used to eliminate hazards that arise due to WAR (Write After Read) and WAW(Write After Write) dependencies.
Question 40 |
In which class of Flynn’s taxonomy, Von Neumann architecture belongs to?
SISD | |
SIMD | |
MIMD | |
MISD |
Question 40 Explanation:
→ SISD (single instruction stream, single data stream) is a computer architecture in which a single uni-core processor, executes a single instruction stream, to operate on data stored in a single memory. This corresponds to the von Neumann architecture.
→ SISD is one of the four main classifications as defined in Flynn's taxonomy.
→ In this system, classifications are based upon the number of concurrent instructions and data streams present in the computer architecture. According to Michael J. Flynn, SISD can have concurrent processing characteristics.
→ Pipelined processors and superscalar processors are common examples found in most modern SISD computers.
→ Instructions are sent to the control unit from the Memory Module and are decoded and sent to the processing unit which processes on the data retrieved from Memory module and sent back to it.
→ SISD is one of the four main classifications as defined in Flynn's taxonomy.
→ In this system, classifications are based upon the number of concurrent instructions and data streams present in the computer architecture. According to Michael J. Flynn, SISD can have concurrent processing characteristics.
→ Pipelined processors and superscalar processors are common examples found in most modern SISD computers.
→ Instructions are sent to the control unit from the Memory Module and are decoded and sent to the processing unit which processes on the data retrieved from Memory module and sent back to it.
Question 41 |
Relative mode of addressing is most relevant to writing
Coroutines | |
Position-independent code | |
Shareable code | |
Interrupt Handlers |
Question 41 Explanation:
The main advantage of PC- relative addressing is that code may be position independent, i.e., it can be loaded anywhere in memory without the need to adjust any address.
Question 42 |
Consider a system with 2 level cache. Access times of Level 1 cache, Level 2 cache and main memory are 1 ns, 10 ns, and 500 ns, respectively. The hit rates of Level 1 and Level 2 caches are 0.8 and 0.9, respectively. What is the average access time of the system ignoring the search time within the cache?
13.0 | |
12.8 | |
12.6 | |
12.4 |
Question 42 Explanation:
Average access time = [H1 * T1] + [(1 - H1) * Hm * Tm]
H1 = 0.8, (1 - H1) = 0.2
H2 = 0.9, (1 - H2) = 0.1
T1 = Access time for level 1 cache = 1ns
T2 = Access time for level 2 cache = 10ns
Hm = Hit rate of main memory = 1
Tm = Access time for main memory = 500ns
Average access time = [(0.8 * 1) + (0.2 * 0.9 * 10) + (0.2)(0.1) * 1 * 500]
= 0.8 + 1.8 + 10
= 12.6ns
H1 = 0.8, (1 - H1) = 0.2
H2 = 0.9, (1 - H2) = 0.1
T1 = Access time for level 1 cache = 1ns
T2 = Access time for level 2 cache = 10ns
Hm = Hit rate of main memory = 1
Tm = Access time for main memory = 500ns
Average access time = [(0.8 * 1) + (0.2 * 0.9 * 10) + (0.2)(0.1) * 1 * 500]
= 0.8 + 1.8 + 10
= 12.6ns
Question 43 |
MOV [BX], AL type of data addressing is called ?
register | |
immediate | |
register indirect | |
register relative |
Question 43 Explanation:
Register indirect addressing means that the location of an operand is held in a register.
In register addressing mode, a register contains the operand. Depending upon the instruction, the register may be the first operand, the second operand or both.
In Immediate Addressing,an immediate operand has a constant value or an expression. When an instruction with two operands uses immediate addressing, the first operand may be a register or memory location, and the second operand is an immediate constant.
In register addressing mode, a register contains the operand. Depending upon the instruction, the register may be the first operand, the second operand or both.
In Immediate Addressing,an immediate operand has a constant value or an expression. When an instruction with two operands uses immediate addressing, the first operand may be a register or memory location, and the second operand is an immediate constant.
Question 44 |
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are
INTR & INTA
| |
RD & WR | |
S0 & S1 | |
HOLD & HLDA |
Question 44 Explanation:
HOLD (Hold) is a control signal input and HLDA (Hold acknowledge) is a control signal output.
These two signals are used for hand shaked control during DMA operation (Direct Memory Access)
These two signals are used where there is more than one CPU like devices sharing the same system bus
These two signals are used for hand shaked control during DMA operation (Direct Memory Access)
These two signals are used where there is more than one CPU like devices sharing the same system bus
Question 45 |
If a microcomputer operates at 5 MHz with an 8-bit bus and a newer version operates at 20 MHz with a 32-bit bus, the maximum speed-up possible approximately will be
2 | |
4 | |
8 | |
16 |
Question 45 Explanation:
The newer version is the best as compared to old one, but the second version has both high bandwidth as well as increased CPU speed.
20/5 = 4 and 32/8 = 4
Maximum speed up possible is 4
20/5 = 4 and 32/8 = 4
Maximum speed up possible is 4
Question 46 |
The search concept used in associative memory is
Parallel search | |
Sequential search | |
Binary search | |
Selection search |
Question 46 Explanation:
A type of computer memory from which items may be retrieved by matching some part of their content, rather than by specifying their address (hence also called associative storage or Content-addressable memory (CAM)
Associative memory makes a parallel search with the stored patterns as data files.
Associative memory makes a parallel search with the stored patterns as data files.
Question 47 |
In a DMA transfer scheme, the transfer scheme other than burst mode is
cycle technique | |
stealing technique | |
cycle stealing technique | |
cycle bypass technique |
Question 47 Explanation:
Direct memory access (DMA) is a method that allows an input/output (I/O) device to send or receive data directly to or from the main memory, bypassing the CPU to speed up memory operations.
DMA transfers can transfer either one byte at a time or all at once in burst mode. If they transfer a byte at a time, this can allow the CPU to access memory on alternating bus cycles – this is called cycle stealing since the CPU and either the DMA controller or the bus master contend for memory access.
In burst mode DMA, the CPU can be put on hold while the DMA transfer occurs and a full block of possibly hundreds or thousands of bytes can be moved.
DMA transfers can transfer either one byte at a time or all at once in burst mode. If they transfer a byte at a time, this can allow the CPU to access memory on alternating bus cycles – this is called cycle stealing since the CPU and either the DMA controller or the bus master contend for memory access.
In burst mode DMA, the CPU can be put on hold while the DMA transfer occurs and a full block of possibly hundreds or thousands of bytes can be moved.
Question 48 |
Consider a direct mapped cache with 64 blocks and a block size of 16 bytes. To what block number does the byte address 1206 map to
does not map | |
6 | |
11 | |
54 |
Question 48 Explanation:
Given data,
Direct memory cache have = 64 block
Block size = 16 Bytes
Block number does the byte address of 1206 map=?
Step-1: To find block number = Byte Address / Block size
= 1206/16
= 75.3
Step-2: Byte address 1206 map to 75th block.
Step-3: We have to find the cache block number.
Cache block number = (Block number) mod (Block size in cache)
= 75 mod 16
= 11
Direct memory cache have = 64 block
Block size = 16 Bytes
Block number does the byte address of 1206 map=?
Step-1: To find block number = Byte Address / Block size
= 1206/16
= 75.3
Step-2: Byte address 1206 map to 75th block.
Step-3: We have to find the cache block number.
Cache block number = (Block number) mod (Block size in cache)
= 75 mod 16
= 11
Question 49 |
A processor takes 12 cycles to complete an instruction I. The corresponding pipelined processor uses 6 stages with the execution times of 3, 2, 5, 4, 6 and 2 cycles respectively. What is the asymptotic speedup assuming that a very large number of instructions are to be executed?
1.83 | |
2 | |
3 | |
6 |
Question 49 Explanation:
Step-1: Speed Up= Time without Pipeline / Time with Pipeline
Step-2: It is given that without pipeline it takes 12ns to execute one instruction. Assuming there are n-instructions, time without pipeline = (12*n) ns.
Step-3: For time with pipeline, when there are k-stages in the pipeline, time taken to execute n-instructions is = (k+n-1) clock cycles.
Step-4: There are six stages in the pipeline, so k=6.
Time with pipeline = (6+n-1) clock cycles
= (n+5) clock cycles.
Step-5: It is also given that very large number of instructions are to be executed. So in the time with pipeline, (n+5) clock cycles, we can ignore 5. So time with pipeline for running large number of instructions = n clock cycles.
Step-6: 1 clock cycle time in pipeline = max. of all stage delays
= max(3, 2, 5, 4, 6, 2)
= 6ns
Now, time with pipeline= (n*6) ns
Asymptotic speedup = (12*n) / (6*n)
= 2
Step-2: It is given that without pipeline it takes 12ns to execute one instruction. Assuming there are n-instructions, time without pipeline = (12*n) ns.
Step-3: For time with pipeline, when there are k-stages in the pipeline, time taken to execute n-instructions is = (k+n-1) clock cycles.
Step-4: There are six stages in the pipeline, so k=6.
Time with pipeline = (6+n-1) clock cycles
= (n+5) clock cycles.
Step-5: It is also given that very large number of instructions are to be executed. So in the time with pipeline, (n+5) clock cycles, we can ignore 5. So time with pipeline for running large number of instructions = n clock cycles.
Step-6: 1 clock cycle time in pipeline = max. of all stage delays
= max(3, 2, 5, 4, 6, 2)
= 6ns
Now, time with pipeline= (n*6) ns
Asymptotic speedup = (12*n) / (6*n)
= 2
Question 50 |
Find the memory address of the next instruction executed by the microprocessor (8086), when operated in real mode for CS=1000 and IP=E000
10E00 | |
1E000 | |
F000 | |
1000E |
Question 51 |
How many number of times the instruction sequence below will loop before coming out of the loop?
A1: MOV AL, 00H
INC AL
JNZ A1
A1: MOV AL, 00H
INC AL
JNZ A1
1 | |
255 | |
256 | |
Will not come out of the loop |
Question 51 Explanation:
A1: MOV AL, 00H // Storing the value zero into the register AL, Now AL value is 00000000
INC AL // INCREMENT AL register value.
JNZ A1
The JNZ instruction transfers control to the specified address if the value in the accumulator is not 0
Step-1: AL = 0000 0000
Step-2:Next step is for increment the value of AL.
Step-3: Checking the jump condition
The above steps shall repeat until the accumulator value is not equal to zero.
→AL will keep on incrementing and after 255th iteration the value will become 1111 1111
→Again the condition is checked and incremented, now in 256th iteration AL = 1 0000 0000.
→As AL is an 8-bit register, 1 is discarded and the value becomes 0000 0000 and conditional jump to A1 occurs.
→So, total 256 iterations.
INC AL // INCREMENT AL register value.
JNZ A1
The JNZ instruction transfers control to the specified address if the value in the accumulator is not 0
Step-1: AL = 0000 0000
Step-2:Next step is for increment the value of AL.
Step-3: Checking the jump condition
The above steps shall repeat until the accumulator value is not equal to zero.
→AL will keep on incrementing and after 255th iteration the value will become 1111 1111
→Again the condition is checked and incremented, now in 256th iteration AL = 1 0000 0000.
→As AL is an 8-bit register, 1 is discarded and the value becomes 0000 0000 and conditional jump to A1 occurs.
→So, total 256 iterations.
Question 52 |
How much speed do we gain by using the cache, when cache is used 80% of the time? Assume cache is faster than main memory
5.27 | |
2.00 | |
4.16 | |
6.09 |
Question 52 Explanation:
Speed Gain=(Memory Access Time without Cache)/( Memory Access Time with Cache).
Let M is the memory access time and C is the Cache access time.
Then,
Speed Gain= M/ (0.8M +0.2C).
Note: Speed Gain can be computed if we know how faster is the Cache when compared with Memory
Let M is the memory access time and C is the Cache access time.
Then,
Speed Gain= M/ (0.8M +0.2C).
Note: Speed Gain can be computed if we know how faster is the Cache when compared with Memory
Question 53 |
A pipeline P operating at 400 MHz has a speedup factor of 6 and operating at 70% efficiency. How many stages are there in the pipeline?
5 | |
6 | |
8 | |
9 |
Question 53 Explanation:
Given Data,
Speedup factor=6.
efficiency=70%
=0.7
Step-1: Here, we have to find out number of stages.
Efficiency = Speedup factor/ Number of stages
0.7 = 6 / Number of stages
Step-2: Number of stages = 8.56
= 9
Speedup factor=6.
efficiency=70%
=0.7
Step-1: Here, we have to find out number of stages.
Efficiency = Speedup factor/ Number of stages
0.7 = 6 / Number of stages
Step-2: Number of stages = 8.56
= 9
Question 54 |
A processor is fetching instructions at the rate of 1 MIPS. A DMA module is used to transfer characters to RAM from a device transmitting at 9600 bps. How much time will the processor be slowed down due to DMA activity?
9.6 ms | |
4.8 ms | |
2.4 ms | |
1.2 ms |
Question 54 Explanation:
Given data,
A processor is fetching instructions at the rate=1 MIPS.
DMA module transferring characters=9600 bps
Step-1: DMA module transferring characters= 9600/8 bps
= 1200 bps
Step-2: Here, we have to find out slow down in milliseconds.
Slowdown = 1200/106
= 12*1000/104ms
= 1.2 ms
A processor is fetching instructions at the rate=1 MIPS.
DMA module transferring characters=9600 bps
Step-1: DMA module transferring characters= 9600/8 bps
= 1200 bps
Step-2: Here, we have to find out slow down in milliseconds.
Slowdown = 1200/106
= 12*1000/104ms
= 1.2 ms
Question 55 |
Consider a 33 MHz CPU based system. What is the number of wait states required if it is interfaced with a 60 ns memory? Assume a maximum of 10 ns delay for additional circuitry like buffering and decoding.
0 | |
1 | |
2 | |
3 |
Question 55 Explanation:
A wait state is a situation in which a computer program or processor is waiting for the completion of some event before resuming activity. A program or process in a wait state is inactive for the duration of the wait stat
When a computer processor works at a faster clock speed (expressed in MHz or millions of cycles per second) than the random access memory ( RAM ) that sends it instructions, it is set to go into a wait state for one or more clock cycles so that it is synchronized with RAM speed. In general, the more time a processor spends in wait states, the slower the performance of that processor.
From the given question, we will get total memory access time by combining access time and delay.
CPU frequency = 33 MHz
1 clock time = 1 / (33 MHz) = (1/33)*10-6 = 30.30 ns.
Total memory access time = 60 ns + 10 ns = 70 ns.
Total number of wait states = Total number of cycle needed
= Total memory access time / CPU frequency
=70 ns / (30.30 ns) = 2.31 (equivalent to 3 cycles)
When a computer processor works at a faster clock speed (expressed in MHz or millions of cycles per second) than the random access memory ( RAM ) that sends it instructions, it is set to go into a wait state for one or more clock cycles so that it is synchronized with RAM speed. In general, the more time a processor spends in wait states, the slower the performance of that processor.
From the given question, we will get total memory access time by combining access time and delay.
CPU frequency = 33 MHz
1 clock time = 1 / (33 MHz) = (1/33)*10-6 = 30.30 ns.
Total memory access time = 60 ns + 10 ns = 70 ns.
Total number of wait states = Total number of cycle needed
= Total memory access time / CPU frequency
=70 ns / (30.30 ns) = 2.31 (equivalent to 3 cycles)
Question 56 |
There are 200 tracks on a disc platter and the pending requests have come in the order – 36, 69, 167, 76, 42, 51, 126, 12 and 199. Assume the arm is located at the 100 track and moving towards track 199. If the sequence of disc access is 126, 167, 199, 12, 36, 42, 51, 69 and 76 then which disc access scheduling policy is used?
Elevator | |
Shortest seek-time first | |
C-SCAN | |
First Come First Served |
Question 56 Explanation:
Total tracks are :200
Tracks order is 36, 69, 167, 76, 42, 51, 126, 12 and 199
Track position is at 100 and moving towards 199.
sequence of disc access is 126, 167, 199, 12, 36, 42, 51, 69 and 76
From the above sequence , we can observe that disc moving from 100 to 126 from there to moving right side direction until last disc 199
From the last disc(199) to first disc(12) and from there to next disc(36) and so on.
C-SCAN sweeps the disk from end-to-end, but as soon it reaches one of the end tracks it then moves to the other end track without servicing any requesting location. As soon as it reaches the other end track it then starts servicing and grants requests headed to its direction
Tracks order is 36, 69, 167, 76, 42, 51, 126, 12 and 199
Track position is at 100 and moving towards 199.
sequence of disc access is 126, 167, 199, 12, 36, 42, 51, 69 and 76
From the above sequence , we can observe that disc moving from 100 to 126 from there to moving right side direction until last disc 199
From the last disc(199) to first disc(12) and from there to next disc(36) and so on.
C-SCAN sweeps the disk from end-to-end, but as soon it reaches one of the end tracks it then moves to the other end track without servicing any requesting location. As soon as it reaches the other end track it then starts servicing and grants requests headed to its direction
Question 57 |
CMOS is a Computer Chip on the motherboard, which is :
RAM | |
ROM | |
EPROM | |
Auxiliary storage
|
Question 57 Explanation:
Complementary metal-oxide Semiconductor(CMOS) is a random access memory which stores computer start up information which is used by BIOS.
Question 58 |
Match the items in List-I and List-II :
List-I List-II (a) Interrupts which can be delayed when a much highest (i) Normal priority interrupt has occurred (b) Unplanned interrupts which occur while executing (ii) Synchronous a program (c) Source of interrupt is in phase with the system clock (iii) Maskable (iv) Exception
(a)-(ii), (b)-(i), (b)-(iv)
| |
(a)-(ii), (b)-(iv), (b)-(iii) | |
(a)-(iii), (b)-(i), (b)-(ii)
| |
(a)-(iii), (b)-(iv), (b)-(ii)
|
Question 58 Explanation:
Maskable Interrupt :
Maskable Interrupts are those which can be masked/delayed when a higher priority interrupt occurs.
Exception :
Exception are the unplanned interrupts that occur while executing a program. Divide by zero is an example of Exception.
Synchronous:
Synchronous clocks will regularly synchronize their time with a master clock. The connection can be direct (wired), or over the air (radio, wifi or similar). The connections can be at a regular intervals, on demand or a mix.
Maskable Interrupts are those which can be masked/delayed when a higher priority interrupt occurs.
Exception :
Exception are the unplanned interrupts that occur while executing a program. Divide by zero is an example of Exception.
Synchronous:
Synchronous clocks will regularly synchronize their time with a master clock. The connection can be direct (wired), or over the air (radio, wifi or similar). The connections can be at a regular intervals, on demand or a mix.
Question 59 |
Which of the following mapping is not used for mapping process in cache memory?
Associative mapping | |
Direct mapping
| |
Set-Associative mapping
| |
Segmented - page mapping |
Question 59 Explanation:
Segmented - page mapping is the mapping not used for mapping process in cache memory.
Question 60 |
In 8085 microprocessor, what is the output of following program ?
LDA 8000H MVI B, 30H ADD B STA 8001HRead a number from input port and store it in memory
| |
Read a number from input device with address 8000H and store it in memory at location 8001H
| |
Read a number from memory at location 8000H and store it in memory location 8001H | |
Load A with data from input device with address 8000H and display it on the output device with address 8001H |
Question 60 Explanation:
→ 1st instruction "LDA 8000H" transfers data from memory location 8000H to Accumulator.
→ 2nd instruction "MVI B, 30H" moves 30H to register B.
→ 3rd instruction "ADD B" adds contents of B with Accumulator and stores it back to Accumulator. So basically the contents of Accumulator are incremented by 30H.
→ 4th instruction "STA 8001H" stores the contents of Accumulator in memory location 8001H. As none of the choices include the 'addition operation', we need to choose appropriate option from the given options.
→ Option 4 mentions about loading the content from 8000H to accumulator A. Hence option 4 is more appropriate.
→ 2nd instruction "MVI B, 30H" moves 30H to register B.
→ 3rd instruction "ADD B" adds contents of B with Accumulator and stores it back to Accumulator. So basically the contents of Accumulator are incremented by 30H.
→ 4th instruction "STA 8001H" stores the contents of Accumulator in memory location 8001H. As none of the choices include the 'addition operation', we need to choose appropriate option from the given options.
→ Option 4 mentions about loading the content from 8000H to accumulator A. Hence option 4 is more appropriate.
Question 61 |
The ALU uses ____ to store intermediate result.
Cache | |
Registers | |
Accumulators | |
Stack |
Question 61 Explanation:
→ An accumulator is a register for short-term, intermediate storage of arithmetic and logic data in a computer's CPU (central processing unit).
→ A processor register (CPU register) is one of a small set of data holding places that are part of the computer processor.
→ Cache memory is a small-sized type of volatile computer memory that provides high-speed data access to a processor and stores frequently used computer programs, applications and data.
→ A processor register (CPU register) is one of a small set of data holding places that are part of the computer processor.
→ Cache memory is a small-sized type of volatile computer memory that provides high-speed data access to a processor and stores frequently used computer programs, applications and data.
Question 62 |
Identify the true statement from the given statements. Program relocation at run time:
- Requires transfer complete block to some memory locations
- Requires both base address and relative address
- Requires only absolute address
(1) | |
(1) and (2) | |
(1),(2) and (3) | |
(1) and (3) |
Question 62 Explanation:
→ Program relocation at run time transfer complete block to some memory locations.
→ This requires as base address and block should be relatively addressed through this base address .This require both base address and relative address
→ This requires as base address and block should be relatively addressed through this base address .This require both base address and relative address
Question 63 |
How many address lines are needed to address each memory location in a 2048*4 memory chip?
10 | |
11 | |
8 | |
12 |
Question 63 Explanation:
● Given Memory chip size is 2048x4
● The memory words are 2048 (211 ) So 11 bits are needed for address lines.
● The memory words are 2048 (211 ) So 11 bits are needed for address lines.
Question 64 |
MIMD stands for
Multiple instruction multiple data | |
multiple instruction memory data | |
memory instruction multiple data | |
multiple information memory data |
Question 64 Explanation:
In computing, MIMD (multiple instruction, multiple data) is a technique employed to achieve parallelism. Machines using MIMD have a number of processors that function asynchronously and independently. At any time, different processors may be executing different instructions on different pieces of data
Question 65 |
When a subroutine is called, then address of the instruction following the CAL instruction is stored in/on the
Stack pointer | |
Accumulator | |
Program Counter | |
Stack |
Question 65 Explanation:
● The program counter (PC), commonly called the instruction pointer (IP) in Intel x86 and Itanium microprocessors, and sometimes called the instruction address register (IAR),
the instruction counter, or just part of the instruction sequencer,is a processor register that indicates where a computer is in its program sequence.
● PC is incremented after fetching an instruction, and holds the memory address of ("points to") the next instruction that would be executed.
● Processors usually fetch instructions sequentially from memory, but control transfer instructions change the sequence by placing a new value in the PC. These include branches (sometimes called jumps), subroutine calls, and returns..
● PC is incremented after fetching an instruction, and holds the memory address of ("points to") the next instruction that would be executed.
● Processors usually fetch instructions sequentially from memory, but control transfer instructions change the sequence by placing a new value in the PC. These include branches (sometimes called jumps), subroutine calls, and returns..
Question 66 |
Start and stop bits are used in serial communication for
Error detection | |
Error Correction | |
Synchronization | |
Slowing down the communication |
Question 66 Explanation:
● The start and stop bits are used in asynchronous communication as a means of timing or synchronizing the data characters being transmitted.
● Without the use of these bits, the sending and receiving systems will not know where one character ends and another begins.
● Without the use of these bits, the sending and receiving systems will not know where one character ends and another begins.
Question 67 |
Micro programming is a technique for
Writing small programs effectively | |
Programming output/input routines | |
programming the microprocessors | |
Programming the control steps of a computer |
Question 67 Explanation:
● Microprogramming is a technique to implement the control logic necessary to execute instructions within a processor.
● It is based on the general idea of fetching low-level microinstructions from a control store and deriving the appropriate control signals to be active for a single clock cycle, as well as microprogram sequencing information, from each microinstruction.
● Although hybrid techniques exist, microprogramming is generally contrasted with hardwired implementation techniques.
● It is based on the general idea of fetching low-level microinstructions from a control store and deriving the appropriate control signals to be active for a single clock cycle, as well as microprogram sequencing information, from each microinstruction.
● Although hybrid techniques exist, microprogramming is generally contrasted with hardwired implementation techniques.
Question 68 |
An instruction used to set the carry flag in a computer can be classified as
data transfer | |
process control | |
logical | |
program control |
Question 68 Explanation:
● The carry flag is a single bit in a system status register/flag register used to indicate when an arithmetic carry or borrow has been generated out of the most significant arithmetic logic unit (ALU) bit position.
● The carry flag enables numbers larger than a single ALU width to be added/subtracted by carrying (adding) a binary digit from a partial addition/subtraction to the least significant bit position of a more significant word.
● It is also used to extend bit shifts and rotates in a similar manner on many processors (sometimes done via a dedicated X flag).
● For subtractive operations, two (opposite) conventions are employed as most machines set the carry flag on borrow while some machines (such as the 6502 and the PIC) instead reset the carry flag on borrow (and vice versa).
● The carry flag enables numbers larger than a single ALU width to be added/subtracted by carrying (adding) a binary digit from a partial addition/subtraction to the least significant bit position of a more significant word.
● It is also used to extend bit shifts and rotates in a similar manner on many processors (sometimes done via a dedicated X flag).
● For subtractive operations, two (opposite) conventions are employed as most machines set the carry flag on borrow while some machines (such as the 6502 and the PIC) instead reset the carry flag on borrow (and vice versa).
Question 69 |
If a processor does not have any stack pointer register, then
if cannot have subroutine call instruction | |
it can have subroutine call instruction, but no nested subroutine calls are possible, but no nested subroutine calls | |
nested subroutine calls are possible, but interrupts are not | |
all sequences of subroutine calls and also interrupts are possible |
Question 69 Explanation:
● A subroutine is a reusable program module. A main program can call or jump to the subroutine one or more times.
● The stack is an area of memory; the stack pointer is the address of the last value pushed onto the stack
● The main thing you will be using the stack for is saving data when a subroutine is called.
● You call a subroutine that is going to calculate some value and pass it back to the main program. After you call the subroutine, you can just push all the data onto the stack before executing any instructions in the subroutine. The subroutine can then use all the registers for its internal use and store the data that the main program needs in one of the memory locations. At the end of the subroutine, you can pop the stored data off of the stack and then return control to the main program.
● If stack pointer register is not available then activation records in the stack cannot be created. So it cannot have subroutine call instruction.
● The stack is an area of memory; the stack pointer is the address of the last value pushed onto the stack
● The main thing you will be using the stack for is saving data when a subroutine is called.
● You call a subroutine that is going to calculate some value and pass it back to the main program. After you call the subroutine, you can just push all the data onto the stack before executing any instructions in the subroutine. The subroutine can then use all the registers for its internal use and store the data that the main program needs in one of the memory locations. At the end of the subroutine, you can pop the stored data off of the stack and then return control to the main program.
● If stack pointer register is not available then activation records in the stack cannot be created. So it cannot have subroutine call instruction.
Question 70 |
In a microcomputer, WAIT states are used to
make the processor wait during a DMA operation | |
make the processor wait during a power interrupt processing | |
make the processor wait during a power shutdown | |
interface slow peripherals to the processor |
Question 70 Explanation:
● A wait state is a situation in which a computer program or processor is waiting for the completion of some event before resuming activity. A program or process in a wait state is inactive for the duration of the wait state.
● A wait state is a delay experienced by a computer processor when accessing external memory or another device that is slow to respond.
● A wait state is a delay experienced by a computer processor when accessing external memory or another device that is slow to respond.
Question 71 |
The seek time of a disk is 30ms. It rotates at the rate of 30 rotations/second. The capacity of each track is 300 words. The access time is (approximately)
62ms | |
60ms | |
50ms | |
47ms |
Question 71 Explanation:
Hard Disk Access time is the total elapsed time between the initiation of a particular request for data and receipt of the first bit of that data.
Given seek time of disk = 30ms
Rotation rate is 30 rotations/second.
The capacity of each track is 300 words
Given seek time of disk = 30ms
Rotation rate is 30 rotations/second.
The capacity of each track is 300 words
Question 72 |
A Computer uses a memory unit with 256K word of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code and a register code part to specify one of 64 registers and an address part. How many bits are there in operation code, the register code part and the address part?
7, 7, 18
| |
18, 7, 7
| |
7, 6, 18 | |
6, 7, 18 |
Question 72 Explanation:
An instruction size is given as 32-bits.
Now, the instruction is divided into four parts :
An indirect bit
Register code part : Since number of registers given as 64(26) so to identify each register uniquely 6-bits are needed.
Address part : 256K(218) word memory is mentioned so to identify each word uniquely 18-bits are needed.
Operation code:
Size of Operation code = Complete instruction size - (size of indirect bit + size of register code + size of address part)
Size of Operation code = 7-bits
Now, the instruction is divided into four parts :
An indirect bit
Register code part : Since number of registers given as 64(26) so to identify each register uniquely 6-bits are needed.
Address part : 256K(218) word memory is mentioned so to identify each word uniquely 18-bits are needed.
Operation code:
Size of Operation code = Complete instruction size - (size of indirect bit + size of register code + size of address part)
Size of Operation code = 7-bits
Question 73 |
Consider a system with 2 level cache. Access times of Level 1, Level 2 cache and main memory are 0.5 ns, 5 ns and 100 ns respectively. The hit rates of Level 1 and Level 2 caches are 0.7 and 0.8 respectively. What is the average access time of the system ignoring the search time within cache?
20.75 ns
| |
7.55 ns | |
24.35 ns
| |
35.20 ns |
Question 73 Explanation:
Average access time = level 1 hit rate( level 1 access time) + (level1 miss rate)(level 2 hit rate(level 2 access time)+ (level 1 miss rate)( level 2 miss rate) (main memory access time)
Average access time = 0.7(0.5) + 0.3(0.8)(5) + 0.3(0.2)(100)
Average access time = 7.55 ns
Average access time = 0.7(0.5) + 0.3(0.8)(5) + 0.3(0.2)(100)
Average access time = 7.55 ns
Question 74 |
Consider the following x86 - assembly language instructions :
-
MOV AL, 153
NEG AL
The contents of the destination register AL (in 8-bit binary notation), the status of Carry Flag(CF) and Sign Flag(SF) after the execution of above instructions, are
AL = 0110 0110; CF = 0; SF = 0 | |
AL = 0110 0111; CF = 0; SF = 1
| |
AL = 0110 0110; CF = 1; SF = 1 | |
AL = 0110 0111; CF = 1; SF = 0 |
Question 74 Explanation:
153 = 1001 1001
NEG(1001 1001) = 1's complement of(1001 1001) = 0110 0110
MOV AL 153
AL = 1001 1001
NEG AL
AL = 0110 0101
MSB is 0. Hence SF=0
By default CF=0 and it will not change with above operations (MOV, NEG)
So, option 1 is the correct answer.
Note: Original UGC Key given correct answer is option-(4).
NEG(1001 1001) = 1's complement of(1001 1001) = 0110 0110
MOV AL 153
AL = 1001 1001
NEG AL
AL = 0110 0101
MSB is 0. Hence SF=0
By default CF=0 and it will not change with above operations (MOV, NEG)
So, option 1 is the correct answer.
Note: Original UGC Key given correct answer is option-(4).
Question 75 |
Consider the following statements :
- (i) Auto increment addressing mode is useful in creating self-relocating code.
(ii) If auto addressing mode is included in an instruction set architecture, then
an additional ALU is required for effective address calculation.
(iii) In auto increment addressing mode, the amount of increment depends on
the size of the data item accessed.
Which of the above statements is/are true ?
Choose the correct answer from the code given below :
Code :(iii) only | |
(ii) and (iii) only | |
(i) and (ii) only
| |
(ii) only |
Question 75 Explanation:
→ Auto increment addressing mode is useful in implementing arrays.
→ After determining the effective address, the value in the base register is incremented by the size of the data item that is to be accessed. For example, (A7)+ would access the content of the address register A7, then increase the address pointer of A7 by 1 (usually 1 word).
→ Within a loop, this addressing mode can be used to step through all the elements of an array or vector.
→ After determining the effective address, the value in the base register is incremented by the size of the data item that is to be accessed. For example, (A7)+ would access the content of the address register A7, then increase the address pointer of A7 by 1 (usually 1 word).
→ Within a loop, this addressing mode can be used to step through all the elements of an array or vector.
Question 76 |
What is the average access time for a Drum rotating at 4000 revolutions per minute?
2.5 milliseconds | |
5.0 milliseconds | |
7.5 milliseconds | |
4.0 milliseconds |
Question 76 Explanation:
→ 4000 revolution per minute means 60/4000 seconds for 1 revolution.
→ Average access time is time to complete 1/2 revolution= 7.5milliseconds.
→ Average access time is time to complete 1/2 revolution= 7.5milliseconds.
Question 77 |
Comparing the time T1 taken for a single instruction on a pipelined CPU, with time T2 taken on a no-pipelined but identical CPU, we can say that___?
T1=T2 | |
T1>T2 | |
T1 | |
T1 is T2 plus time taken for one instruction fetch cycle |
Question 77 Explanation:
PIPELINING SYSTEM:
Pipelining is an implementation technique where multiple instructions are overlapped in execution. It has a high throughput (amount of instructions executed per unit time). In pipelining, many instructions are executed at the same time and execution is completed in fewer cycles. The pipeline is filled by the CPU scheduler from a pool of work which is waiting to occur. Each execution unit has a pipeline associated with it, so as to have work pre-planned. The efficiency of pipelining system depends upon the effectiveness of CPU scheduler.
NON- PIPELINING SYSTEM:
All the actions (fetching, decoding, execution of instructions and writing the results into the memory) are grouped into a single step. It has a low throughput. Only one instruction is executed per unit time and execution process requires more number of cycles. The CPU scheduler in the case of non-pipelining system merely chooses from the pool of waiting work when an execution unit gives a signal that it is free. It is not dependent on CPU scheduler.
Pipelining is an implementation technique where multiple instructions are overlapped in execution. It has a high throughput (amount of instructions executed per unit time). In pipelining, many instructions are executed at the same time and execution is completed in fewer cycles. The pipeline is filled by the CPU scheduler from a pool of work which is waiting to occur. Each execution unit has a pipeline associated with it, so as to have work pre-planned. The efficiency of pipelining system depends upon the effectiveness of CPU scheduler.
NON- PIPELINING SYSTEM:
All the actions (fetching, decoding, execution of instructions and writing the results into the memory) are grouped into a single step. It has a low throughput. Only one instruction is executed per unit time and execution process requires more number of cycles. The CPU scheduler in the case of non-pipelining system merely chooses from the pool of waiting work when an execution unit gives a signal that it is free. It is not dependent on CPU scheduler.
Question 78 |
Which memory is difficult to interface with processor?
Static memory | |
Dynamic memory | |
ROM | |
None of the option |
Question 78 Explanation:
Dynamic random-access memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a separate tiny capacitor within an integrated circuit.
The electric charge on the capacitors slowly leaks off, so without intervention the data on the chip would soon be lost.
To prevent this, DRAM requires an external memory refresh circuit which periodically rewrites the data in the capacitors, restoring them to their original charge. This refresh process is the defining characteristic of dynamic random-access memory, in contrast to static random-access memory (SRAM) which does not require data to be refreshed.
The electric charge on the capacitors slowly leaks off, so without intervention the data on the chip would soon be lost.
To prevent this, DRAM requires an external memory refresh circuit which periodically rewrites the data in the capacitors, restoring them to their original charge. This refresh process is the defining characteristic of dynamic random-access memory, in contrast to static random-access memory (SRAM) which does not require data to be refreshed.
Question 79 |
For a memory system, the cycle time is
Same as the access time | |
Longer than the access time | |
Shorter than the access time | |
Multiple of the access time |
Question 79 Explanation:
For Memory Access, Cycle time=Latency time+Transfer Time
Latency time is overhead of finding the right memory location and preparing to access it.
Transfer Time = Time required to transfer the data.
Hence cycle time is longer than access time
Latency time is overhead of finding the right memory location and preparing to access it.
Transfer Time = Time required to transfer the data.
Hence cycle time is longer than access time
Question 80 |
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4 x 6 array, where each chip is 8K x 4 bits?
13 | |
14 | |
16 | |
17 |
Question 80 Explanation:
Size of each Ram chip = 8K x 4 bits = 23 x 210x 22 ⇒ 215 bits = 212 bytes
Number of chips required = 6 x 4 = 24 = 5 bits
So, total number of bits required = 12 + 5 = 17 bits
Number of chips required = 6 x 4 = 24 = 5 bits
So, total number of bits required = 12 + 5 = 17 bits
Question 81 |
Consider data given in the above question. What is the minimum number of page colours needed to guarantee that no two synonyms map to different sets in the processor cache of this computer?
2 | |
4 | |
8 | |
16 |
Question 81 Explanation:
1 MB 16-way set associative virtually indexed physically tagged cache(VIPT).
The cache block size is 64 bytes.
The cache block size is 64 bytes.
Question 82 |
A disk has 200 tracks(numbered 0 through 199). At a given time, it was servicing the request of reading data from track 120 and at the previous request, service was for track 90. The pending requests(in order of their arrival) are for track numbers
30 70 115 130 110 80 20 25.
How many times will the head change its direction for the disk scheduling policies SSTF(Shortest Seek Time First) and FCFS(First come first serve)?
2 and 3 | |
3 and 3 | |
3 and 4 | |
4 and 4 |
Question 82 Explanation:
According to Shortest Seek Time First:
90-> 120-> 115-> 110-> 130-> 80-> 70-> 30-> 25-> 20
Change of direction(Total 3); 120->15; 110->130; 130->80
According to First Come First Serve:
90-> 120-> 30-> 70-> 115-> 130-> 110-> 80-> 20-> 25
Change of direction(Total 4); 120->30; 30->70; 130->110;20->25
90-> 120-> 115-> 110-> 130-> 80-> 70-> 30-> 25-> 20
Change of direction(Total 3); 120->15; 110->130; 130->80
According to First Come First Serve:
90-> 120-> 30-> 70-> 115-> 130-> 110-> 80-> 20-> 25
Change of direction(Total 4); 120->30; 30->70; 130->110;20->25
Question 83 |
The part of machine level instruction, which tells the central processor what has to be done, is
Operation code | |
Address | |
locator | |
Flip flop |
Question 83 Explanation:
An opcode (abbreviated from operation code) is the portion of a machine language instruction that specifies the operation to be performed. Beside the opcode itself, most instructions also specify the data they will process, in the form of operands.
In addition to opcodes used in the instruction set architectures of various CPUs, which are hardware devices, they can also be used in abstract computing machines as part of their byte code specifications.
A flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs
In addition to opcodes used in the instruction set architectures of various CPUs, which are hardware devices, they can also be used in abstract computing machines as part of their byte code specifications.
A flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs
Question 84 |
Which of the following need not necessarily be saved on a context switch between processes?
Program counter | |
IO status information | |
CPU registers | |
Translation lookaside buffer |
Question 84 Explanation:
→ Actually TLB (or) Cache memory to ensure correct program resumption.
→ With TLB (or) Cache memory we can get better performance but not mandatory.
→ Program counter, stack, I/O status information and registers must be saved on a context switch between processes.
→ With TLB (or) Cache memory we can get better performance but not mandatory.
→ Program counter, stack, I/O status information and registers must be saved on a context switch between processes.
Question 85 |
CPU register to perform storage of arithmetic and logic results is called:
Instruction register | |
Program counter | |
Accumulator | |
Instruction Decoder |
Question 85 Explanation:
→ An accumulator is a register in which intermediate arithmetic and logic results are stored.
→ In a computer's central processing unit (CPU), the accumulator is a register in which intermediate arithmetic and logic results are stored. Without a register like an accumulator, it would be necessary to write the result of each calculation (addition, multiplication, shift, etc.) to main memory, perhaps only to be read right back again for use in the next operation.
→ Access to main memory is slower than access to a register like the accumulator because the technology used for the large main memory is slower (but cheaper) than that used for a register. Early electronic computer systems were often split into two groups, those with accumulators and those without.
→ In a computer's central processing unit (CPU), the accumulator is a register in which intermediate arithmetic and logic results are stored. Without a register like an accumulator, it would be necessary to write the result of each calculation (addition, multiplication, shift, etc.) to main memory, perhaps only to be read right back again for use in the next operation.
→ Access to main memory is slower than access to a register like the accumulator because the technology used for the large main memory is slower (but cheaper) than that used for a register. Early electronic computer systems were often split into two groups, those with accumulators and those without.
Question 86 |
The quantity of very long word is:
32 bits | |
64 bits | |
128 bits | |
256 bits |
Question 86 Explanation:
A double word is a single unit of data expressing two adjacent words (a word is a standard unit of data for a certain processor architecture). For instance, if a single word is 16-bits in size, a double word would be 32-bits. A double word can doubled a second time, which turns it into a very long word that is 64-bits.
Question 87 |
Suppose the pipelined stages take {15,8,25,4,8} nanoseconds(ns) respectively. With a buffering delay of 5ns. Two pipelined implementation of the processor are used?
(i) A naive pipeline implementation(NP) and
(ii) An efficient pipeline(EP) where the third stage is splitted into {12ns, 5ns and 8ns} respectively.
The speedup achieved by EP over NP in executing 100 independent instructions with no hazards is:
1.471 | |
1.517 | |
1.638 | |
1.567 |
Question 87 Explanation:
Naive Pipeline implementation:
The stage delays are {15,8,25,4,8}. And buffer delay = 5ns
So clock cycle time = max of stage delays + buffer delay = max{15,8,25,4,8}+5 = 25+5 = 30ns
Execution time for n-instructions in a pipeline with k-stages = (k+n-1) clock cycles = (k+n-1)* clock cycle time
In this case execution time for 100 instructions in the pipeline with 5-stages
= (5+100-1)*30ns = 104*30 = 3120ns
Efficient Pipeline implementation: The 3rd phase is split into 3 stages with execution times of 12ns, 5ns and 8ns
New stage delays in this case = {15, 8, 12, 5, 8, 4, 8}
Buffer delay is the same 5ns.
So clock cycle time = max of stage delays + buffer delay = max{15, 8, 12, 5, 8, 4, 8}+5 = 15+5 = 20ns
Execution time = (k+n-1) clock cycles = (k+n-1)* clock cycle time
In this case no. of pipeline stages, k = 7
No. of instructions = 100
Execution time = (7+100-1)*20 = 106*20 = 2120ns
Speed up of Efficient pipeline over naive pipeline = Naive pipeline execution time / efficient pipeline execution time
= 3120 / 2120
~= 1.471
So clock cycle time = max of stage delays + buffer delay = max{15,8,25,4,8}+5 = 25+5 = 30ns
Execution time for n-instructions in a pipeline with k-stages = (k+n-1) clock cycles = (k+n-1)* clock cycle time
In this case execution time for 100 instructions in the pipeline with 5-stages
= (5+100-1)*30ns = 104*30 = 3120ns
Efficient Pipeline implementation: The 3rd phase is split into 3 stages with execution times of 12ns, 5ns and 8ns
New stage delays in this case = {15, 8, 12, 5, 8, 4, 8}
Buffer delay is the same 5ns.
So clock cycle time = max of stage delays + buffer delay = max{15, 8, 12, 5, 8, 4, 8}+5 = 15+5 = 20ns
Execution time = (k+n-1) clock cycles = (k+n-1)* clock cycle time
In this case no. of pipeline stages, k = 7
No. of instructions = 100
Execution time = (7+100-1)*20 = 106*20 = 2120ns
Speed up of Efficient pipeline over naive pipeline = Naive pipeline execution time / efficient pipeline execution time
= 3120 / 2120
~= 1.471
Question 88 |
When we move from the outermost track to the innermost track in a magnetic disk, then density(bits per linear inch)
increases | |
decreases | |
remains the same | |
either remains constant or decreases |
Question 88 Explanation:
→ we move from the outermost track to the innermost track in a magnetic disk, then density(bits per linear inch) increases
→ The density, in bits per linear inch, increases as we move from the outermost track to the innermost track (this same phenomenon is present in a phonograph record).
→ The density, in bits per linear inch, increases as we move from the outermost track to the innermost track (this same phenomenon is present in a phonograph record).
Question 89 |
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor?
Pointers | |
Arrays | |
Records | |
All of these |
Question 89 Explanation:
→ Pointer access requires indirect addressing which can be simulated with indexed addressing or register indirect addressing but not with direct and immediate addressing.
→ An array and record access needs a pointer access. So, options (A), (B) and (C) cannot be implemented on such a processor.
→ Now to handle recursive procedure we need to use stack. A local variable inside the stack will be accessed as *(SP+Offset) which is nothing but a pointer access and requires indirect addressing. Usually this is done by moving the SP value to the base register and then using base register addressing to avoid unnecessary memory access for indirect addressing but not possible with just direct and immediate addressing.
→ An array and record access needs a pointer access. So, options (A), (B) and (C) cannot be implemented on such a processor.
→ Now to handle recursive procedure we need to use stack. A local variable inside the stack will be accessed as *(SP+Offset) which is nothing but a pointer access and requires indirect addressing. Usually this is done by moving the SP value to the base register and then using base register addressing to avoid unnecessary memory access for indirect addressing but not possible with just direct and immediate addressing.
Question 90 |
The number of address lines in a memory chip of size 8192*8 is
8 | |
12 | |
13 | |
16 |
Question 90 Explanation:
At every point in time, each address line can be one of two states (high or low). Some basic counting shows that N address lines can address 2 n memory locations.
This problem can be solved using an equation
2 n = x; where n is the number of address lines and x is the memory space
2 n = 8192 = 2 13 n = 13
Total number of address line required is 13.
This problem can be solved using an equation
2 n = x; where n is the number of address lines and x is the memory space
2 n = 8192 = 2 13 n = 13
Total number of address line required is 13.
Question 91 |
The register which keeps track of the execution of a program and which contains the memory address of the instruction currently being execution is called
Index register | |
Memory address register | |
Program counter | |
Instruction register |
Question 91 Explanation:
● A program counter is a register in a computer processor that contains the address (location) of the instruction being executed at the current time.
● As each instruction is fetched, the program counter increases its stored value by 1.
● After each instruction is fetched, the program counter points to the next instruction in the sequence. When the computer restarts or is reset, the program counter normally reverts to 0.
● As each instruction is fetched, the program counter increases its stored value by 1.
● After each instruction is fetched, the program counter points to the next instruction in the sequence. When the computer restarts or is reset, the program counter normally reverts to 0.
Question 92 |
The register which holds the address of the location to or from which data are to be transferred is called
index register | |
instruction register | |
memory address register | |
memory data register |
Question 92 Explanation:
● The Memory Address Register (MAR) is the CPU register that either stores the memory address from which data will be fetched from the CPU, or the address to which data will be sent and stored.
● In other words, MAR holds the memory location of data that needs to be accessed. When reading from memory, data addressed by MAR is fed into the MDR (memory data register) and then used by the CPU. When writing to memory, the CPU writes data from MDR to the memory location whose address is stored in MAR. MAR which is found inside the CPU goes either to the RAM(Random Access Memory) or Cache.
● The Memory Address Register is half of a minimal interface between a microprogram and computer storage. The other half is a memory data register.
● In general, MAR is a parallel load register that contains the next memory address to be manipulated. For example, the next address to be read or written. is reset, the program counter normally reverts to 0.
● In other words, MAR holds the memory location of data that needs to be accessed. When reading from memory, data addressed by MAR is fed into the MDR (memory data register) and then used by the CPU. When writing to memory, the CPU writes data from MDR to the memory location whose address is stored in MAR. MAR which is found inside the CPU goes either to the RAM(Random Access Memory) or Cache.
● The Memory Address Register is half of a minimal interface between a microprogram and computer storage. The other half is a memory data register.
● In general, MAR is a parallel load register that contains the next memory address to be manipulated. For example, the next address to be read or written. is reset, the program counter normally reverts to 0.
Question 93 |
The addressing mode used in the instruction PUSH B is
Direct | |
register | |
Register indirect | |
Immediate |
Question 93 Explanation:
There are four types of instruction: –
PUSH A, PUSH B, add α popc
Wherein addressing mode used are as follows: –
PUSH A – Direct
PUSH B – Register
Add – Register indirect
Pop.C – Immediate
PUSH A, PUSH B, add α popc
Wherein addressing mode used are as follows: –
PUSH A – Direct
PUSH B – Register
Add – Register indirect
Pop.C – Immediate
Question 94 |
Consider the following x86 - assembly language instructions :
MOV AL, 153
NEG AL
The contents of the destination register AL (in 8-bit binary notation), the status of Carry Flag(CF) and Sign Flag(SF) after the execution of above instructions, are
MOV AL, 153
NEG AL
The contents of the destination register AL (in 8-bit binary notation), the status of Carry Flag(CF) and Sign Flag(SF) after the execution of above instructions, are
AL = 0110 0110; CF = 0; SF =0 | |
AL = 0110 0111; CF = 0; SF =1 | |
AL = 0110 0110; CF = 1; SF =1 | |
AL = 0110 0111; CF = 1; SF =0 |
Question 94 Explanation:
153 = 1001 1001
NEG(1001 1001) = 1's complement of(1001 1001)= 0110 0110
MOV AL 153
AL= 1001 1001
NEG AL
AL = 0110 0101
MSB is 0. Hence SF=0
By default CF=0 and it will not change with above operations( MOV, NEG)
So, option 1 is the correct answer.
Note: Original UGC Key given correct answer is option-(4).
NEG(1001 1001) = 1's complement of(1001 1001)= 0110 0110
MOV AL 153
AL= 1001 1001
NEG AL
AL = 0110 0101
MSB is 0. Hence SF=0
By default CF=0 and it will not change with above operations( MOV, NEG)
So, option 1 is the correct answer.
Note: Original UGC Key given correct answer is option-(4).
Question 95 |
Consider the following statements :
(i) Auto increment addressing mode is useful in creating self-relocating code.
(ii) If auto addressing mode is included in an instruction set architecture, then an additional ALU is required for effective address calculation.
(iii) In auto increment addressing mode, the amount of increment depends on the size of the data item accessed.
Which of the above statements is/are true ?
(i) Auto increment addressing mode is useful in creating self-relocating code.
(ii) If auto addressing mode is included in an instruction set architecture, then an additional ALU is required for effective address calculation.
(iii) In auto increment addressing mode, the amount of increment depends on the size of the data item accessed.
Which of the above statements is/are true ?
(iii) only | |
(ii) and (iii) only | |
(i) and (ii) only | |
(ii) only |
Question 95 Explanation:
→ Auto increment addressing mode is useful in implementing arrays.
→ After determining the effective address, the value in the base register is incremented by the size of the data item that is to be accessed. For example, (A7)+ would access the content of the address register A7, then increase the address pointer of A7 by 1 (usually 1 word).
→ Within a loop, this addressing mode can be used to step through all the elements of an array or vector.
→ After determining the effective address, the value in the base register is incremented by the size of the data item that is to be accessed. For example, (A7)+ would access the content of the address register A7, then increase the address pointer of A7 by 1 (usually 1 word).
→ Within a loop, this addressing mode can be used to step through all the elements of an array or vector.
Question 96 |
A nonpipelined system taken 50ns to process a task. the same task can be processed in a six-segment pipeline with a clock cycle of 10ns. Determinant the speedup ration of the pipeline for 100 tasks. What is the maximum speedup that can be achieved?
4.90,5 | |
4.76,5 | |
3.90,5 | |
4.30,5 |
Question 96 Explanation:
Speed up ratio (S) :
It is defined as the speedup of a pipeline processing with respect to the equivalent non-pipeline processing.
S =nt n/(k+n−1)t p
Number of tasks n = 100
For Non-pipeline:
Time taken by non-pipeline to process a task t n = 50ns
Total time taken by non-pipeline to process 100 task = n t n
= 100 × 50
= 5000ns
For Pipeline:
Number of segment pipeline k = 6
Time period of 1 clock cycle t p = 10ns
Total time required to complete n tasks in k segment pipeline with tp clock cycle time:
= ( k + n − 1 )t p
= ( 6 + 100 − 1 )10
= 1050ns
Speed up Ratio:
When total time taken by the pipeline to process 100 tasks is divided by the total time required to complete n tasks in k segment pipeline with t p clock cycle time then speed up ratio is obtained.
S =5000/1050
= 4 .76
It is defined as the speedup of a pipeline processing with respect to the equivalent non-pipeline processing.
S =nt n/(k+n−1)t p
Number of tasks n = 100
For Non-pipeline:
Time taken by non-pipeline to process a task t n = 50ns
Total time taken by non-pipeline to process 100 task = n t n
= 100 × 50
= 5000ns
For Pipeline:
Number of segment pipeline k = 6
Time period of 1 clock cycle t p = 10ns
Total time required to complete n tasks in k segment pipeline with tp clock cycle time:
= ( k + n − 1 )t p
= ( 6 + 100 − 1 )10
= 1050ns
Speed up Ratio:
When total time taken by the pipeline to process 100 tasks is divided by the total time required to complete n tasks in k segment pipeline with t p clock cycle time then speed up ratio is obtained.
S =5000/1050
= 4 .76
Question 97 |
The principle of locality of reference justifies the use of:
Non reusable | |
Cache memory | |
Virtual memory | |
None of the above |
Question 97 Explanation:
● Locality of reference, also known as the principle of locality is the tendency of a processor to access the same set of memory locations repetitively over a short period of time.
● There are two basic types of reference locality – temporal and spatial locality.
● Temporal locality refers to the reuse of specific data, and/or resources, within a relatively small time duration.
● Spatial locality refers to the use of data elements within relatively close storage locations.
● Systems that exhibit strong locality of reference are great candidates for performance optimization through the use of techniques such as the caching, pre fetching for memory and advanced branch predictors at the pipe lining stage of a processor core.
● There are two basic types of reference locality – temporal and spatial locality.
● Temporal locality refers to the reuse of specific data, and/or resources, within a relatively small time duration.
● Spatial locality refers to the use of data elements within relatively close storage locations.
● Systems that exhibit strong locality of reference are great candidates for performance optimization through the use of techniques such as the caching, pre fetching for memory and advanced branch predictors at the pipe lining stage of a processor core.
Question 98 |
External Interrupt may not arise because of:
illegal or erroneous use of an instruction | |
a timing devices | |
external sources | |
I/O devices |
Question 98 Explanation:
● An external interrupt is a computer system interrupt that happens as a result of outside interference, whether that’s from the user, from peripherals, from other hardware devices or through a network.
● These are different than internal interrupts that happen automatically as the machine reads through program instructions
● These are different than internal interrupts that happen automatically as the machine reads through program instructions
Question 99 |
Where does the swap reside?
RAM | |
ROM | |
DISK | |
On-chip cache |
Question 99 Explanation:
●Swap space is an area on disk that temporarily holds a process memory image.
● When memory is full and process needs memory, inactive parts of process are put in swap space of disk.
● When memory is full and process needs memory, inactive parts of process are put in swap space of disk.
Question 100 |
The addressing mode used in an instruction of the form ADD X Y, is___
Direct | |
Absolute | |
Indirect | |
Indexed |
Question 100 Explanation:
● In direct addressing mode, the offset value is specified directly as part of the instruction, usually indicated by the variable name.
● Indirect addressing is generally used for variables containing several elements like, arrays. Starting address of the array is stored in, say, the EBX register.
● The address of the operand is obtained by adding to the contents of the general register (called index register) a constant value. The number of the index register and the constant value are included in the instruction code. Index Mode is used to access an array whose elements are in successive memory locations.
● An absolute address is represented by the contents of a register. This addressing mode is absolute in the sense that it is not specified relative to the current instruction address.
● Indirect addressing is generally used for variables containing several elements like, arrays. Starting address of the array is stored in, say, the EBX register.
● The address of the operand is obtained by adding to the contents of the general register (called index register) a constant value. The number of the index register and the constant value are included in the instruction code. Index Mode is used to access an array whose elements are in successive memory locations.
● An absolute address is represented by the contents of a register. This addressing mode is absolute in the sense that it is not specified relative to the current instruction address.
Question 101 |
Process that periodically checks status of an I/O devices, is known as:
Cold swapping | |
I/O instructions | |
Polling | |
Dealing |
Question 101 Explanation:
● Polling, or polled operation refers to actively sampling the status of an external device by a client program as a synchronous activity. Polling is most often used in terms of input/output (I/O), and is also referred to as polled I/O or software-driven I/O.
● A cold swap is term used to describe the process of installing, connecting, or disconnecting a hardware device that requires that the computer be turned off during the installation.
● A cold swap is term used to describe the process of installing, connecting, or disconnecting a hardware device that requires that the computer be turned off during the installation.
Question 102 |
CPU consists of __
ALU and Control Unit | |
ALU, Control Unit and Monitor | |
ALU, Control Unit and Hard disk | |
ALU, Control Unit and register |
Question 102 Explanation:
A central processing unit (CPU), also called a central processor or main processor, is the electronic circuitry within a computer that carries out the instructions of a computer program by performing the basic arithmetic, logic, controlling, and input/output (I/O) operations specified by the instructions.
Question 103 |
A hard disk system has the following parameters :
Number of tracks = 500
Number of sectors/track = 100
Number of bytes /sector = 500
Time taken by the head to move from one track to adjacent track = 1 ms
Rotation speed = 600 rpm.
What is the average time taken for transferring 250 bytes from the disk ?
300.5 ms | |
255.5 ms | |
255 ms | |
300 ms |
Question 103 Explanation:
Avg. time to transfer = Avg. seek time + Avg. rotational delay + Data transfer time
For Avg. seek time:
Given that, time to move between successive tracks is 1ms.
Time to move from track1 to track1 = 0ms
Time to move from track1 to track2 = 1ms
Time to move from track1 to track3 = 2ms
⋮ Time to move from track1 to track500 = 499ms
∴ Avg. seek time = 0+1+2+...+499/500 = 249.5ms
Avg. rotational delay:
600 rotations in 60sec.
One rotation takes 60/600 s = 100ms ∴ Avg. rotational delay = 100/2 = 50ms
Data transfer time:
In one rotation, we can read data on one complete track
= 100 × 500 = 50,000B data is read in one complete rotation
One complete rotation takes 100ms.
100ms → 50,000B
250B → 100/50000 × 250 = 0.5ms
∴ Avg. time to transfer = 249.5 × 50 + 0.5 = 300ms
For Avg. seek time:
Given that, time to move between successive tracks is 1ms.
Time to move from track1 to track1 = 0ms
Time to move from track1 to track2 = 1ms
Time to move from track1 to track3 = 2ms
⋮ Time to move from track1 to track500 = 499ms
∴ Avg. seek time = 0+1+2+...+499/500 = 249.5ms
Avg. rotational delay:
600 rotations in 60sec.
One rotation takes 60/600 s = 100ms ∴ Avg. rotational delay = 100/2 = 50ms
Data transfer time:
In one rotation, we can read data on one complete track
= 100 × 500 = 50,000B data is read in one complete rotation
One complete rotation takes 100ms.
100ms → 50,000B
250B → 100/50000 × 250 = 0.5ms
∴ Avg. time to transfer = 249.5 × 50 + 0.5 = 300ms
Question 104 |
How many characters per sec (7 bits + 1 parity) can be transmitted over a 2400 bps line if the transfer is synchronous ( 1 start and 1 stop bit)?
300 | |
240 | |
250 | |
275 |
Question 104 Explanation:
Given bandwidth is 2400 bps
Each character consists of (7+1)bits = 8 bits
Synchronous transmission is a data transfer method which is characterized by a continuous stream of data in the form of signals which are accompanied by regular timing signals which are generated by some external clocking mechanism meant to ensure that both the sender and receiver are synchronized with each other.
Once sender and receiver synchronized means no need to use start and stop bits every time
Total number of characters can be transmitted per second is =bandwidth/ number of bits in each character=2400/8 = 300
Each character consists of (7+1)bits = 8 bits
Synchronous transmission is a data transfer method which is characterized by a continuous stream of data in the form of signals which are accompanied by regular timing signals which are generated by some external clocking mechanism meant to ensure that both the sender and receiver are synchronized with each other.
Once sender and receiver synchronized means no need to use start and stop bits every time
Total number of characters can be transmitted per second is =bandwidth/ number of bits in each character=2400/8 = 300
Question 105 |
In X = (M + N x O)/(P x Q), how many one-address instructions are required to evaluate it?
4 | |
6 | |
8 | |
10 |
Question 105 Explanation:
All operations are performed with an implied accumulator register. The instruction format in this type of computer uses one address field. For example, the instruction that specifies an arithmetic addition is defined by an assembly language instruction as ADD.
Given instruction is
Instruction-1: Load the value “M” into accumulator
Instruction-2:Add the “N” value to M and store result into accumulator register
Instruction-3:Multiply “O” with the accumulator register value and store in to accumulator register
instruction-4: Store that result into Memory
Instruction-5:Load/store the value “P” into accumulator register
instruction-6:Multiply “Q” with the accumulator register value and store in to accumulator
instruction-7:Divide the memory value with the accumulator register value and store in to accumulator
Instruction-8: Store the accumulator value in the memory location.
Given instruction is
Instruction-1: Load the value “M” into accumulator
Instruction-2:Add the “N” value to M and store result into accumulator register
Instruction-3:Multiply “O” with the accumulator register value and store in to accumulator register
instruction-4: Store that result into Memory
Instruction-5:Load/store the value “P” into accumulator register
instruction-6:Multiply “Q” with the accumulator register value and store in to accumulator
instruction-7:Divide the memory value with the accumulator register value and store in to accumulator
Instruction-8: Store the accumulator value in the memory location.
Question 106 |
The minimum time delay between the initiation of two independent memory operations is called
Access time | |
Cycle time | |
Rotational time | |
Latency time |
Question 106 Explanation:
→ This is the minimum time delay between the initiation two independent memory operations (for example, two successive memory read operation).
→ Memory cycle time is slightly larger than memory access time.
→ Memory cycle time is slightly larger than memory access time.
Question 107 |
The contents of the flag register after execution of the following program by 8085 microprocessor will be
Program
SUB A
MVI B,(01)H
DCR B
HLT
Program
SUB A
MVI B,(01)H
DCR B
HLT
(54)H | |
(00)H | |
(01)H
| |
(45)H |
Question 107 Explanation:
Question 108 |
In a Big-Endian machine, a 32 bit word is stored at address 0 in a memory that is byte addressable. What byte of the word will be stored at address 0?
Byte 3
| |
Byte 2
| |
Byte 1
| |
Byte 0
|
Question 108 Explanation:
→ A load word or store word instruction uses only one memory address. The lowest address of the four bytes is used for the address of a block of four contiguous bytes.
→ How is a 32-bit pattern held in the four bytes of memory?
There are 32 bits in the four bytes and 32 bits in the pattern, but a choice has to be made about which byte of memory gets what part of the pattern. There are two ways that computers commonly do this:
Big Endian Byte Order: The most significant byte (the "big end") of the data is placed at the byte with the lowest address. The rest of the data is placed in order in the next three bytes in memory.
Little Endian Byte Order: The least significant byte (the "little end") of the data is placed at the byte with the lowest address. The rest of the data is placed in order in the next three bytes in memory.
→ In these definitions, the data, a 32-bit pattern, is regarded as a 32-bit unsigned integer.
→ The "most significant" byte is the one for the largest powers of two: 231, ..., 224. The "least significant" byte is the one for the smallest powers of two: 27, ..., 20.
→ For example, say that the 32-bit pattern 0x12345678 is stored at address 0x00400000. The most significant byte is 0x12; the least significant is 0x78.
Within a byte the order of the bits is the same for all computers (no matter how the bytes themselves are arranged).
→ How is a 32-bit pattern held in the four bytes of memory?
There are 32 bits in the four bytes and 32 bits in the pattern, but a choice has to be made about which byte of memory gets what part of the pattern. There are two ways that computers commonly do this:
Big Endian Byte Order: The most significant byte (the "big end") of the data is placed at the byte with the lowest address. The rest of the data is placed in order in the next three bytes in memory.
Little Endian Byte Order: The least significant byte (the "little end") of the data is placed at the byte with the lowest address. The rest of the data is placed in order in the next three bytes in memory.
→ In these definitions, the data, a 32-bit pattern, is regarded as a 32-bit unsigned integer.
→ The "most significant" byte is the one for the largest powers of two: 231, ..., 224. The "least significant" byte is the one for the smallest powers of two: 27, ..., 20.
→ For example, say that the 32-bit pattern 0x12345678 is stored at address 0x00400000. The most significant byte is 0x12; the least significant is 0x78.
Within a byte the order of the bits is the same for all computers (no matter how the bytes themselves are arranged).
Question 109 |
Considering every instruction and address as one word long, how many memory access are required for the following instruction, where R1, R2 and R3 are registers, and (R3) represents that R3 contains a memory address where some value (operand) is stored?
ADD R1, R2, (R3)
4 | |
1 | |
3 | |
2 |
Question 109 Explanation:
We need one memory access to load the actual instruction from memory. Then R2 contains an operand value, so it doesn't require a memory access. Whereas R3 has a value which is the address of the operand, so taking that address we need to make one memory access to load the actual operand. So, this will be second memory access. The result of the addition is stored into R1. This doesn't require a memory access. So, in total there are 2 memory accesses.
Question 110 |
Which of the following is not a form of main memory?
Instruction cache | |
Instruction register | |
Instruction Opcode | |
Translation lookaside buffer |
Question 110 Explanation:
In computing, an opcode (abbreviated from operation code, also known as instruction syllable, instruction parcel or opstring) is the portion of a machine language instruction that specifies the
operation to be performed. Beside the opcode itself, most instructions also specify the data they will process, in the form of operands. In addition to opcodes used in the instruction set
architectures of various CPUs, which are hardware devices, they can also be used in abstract computing machines as part of their byte code specifications.
Note: Instruction opcode not in a form of main memory.
Note: Instruction opcode not in a form of main memory.
Question 111 |
A pipeline is having speed up factor as 10 and operating with efficiency of 80%. what will be the number of stages in the pipeline?
10 | |
8 | |
13 | |
None |
Question 111 Explanation:
Efficiency of a pipeline(E k ) = Speed Up / No of stages
No of Stages =Speed Up / E k = 10/0.8 =12.5(approximately 13)
No of Stages =Speed Up / E k = 10/0.8 =12.5(approximately 13)
Question 112 |
Which level of RAID refers to disk mirroring with block striping?
RAID level 1 | |
RAID level 2 | |
RAID level 0 | |
RAID level 3 |
Question 112 Explanation:
● The standard RAID levels comprise a basic set of RAID (redundant array of independent disks) configurations that employ the techniques of striping, mirroring, or parity to create
large reliable data stores from multiple general-purpose computer hard disk drives (HDDs).
●RAID 0: Stripping
● RAID 1: Mirroring
● RAID 2: Hamming code for error detection
● RAID 3: Byte-level striping with a dedicated parity disk
● RAID 4: Block-level striping with block-level striping with two parity blocks parity
● RAID 5: Block-level striping with distributed parity
● RAID 6: Block-level striping with double distributed parity.
●RAID 0: Stripping
● RAID 1: Mirroring
● RAID 2: Hamming code for error detection
● RAID 3: Byte-level striping with a dedicated parity disk
● RAID 4: Block-level striping with block-level striping with two parity blocks parity
● RAID 5: Block-level striping with distributed parity
● RAID 6: Block-level striping with double distributed parity.
Question 113 |
In a 10 bit computer instruction format, the size of address field is 3 bits. Thecomputer uses expanding OPcode technique and has 4 two address instructions and 16
one address instructions. The number of zero address instructions it can support is
256 | |
356 | |
640 | |
56 |
Question 113 Explanation:
No. of possible instruction encoding =2 10 =1024
No. of encoding taken by two-address instructions =4×2 3 ×2 3 =256
No. of encoding taken by one-address instructions =16×2 3 =128
So, no. of possible zero-address instructions =1024−(256+128)=640
No. of encoding taken by two-address instructions =4×2 3 ×2 3 =256
No. of encoding taken by one-address instructions =16×2 3 =128
So, no. of possible zero-address instructions =1024−(256+128)=640
Question 114 |
Match list I with list II and select the correct answer using the codes given below the lists.
1 2 3 4 | |
3 2 4 1 | |
2 3 1 4 | |
1 4 2 3 |
Question 114 Explanation:
● A stack-organized computer does not use an address field for the instructions ADD and MUL. The PUSH and POP instructions, however, need an address field to specify the operand that communicates with the stack.
● One-address instructions use an implied accumulator (AC) register for all data manipulation.
● Two address instructions are the most common in commercial computers. Here each address field can specify either a processor register or a memory word.
● Computers with three-address instruction formats can use each address field to specify either a processor register or a memory operand.
● One-address instructions use an implied accumulator (AC) register for all data manipulation.
● Two address instructions are the most common in commercial computers. Here each address field can specify either a processor register or a memory word.
● Computers with three-address instruction formats can use each address field to specify either a processor register or a memory operand.
Question 115 |
In a cache memory if total number of sets are 's', then the set offset is:
28 | |
log2s | |
s2 | |
s |
Question 115 Explanation:
If S is the number of sets in our cache, then the set index has s=log2 S bits.
→ Note that in a fully-associative cache, there is only 1 set so the set index will not exist. The remaining bits are used for the tag.
→ If ℓ is the length of the address (in bits), then the number of tag bits is t = ℓ − b − s.
→ Note that in a fully-associative cache, there is only 1 set so the set index will not exist. The remaining bits are used for the tag.
→ If ℓ is the length of the address (in bits), then the number of tag bits is t = ℓ − b − s.
Question 116 |
A stack organized computer has which of the following instructions?
Zero address | |
one address | |
two address | |
three address |
Question 116 Explanation:
Zero-Address Instructions:
A stack-organized computer does not use an address field for the instructions ADD and MUL. The PUSH and POP instructions, however, need an address field to specify the operand that communicates with the stack. The following program shows how X=(A+B)*(C+D) will be written for a stack-organized computer. (TOS stands for top of stack).
To evaluate arithmetic expressions in a stack computer, it is necessary to convert the expression into reverse Polish notation. The name “zero-address” is given to this type of computer because of the absence of an address field in the computational instructions.
A stack-organized computer does not use an address field for the instructions ADD and MUL. The PUSH and POP instructions, however, need an address field to specify the operand that communicates with the stack. The following program shows how X=(A+B)*(C+D) will be written for a stack-organized computer. (TOS stands for top of stack).
To evaluate arithmetic expressions in a stack computer, it is necessary to convert the expression into reverse Polish notation. The name “zero-address” is given to this type of computer because of the absence of an address field in the computational instructions.
Question 117 |
Consider a non pipelined machine with 6 stages. the length of each stage are 20ns, 10ns, 30ns, 25ns, 40ns, and 15ns respectively. Suppose for implementing the pipelining the machine adds 5ns of overhead to each stage for clock skew and set up. What is the speed up factor of the pipelining system (ignoring any hazard impact) ?
7 | |
14
| |
3.11 | |
6.22 |
Question 117 Explanation:
Given data,
Non pipelined machine with 6 stages,
Length of each stage=20,10,30,25,40,15 ns.
Implementing the pipelining the machine adds each stage=5ns overhead.
Speed up factor of the pipelining system=?
Step-1: Non pipeline for 1 instruction to all stages=20+10+30+25+40+15 ns
=140 ns
Step-2: Per cycle adds 5ns overhead to each stage =25,15,35,30,45,20 ns
= 45 ns
Step-3: Speedup factor= Time non pipelining / Time with pipeline
= 140/45
= 3.11 ns
Non pipelined machine with 6 stages,
Length of each stage=20,10,30,25,40,15 ns.
Implementing the pipelining the machine adds each stage=5ns overhead.
Speed up factor of the pipelining system=?
Step-1: Non pipeline for 1 instruction to all stages=20+10+30+25+40+15 ns
=140 ns
Step-2: Per cycle adds 5ns overhead to each stage =25,15,35,30,45,20 ns
= 45 ns
Step-3: Speedup factor= Time non pipelining / Time with pipeline
= 140/45
= 3.11 ns
Question 118 |
Which of the following is/are not features of RISC processor?
i.Large number of addressing modes
ii.Uniform instruction set
i.Large number of addressing modes
ii.Uniform instruction set
i only | |
ii only | |
Both i and ii | |
None of the options |
Question 118 Explanation:
The standard features of RISC processors are listed below:
1. RISC processors use a small and limited number of instructions.
RISC processors only support a small number of primitive and essential instructions. This puts emphasis on software and compiler design due to the relatively simple instruction set.
2. RISC machines mostly uses hardwired control unit.
Most of the RISC processors are based on the hardwired control unit design approach. In hardwired control unit, the control units use fixed logic circuits to interpret instructions and generate control signals from them. It is significantly faster than its counterpart but are rather inflexible.
3. RISC processors consume less power and have high performance.
RISC processors have been known to be heavily pipelined this ensures that the hardware resources of the processor are utilized to a maximum giving higher throughput and also consuming less power.
4. Each instruction is very simple and consistent.
Most instructions in a RISC instruction set are very simple that get executed in one clock cycle. 5. RISC processors use simple addressing modes.
RISC processors don’t have as many addressing modes and the addressing modes these processors have are rather very simple. Most of the addressing modes are for register operations and do not refer memory.
6. RISC instruction is of uniform fixed length.
The decision of RISC processor designers to provide simple addressing modes leads to uniform length instructions. For example, instruction length increases if an operand is in memory as opposed to in a register. a. This is because we have to specify the memory address as part of instruction encoding, which takes many more bits. This complicates instruction decoding and scheduling.
7. Large Number of Registers.
The RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory
1. RISC processors use a small and limited number of instructions.
RISC processors only support a small number of primitive and essential instructions. This puts emphasis on software and compiler design due to the relatively simple instruction set.
2. RISC machines mostly uses hardwired control unit.
Most of the RISC processors are based on the hardwired control unit design approach. In hardwired control unit, the control units use fixed logic circuits to interpret instructions and generate control signals from them. It is significantly faster than its counterpart but are rather inflexible.
3. RISC processors consume less power and have high performance.
RISC processors have been known to be heavily pipelined this ensures that the hardware resources of the processor are utilized to a maximum giving higher throughput and also consuming less power.
4. Each instruction is very simple and consistent.
Most instructions in a RISC instruction set are very simple that get executed in one clock cycle. 5. RISC processors use simple addressing modes.
RISC processors don’t have as many addressing modes and the addressing modes these processors have are rather very simple. Most of the addressing modes are for register operations and do not refer memory.
6. RISC instruction is of uniform fixed length.
The decision of RISC processor designers to provide simple addressing modes leads to uniform length instructions. For example, instruction length increases if an operand is in memory as opposed to in a register. a. This is because we have to specify the memory address as part of instruction encoding, which takes many more bits. This complicates instruction decoding and scheduling.
7. Large Number of Registers.
The RISC design philosophy generally incorporates a larger number of registers to prevent in large amounts of interactions with memory
Question 119 |
INCA(Increase register A by 1) is an example of which of the following addressing mode?
Immediate addressing | |
Indirect addressing | |
Implied addressing | |
Relative addressing |
Question 119 Explanation:
→ Implied addressing refers to instructions that comprise only an opcode without an operand; for example, the INCA (“increment accumulator”) instruction.
→ An implied sequence commences when the PC reaches the opcode for an implied instruction
(a). loads that opcode into the IR
(b). Increments the PC (c). Recognizing that this is an implied instruction, the CPU executes it and continues on to the next instruction.
→ Instructions that use implied addressing are: CLRIM, DECA, DECX, HALT, INCA, INCX, NOP, POPA, POPSR, PUSHA, PUSHSR, ROLC, RORC, RTI, RTS, SETIM, SHL, and SHR.
→ An implied sequence commences when the PC reaches the opcode for an implied instruction
(a). loads that opcode into the IR
(b). Increments the PC (c). Recognizing that this is an implied instruction, the CPU executes it and continues on to the next instruction.
→ Instructions that use implied addressing are: CLRIM, DECA, DECX, HALT, INCA, INCX, NOP, POPA, POPSR, PUSHA, PUSHSR, ROLC, RORC, RTI, RTS, SETIM, SHL, and SHR.
Question 120 |
Which of the following statement(S) is/are true in the context of interpreters?
S1: Interpreters process program according to the logical flow of control through the program
S2: Interpreter translates and executes the error free instruction before it goes to the second
S3: Interpreter processing time is less compared with compiler
S4. LISP and Prolog are interpreted languages
Only S1 | |
Only S3 | |
Only S1,S2 and S3 | |
Only S1, S2 and S4 |
Question 120 Explanation:
S1: TRUE: Interpreters process program according to the logical flow of control through the program
S2: FALSE: Interpreter translates and executes the instruction before it goes to the second line but not doing error free operations.
S3: FALSE: Compiler more faster than interpreter
S4: FALSE:LISP and Prolog are interpreted rather than compiler based
S2: FALSE: Interpreter translates and executes the instruction before it goes to the second line but not doing error free operations.
S3: FALSE: Compiler more faster than interpreter
S4: FALSE:LISP and Prolog are interpreted rather than compiler based
Question 121 |
Which of the following is false?
Interrupts which are initially by an instruction are software interrupts | |
When a subordinate is called, the address of the instruction following the CALL instruction is stored in the stack pointer | |
A micro program which is written as 0's and 1's is a binary micro program | |
None of the options |
Question 121 Explanation:
→ An interrupt is a signal to the processor emitted by hardware or software indicating an event that needs immediate attention
→ Hardware interrupts are used by devices to communicate that they require attention from the operating system.
→ A software interrupt is caused either by an exceptional condition in the processor itself, or a special instruction in the instruction set which causes an interrupt when it is executed.
→ Hardware interrupts are used by devices to communicate that they require attention from the operating system.
→ A software interrupt is caused either by an exceptional condition in the processor itself, or a special instruction in the instruction set which causes an interrupt when it is executed.
Question 122 |
We have 10 stage pipeline, where the branch target conditions are resolved at stage 5. How many stalls are there for an incorrect predicted branch?
5 | |
6 | |
7 | |
4 |
Question 122 Explanation:
→ A branch predictor is a digital circuit that tries to guess which way a branch (e.g. an if–then–else structure) will go before this is known definitively.
→ The purpose of the branch predictor is to improve the flow in the instruction pipeline.
→ The technique involves only executing certain instructions if certain predicates are true.
→ Branch prediction is typically implemented in hardware using a branch predictor.
→ Branch target conditions resolved at stage 5 means upto 4 stages there are incorrect branch target conditions are there.
→ So Branch condition is resolved at nth stage means, the number of stalls are (n-1)
→ The purpose of the branch predictor is to improve the flow in the instruction pipeline.
→ The technique involves only executing certain instructions if certain predicates are true.
→ Branch prediction is typically implemented in hardware using a branch predictor.
→ Branch target conditions resolved at stage 5 means upto 4 stages there are incorrect branch target conditions are there.
→ So Branch condition is resolved at nth stage means, the number of stalls are (n-1)
Question 123 |
A RAM chip has 7 address lines, 8 data lines and 2 chips select lines. Then the number of memory locations is___
212 | |
210 | |
219 | |
213 |
Question 123 Explanation:
Given data,
address line=7
Data lines=8
Chip selected lines=2
Step-1: Total address lines are 27 and chips select lines
Step-2: The chips select lines are 22
Step-3: Total address and chip selected lines are 27 * 22 = 29
Step-4: Number of memory locations for 8 data lines =29 * 23
= 212
address line=7
Data lines=8
Chip selected lines=2
Step-1: Total address lines are 27 and chips select lines
Step-2: The chips select lines are 22
Step-3: Total address and chip selected lines are 27 * 22 = 29
Step-4: Number of memory locations for 8 data lines =29 * 23
= 212
Question 124 |
A two word instruction is stored in a location A. The operand part of instruction holds B. if the addressing mode is relative, the operand is available in location
A+B+2 | |
A+B+1 | |
B+1 | |
A+B |
Question 124 Explanation:
It is given that instruction size is 2 words, and it’s starting address is A.
When executing the present instruction program counter gets incremented to the address of the next instruction.
So, latest value in PC=A+2.
In the instruction operand value is B, which is used as a offset for the effective address calculation.
So, Effective address= Program counter + Offset.
Here Program counter= A+2, Offset = B
Effective address= A+2+B
When executing the present instruction program counter gets incremented to the address of the next instruction.
So, latest value in PC=A+2.
In the instruction operand value is B, which is used as a offset for the effective address calculation.
So, Effective address= Program counter + Offset.
Here Program counter= A+2, Offset = B
Effective address= A+2+B
Question 125 |
In a particular system it is observed that, The cache performance gets improved as a result of increasing the block size of he cache. The primary reason behind this is:
Programs exhibits temporal locality | |
Programs have small working set | |
Read operation is frequently required rather than write operation | |
Programs exhibits spatial locality |
Question 125 Explanation:
Helps improve miss rate b/c of principle of locality:
1)Temporal locality says that if something is accessed once, “it will probably be accessed again soon"
2)Spatial locality says that if something is accessed, something nearby it will probably be accessed
Note: Larger block sizes help with spatial locality. Easiest way to reduce miss rate is to increase cache block size
1)Temporal locality says that if something is accessed once, “it will probably be accessed again soon"
2)Spatial locality says that if something is accessed, something nearby it will probably be accessed
Note: Larger block sizes help with spatial locality. Easiest way to reduce miss rate is to increase cache block size
Question 126 |
Action implementing instructor’s meaning are actually carried out by____
Instruction fetch
| |
Instruction decode | |
Instruction execution | |
Instruction program |
Question 126 Explanation:
→ The basic function performed by a computer is the execution of a program. The program which is to be executed is a set of instructions which are stored in memory.
→ The central processing unit (CPU) executes the instructions of the program to complete a task.
→ The major responsibility of the instruction execution is with the CPU. The instruction execution takes place in the CPU registers
→ The central processing unit (CPU) executes the instructions of the program to complete a task.
→ The major responsibility of the instruction execution is with the CPU. The instruction execution takes place in the CPU registers
Question 127 |
The operation executed on data stored in registers is called____
Macro operation | |
Micro operation | |
Bit operation | |
Byte operation |
Question 127 Explanation:
Micro-operations perform basic operations on data stored in one or more registers, including transferring data between registers or between registers and external buses of the central processing unit (CPU), and performing arithmetic or logical operations on registers
Question 128 |
Hardware mechanism that enables a device to notify the CPU is called:
Busy-waiting | |
Interrupt | |
Polling | |
DMA |
Question 128 Explanation:
→ An interrupt is a signal to the processor emitted by hardware or software indicating an event that needs immediate attention.
→ An interrupt alerts the processor to a high-priority condition requiring the interruption of the current code the processor is executing.
→ An interrupt alerts the processor to a high-priority condition requiring the interruption of the current code the processor is executing.
Question 129 |
How many characters per second (7 bits+1 parity) can be transmitted over a 2400 bps line if the transfer is asynchronous(1 start and 1 stop bit)?
240 | |
250 | |
275 | |
300 |
Question 129 Explanation:
→ Synchronous data transmission is a data transfer method in which a continuous stream of data signals is accompanied by timing signals (generated by an electronic clock) to ensure that the transmitter and the receiver are in step (synchronized) with one another
→ Asynchronous transmission works in spurts and must insert a start bit before each data character and a stop bit at its termination to inform the receiver where it begins and ends.
→ In synchronous mode of transfer we don’t require start and stop bits but in Asynchronous mode of transfer these bits are added to the number of bits in each character.
→ Number of characters per second = (7+1)bits + 1 start + 1 stop = 10 bits
→ Bandwidth = 2400 bps
→ Number of characters to be transmitted = 2400/10 = 240
→ Asynchronous transmission works in spurts and must insert a start bit before each data character and a stop bit at its termination to inform the receiver where it begins and ends.
→ In synchronous mode of transfer we don’t require start and stop bits but in Asynchronous mode of transfer these bits are added to the number of bits in each character.
→ Number of characters per second = (7+1)bits + 1 start + 1 stop = 10 bits
→ Bandwidth = 2400 bps
→ Number of characters to be transmitted = 2400/10 = 240
Question 130 |
Von neumann computer architecture is____
SISD | |
SIMD | |
MIMD | |
MISD |
Question 130 Explanation:
SISD (single instruction stream, single data stream) is a computer architecture in which a single uni-core processor, executes a single instruction stream, to operate on data stored in a single memory. This corresponds to the von Neumann architecture.
Question 131 |
The Communication between the components in a microcomputer takes place via the address and ____
I/O bus | |
Data bus | |
Address bus | |
Control lines |
Question 131 Explanation:
→ A data bus is a system within a computer or device, consisting of a connector or set of wires, that provides transportation for data.
→ A data bus is also called a processor bus, front side bus, frontside bus or backside bus—is a group of electrical wires used to send information (data) between two or more components.
→ A data bus is also called a processor bus, front side bus, frontside bus or backside bus—is a group of electrical wires used to send information (data) between two or more components.
Question 132 |
An interface that provides I/o transfer of data directly to and from the memory unit and the peripheral is termed as_____
DDA | |
Serial Interface | |
BR | |
DMA |
Question 132 Explanation:
Direct memory access (DMA) is a method that allows an input/output (I/O) device to send or receive data directly to or from the main memory, bypassing the CPU to speed up memory operations
Question 133 |
Match list I with list II and select the correct answer using the codes given below the lists.
1 2 3 4 | |
3 2 4 1 | |
2 3 1 4 | |
1 4 2 3 |
Question 133 Explanation:
3 address instruction:
Two operand locations and a result location are explicitly contained in the instruction word.
e.g., Y = A − B
2 address instruction:
One of the addresses is used to specify both an operand and the result location.
e.g., Y = Y + X
1 address instruction:
Two addresses are implied in the instruction and accumulator based operations.
e.g., A CC = A CC + X
0 address instructions:
They are applicable to a special memory organization called a stack. It interact with a stack using push and pop operations. All addresses are implied as in register based operations.
T = Tap(T − 1 )
Two operand locations and a result location are explicitly contained in the instruction word.
e.g., Y = A − B
2 address instruction:
One of the addresses is used to specify both an operand and the result location.
e.g., Y = Y + X
1 address instruction:
Two addresses are implied in the instruction and accumulator based operations.
e.g., A CC = A CC + X
0 address instructions:
They are applicable to a special memory organization called a stack. It interact with a stack using push and pop operations. All addresses are implied as in register based operations.
T = Tap(T − 1 )
Question 134 |
A microprogrammed control unit
Is faster than a hardwired unit | |
Facilitates easy implementation of a new instruction | |
Is useful when small programs are to be run | |
All of the above |
Question 134 Explanation:
→ In hardwired control, we saw how all the control signals required inside the CPU can be generated using a state counter and a PLA circuit.
→ There is an alternative approach by which the control signals required inside the CPU can be generated . This alternative approach is known as microprogrammed control unit.
→ In microprogrammed control unit, the logic of the control unit is specified by a microprogram. A microprogram consists of a sequence of instructions in a microprogramming language. These are instructions that specify microoperations.
→ A microprogrammed control unit is a relatively simple logic circuit that is capable of
(1) sequencing through microinstructions.
(2) generating control signals to execute each microinstruction.
→ The concept of microprogram is similar to computer program. In computer program the complete instructions of the program is stored in main memory and during execution it fetches the instructions from main memory one after another.
→ The sequence of instruction fetch is controlled by program counter (PC)
→ There is an alternative approach by which the control signals required inside the CPU can be generated . This alternative approach is known as microprogrammed control unit.
→ In microprogrammed control unit, the logic of the control unit is specified by a microprogram. A microprogram consists of a sequence of instructions in a microprogramming language. These are instructions that specify microoperations.
→ A microprogrammed control unit is a relatively simple logic circuit that is capable of
(1) sequencing through microinstructions.
(2) generating control signals to execute each microinstruction.
→ The concept of microprogram is similar to computer program. In computer program the complete instructions of the program is stored in main memory and during execution it fetches the instructions from main memory one after another.
→ The sequence of instruction fetch is controlled by program counter (PC)
Question 135 |
Which level of RAID refers to disk mirroring with block striping?
RAID level 1 | |
RAID level 2 | |
RAID level 0 | |
RAID level 3 |
Question 135 Explanation:
RAID is a technology that is used to increase the performance and/or reliability of data storage.
Following are the various RAID levels:
RAID 0: Stripping
RAID 1: Mirroring
RAID 2: Hamming code for error detection
RAID 3: Byte-level striping with a dedicated parity disk
RAID 4: Block-level striping with block-level striping with two parity blocks parity
RAID 5: Block-level striping with distributed parity
RAID 6: Block-level striping with double distributed parity.
Following are the various RAID levels:
RAID 0: Stripping
RAID 1: Mirroring
RAID 2: Hamming code for error detection
RAID 3: Byte-level striping with a dedicated parity disk
RAID 4: Block-level striping with block-level striping with two parity blocks parity
RAID 5: Block-level striping with distributed parity
RAID 6: Block-level striping with double distributed parity.
Question 136 |
Which of the following is not a form of main memory?
Instruction cache | |
Instruction register | |
Instruction Opcode | |
Translation lookaside buffer |
Question 136 Explanation:
→ The instruction opcode is the portion of a machine language instruction that specifies the operation to be performed. Beside the opcode itself, most instructions also specify the data they will process, in the form of operands. In addition to opcodes used in the instruction set architectures of various CPUs, which are hardware devices, they can also be used in abstract computing machines as part of their byte code specifications.
Question 137 |
____refers to these attributes of a system visible to a programmer or, put another way, those attributes that have a direct impact on the logical execution of a program
Computer organization | |
Computer architecture | |
Microprocessor | |
Bus |
Question 137 Explanation:
→ Computer architecture is a set of rules and methods that describe the functionality, organization, and implementation of computer systems.
→ Computer architecture involves instruction set architecture design, microarchitecture design, logic design, and implementation.
→ Organization of computer system is the way of practical implementation which results in realization of architectural specifications of a computer system.
→ A microprocessor is a computer processor that incorporates the functions of a central processing unit on a single integrated circuit (IC),or at most a few integrated circuits.
→ A bus is a communication system that transfers data between components inside a computer, or between computers.
→ Computer architecture involves instruction set architecture design, microarchitecture design, logic design, and implementation.
→ Organization of computer system is the way of practical implementation which results in realization of architectural specifications of a computer system.
→ A microprocessor is a computer processor that incorporates the functions of a central processing unit on a single integrated circuit (IC),or at most a few integrated circuits.
→ A bus is a communication system that transfers data between components inside a computer, or between computers.
Question 138 |
_____ is the first Intel x86 microprocessor with a dual core, referring to the implementation of two processors on a single chip
Core | |
Core 2 duo | |
Dual core | |
Centrino |
Question 138 Explanation:
Core: This is the first Intel x86 microprocessor with a dual core, referring to the implementation of two processors on a single chip.
Core 2: The Core 2 extends the architecture to 64 bits. The Core 2 Quad provides four processors on a single chip. More recent Core offerings have up to 10 processors per chip.
Dual-core refers to a CPU that includes two complete execution cores per physical processor. It has combined two processors and their caches and cache controllers onto a single integrated circuit (silicon chip).
Core 2: The Core 2 extends the architecture to 64 bits. The Core 2 Quad provides four processors on a single chip. More recent Core offerings have up to 10 processors per chip.
Dual-core refers to a CPU that includes two complete execution cores per physical processor. It has combined two processors and their caches and cache controllers onto a single integrated circuit (silicon chip).
Question 139 |
_____chips are high speed processor that are known for their small die size and low power requirements. They are widely used in PDAs and other handheld devices, including games and phones as well as a large variety of consumer products. It is probably the most widely used embedded processor architecture and indeed the most widely used processor architecture of any kind in the world.
HAND | |
LEG | |
ARM | |
SUN |
Question 139 Explanation:
→ An ARM processor is one of a family of CPU’s based on the RISC (reduced instruction set computer) architecture developed by Advanced RISC Machines(ARM). ARM makes 32-bit and 64-bit RISC multi-core processors.
→ ARM processors are extensively used in consumer electronic devices such as Smartphones,tablets, multimedia players and other mobile devices, such as wearable. Because of their reduced instruction sets, they require fewer transistor, which enables a smaller die size for the integrated circuitry (IC).
→ ARM processors are extensively used in consumer electronic devices such as Smartphones,tablets, multimedia players and other mobile devices, such as wearable. Because of their reduced instruction sets, they require fewer transistor, which enables a smaller die size for the integrated circuitry (IC).
Question 140 |
_____ memory is intended to give memory speed approaching that of the fastest memories available, and at the same time provide a large memory size at the price of less expensive types of semiconductor memories
Register | |
Counter | |
Flip flop | |
cache |
Question 140 Explanation:
→ Cache memory, also called CPU memory, is high-speed static random access memory (SRAM) that a computer microprocessor can access more quickly than it can access regular random access memory (RAM).
→ Register memory is the smallest and fastest memory in a computer.
→ Register memory size very small compared to Cache memory.
→ Register memory is the smallest and fastest memory in a computer.
→ Register memory size very small compared to Cache memory.
Question 141 |
____ are used to access data on secondary, sequential access stores, such as disks and tapes.
Sequences | |
Arrays | |
Records | |
Registers |
Question 141 Explanation:
● Registers is not secondary storage devices. So it is not correct
● Array occupies primary memory(RAM). So it also not correct.
● Records used to access data on secondary devices record by record sequentially.
● Array occupies primary memory(RAM). So it also not correct.
● Records used to access data on secondary devices record by record sequentially.
Question 142 |
The positioning time or random access time, consists of two parts: The time necessary to move the disk arm to the desired cylinder, called
Seek time | |
Rotational latency | |
Flash drives | |
Transfer rate |
Question 142 Explanation:
Seek Time : The amount of time required to move the read/write head from its current position to desired track.
Rotational latency : The amount of time to rotate the track when the read/write head comes to desired sector position. In simple disk, rotational latency is the time to rotate 1⁄2 disk to the access.
Rotational latency : The amount of time to rotate the track when the read/write head comes to desired sector position. In simple disk, rotational latency is the time to rotate 1⁄2 disk to the access.
Question 143 |
The term ___ is used for the larger, more powerful computers other than supercomputers. It supports a large database, has elaborate I/O hardware, and is used in a central data processing facility
Minicomputer | |
Supercomputer | |
Mainframe | |
microcomputer |
Question 143 Explanation:
→ Mainframe computers or mainframes are computers used primarily by large organizations for critical applications; bulk data processing, such as census, industry and consumer statistics,
enterprise resource planning; and transaction processing.
→ They are larger and have more processing power than some other classes of computers:
minicomputers, servers, workstations, and personal computers.
→ They are larger and have more processing power than some other classes of computers:
minicomputers, servers, workstations, and personal computers.
Question 144 |
This was the first general purpose microprocessor. It was designed to be the CPU of a general purpose micro computer. It was faster, had a richer instruction set and a larger addressing capability. Which microprocessor are we discussing?
4004 | |
8008 | |
8080 | |
All of the these |
Question 144 Explanation:
4004 and 8008 designed for specific purpose but 8080 microprocessor is first general purpose micro computer.
Question 145 |
The____ is popular high bandwidth, processor independent bus that can function as a mezzanine or peripheral bus
Peripheral component interconnect(PCI) | |
Peripheral component disconnect(PCD) | |
Input output connect | |
Array connect |
Question 145 Explanation:
● The peripheral component interconnect (PCI) is a popular high-bandwidth, processor-independent bus that can function as a mezzanine or peripheral bus.
● Compared with other common bus specifications, PCI delivers better system performance for high-speed I/O subsystems (e.g. graphic display adapters, network interface controllers, disk controllers, and so on).
● Compared with other common bus specifications, PCI delivers better system performance for high-speed I/O subsystems (e.g. graphic display adapters, network interface controllers, disk controllers, and so on).
Question 146 |
The following data refers to a hard disk;
number of tracks per side=600;
number of sides=2;
Number of bytes per sector=512;
Storage capacity in bytes=21 504 000
Determine the number of sectors per track for this hard disk
35 | |
40 | |
45 | |
50 |
Question 146 Explanation:
Storage capacity in bytes= (number of tracks per side*number of sides*Number of bytes per sector*number of sectors per track)
Here, we have to find number of sectors per track.
Total storage capacity / (Number of bytes per sector*number of sides*number of tracks per side)
=21504000 / (512*2*600)
=35
Here, we have to find number of sectors per track.
Total storage capacity / (Number of bytes per sector*number of sides*number of tracks per side)
=21504000 / (512*2*600)
=35
Question 147 |
The technology that stores only the essential instructions on a microprocessor chip and thus enhances its speed is referred to as
MIMD | |
CISC | |
RISC | |
SIMD |
Question 147 Explanation:
A reduced instruction set computer(or)RISC is one whose instruction set architecture (ISA) allows it to have fewer cycles per instruction (CPI) than a complex instruction set computer (CISC).
Question 148 |
When a subroutine is called, the add the instruction following the instruction stored in/on the____
Program counter | |
Stack | |
Stack pointer | |
accumulator |
Question 148 Explanation:
The Program Counter is incremented after fetching an instruction, and holds the memory address of ("points to") the next instruction that would be executed.
Question 149 |
A register in the microprocessor that keeps track of the answer or resulting of any arithmetic or logic operation is the___
Accumulator | |
Stack pointer | |
Program Counter | |
Instruction pointer |
Question 149 Explanation:
→ In a computer's central processing unit (CPU), the accumulator is a register in which intermediate arithmetic and logic results are stored.
→ Without a register like an accumulator, it would be necessary to write the result of each calculation (addition, multiplication, shift, etc.) to main memory, perhaps only to be read right back again for use in the next operation.
→ Without a register like an accumulator, it would be necessary to write the result of each calculation (addition, multiplication, shift, etc.) to main memory, perhaps only to be read right back again for use in the next operation.
Question 150 |
On which of the following storage media, storage of information is organized as a single continuous spiral groove?
CD-ROM | |
RAM | |
Hard disk | |
Floppy disk |
Question 150 Explanation:
Compact Disk: original physical design for audio
Question 151 |
Which of the following memory improves the speed of execution of a program?
Virtual memory | |
Primary memory | |
Secondary memory | |
Cache memory |
Question 151 Explanation:
Cache memory improves the speed of execution of a program. But it is costly. When compare to registers, registers are more faster than cache memory.
Question 152 |
In which addressing mode, the operand is given explicitly in the instruction(example instruction: ADD R4,#3?
Based indexed mode | |
Absolute mode | |
Immediate mode | |
Register indirect mode |
Question 152 Explanation:
Here, we are adding R4+3.
Immediate mode
In immediate addressing the operand is specified in the instruction itself. In this mode the data is 8 bits or 16 bits long and data is the part of instruction.
Example: MOV AL, 35H (move the data 35H into AL register)
Immediate mode
In immediate addressing the operand is specified in the instruction itself. In this mode the data is 8 bits or 16 bits long and data is the part of instruction.
Example: MOV AL, 35H (move the data 35H into AL register)
Question 153 |
Which of the following is not a program instruction?
CMP | |
MOV | |
JMP | |
CALL |
Question 153 Explanation:
CMP
The CMP instruction compares two operands. It is generally used in conditional execution. This instruction basically subtracts one operand from the other for comparing whether the operands are equal or not. It does not disturb the destination or source operands. It is used along with the conditional jump instruction for decision making.
Syntax: CMP destination, source
MOV
The MOV instruction is the most important command in the 8086 because it moves data from one location to another. It also has the widest variety of parameters; so it the assembler programmer can use MOV effectively, the rest of the commands are easier to understand.
Syntax: MOV destination,source
JMP Conditional execution often involves a transfer of control to the address of an instruction that does not follow the currently executing instruction. Transfer of control may be forward, to execute a new set of instructions or backward, to re-execute the same steps.
Syntax: JMP label
CALL
The CALL instruction interrupts the flow of a program by passing control to an internal or external subroutine. An internal subroutine is part of the calling program. An external subroutine is another program.
Syntax: CMP destination, source
MOV
The MOV instruction is the most important command in the 8086 because it moves data from one location to another. It also has the widest variety of parameters; so it the assembler programmer can use MOV effectively, the rest of the commands are easier to understand.
Syntax: MOV destination,source
JMP Conditional execution often involves a transfer of control to the address of an instruction that does not follow the currently executing instruction. Transfer of control may be forward, to execute a new set of instructions or backward, to re-execute the same steps.
Syntax: JMP label
CALL
The CALL instruction interrupts the flow of a program by passing control to an internal or external subroutine. An internal subroutine is part of the calling program. An external subroutine is another program.
Question 154 |
The addressing mode used in an instruction of the form ADD X,Y is:
index | |
absolute | |
immediate | |
indirect |
Question 154 Explanation:
The addressing mode used in an instruction of the form ADD X,Y is absolute addressing mode.
Question 155 |
Program counter contents indicate
The time needed to execute a program | |
The time elapsed since execution begins | |
The address where next instruction is stored | |
The count of programs being executed after switching the power ON |
Question 155 Explanation:
The Program Counter is incremented after fetching an instruction, and holds the memory address of ("points to") the next instruction that would be executed.
Question 156 |
____ refers to the amount of time required to position the read write head of a hard disk on appropriate sector
Load Time | |
Seek time | |
Access time | |
Rotational latency |
Question 156 Explanation:
Seek time
→ It measures the time it takes the head assembly on the actuator arm to travel to the track of the disk where the data will be read or written. The data on the media is stored in sectors which are arranged in parallel circular tracks (concentric or spiral depending upon the device type) and there is an actuator with an arm that suspends a head that can transfer data with that media.
→ Average seek time is the average of all possible seek times which technically is the time to do all possible seeks divided by the number of all possible seeks, but in practice it is determined by statistical methods or simply approximated as the time of a seek over one third of the number of tracks.
Rotational latency (sometimes called rotational delay or just latency :
It is the delay waiting for the rotation of the disk to bring the required disk sector under the read-write head. It depends on the rotational speed of a disk (or spindle motor), measured in revolutions per minute (RPM).
→ Maximum latency = 60/rpm
→ Average latency = 0.5*Latency Time
Transfer Time Transfer time is the time to transfer the data. It depends on the rotating speed of the disk and number of bytes to be transferred. Disk Access Time Disk Access Time = Seek Time + Rotational Latency + Transfer Time
→ Average seek time is the average of all possible seek times which technically is the time to do all possible seeks divided by the number of all possible seeks, but in practice it is determined by statistical methods or simply approximated as the time of a seek over one third of the number of tracks.
Rotational latency (sometimes called rotational delay or just latency :
It is the delay waiting for the rotation of the disk to bring the required disk sector under the read-write head. It depends on the rotational speed of a disk (or spindle motor), measured in revolutions per minute (RPM).
→ Maximum latency = 60/rpm
→ Average latency = 0.5*Latency Time
Transfer Time Transfer time is the time to transfer the data. It depends on the rotating speed of the disk and number of bytes to be transferred. Disk Access Time Disk Access Time = Seek Time + Rotational Latency + Transfer Time
Question 157 |
A digital computer has a memory unit of 64k x 16 and a cache memory of 10 words. The cache uses Direct mapping with a block size of four words. How many bits are there in the tag, index and block Fields of address format?
1, 6, 16
| |
28
| |
6, 8, 2 | |
24
|
Question 157 Explanation:
MM size = 64K × 16 = 216 × 16 i.e., MM has 216 words
Therefore Physical address = PA = 16 bits
No. of blocks in cache = cache-size/block-size = 210/ 23 = 28 = 256
∴ 8 bits for block
As block size = 4 words = 22 words
∴ 2 bits for offset
Now, tag = 16 - 8 - 2 = 6 bits
a) Tag = 6 bits, Index = block = 8 bits, offset = word = 2 bits
Therefore Physical address = PA = 16 bits
No. of blocks in cache = cache-size/block-size = 210/ 23 = 28 = 256
∴ 8 bits for block
As block size = 4 words = 22 words
∴ 2 bits for offset
Now, tag = 16 - 8 - 2 = 6 bits
a) Tag = 6 bits, Index = block = 8 bits, offset = word = 2 bits
Question 158 |
A computer employs RAM chips of 256x8 ROM chip of 1024x8. The computer system needs 2k bytes of RAM, 4k bytes of ROM and 4 interface units each with four registers. A memory mapped I/O configuration is used. How many RAM and ROM chips are used?
4, 16 | |
16, 4 | |
4, 8 | |
8, 4 |
Question 158 Explanation:
→ Size of RAM chip is = 256 x 8
Memory size required = 2k bytes = 2*1024*8 bits
= [Memory size required] / [Size of RAM chip] = 8
→ Size of ROM chip is = 1024*8
Memory size required = 4k bytes = 4*1024*8 bits
= [Memory size required] / [Size of ROM chip] = 4
Memory size required = 2k bytes = 2*1024*8 bits
= [Memory size required] / [Size of RAM chip] = 8
→ Size of ROM chip is = 1024*8
Memory size required = 4k bytes = 4*1024*8 bits
= [Memory size required] / [Size of ROM chip] = 4
Question 159 |
EEPROM is
Efficiently erasable programmable read only memory | |
Electrically erasable programmable read only memory | |
Electronically erasable programmable read only memory | |
Electrically and Electronically programmable read only memory |
Question 159 Explanation:
Electrically Erasable Programmable Read-Only Memory is a type of non-volatile memory used in computers, integrated in microcontrollers for smart cards and remote keyless systems, and other electronic devices to store relatively small amounts of data but allowing individual bytes to be erased and reprogrammed.
Question 160 |
A group of bits that tells the computer to perform a specific operation is known as
Instruction code | |
Micro operation | |
Accumulator | |
Register |
Question 160 Explanation:
→An instruction code is a group of bits that instruct the computer to perform a specific operation.
→The operation code of an instruction is a group of bits that define operations such as addition, subtraction, shift, complement, etc.
→An instruction must also include one or more operands, which indicate the registers and/or memory addresses from which data is taken or to which data is deposited.
→The operation code of an instruction is a group of bits that define operations such as addition, subtraction, shift, complement, etc.
→An instruction must also include one or more operands, which indicate the registers and/or memory addresses from which data is taken or to which data is deposited.
Question 161 |
If a value V(x) of the target operand is contained in the field itself, the addressing mode is called
Immediate | |
Direct | |
Indirect | |
Implied |
Question 161 Explanation:
As mentioned in the question “Target operand is contained in the field itself”. It should be immediate addressing mode
Question 162 |
Arrange the following in the order of decreasing access time:
Disk,tape,Cache,RAM | |
tape,Disk,RAM,Cache | |
Cache,RAM,Disk,tape | |
tape,Disk,cache,RAM
|
Question 162 Explanation:
→Access time is the time from the start of one storage device access to the time when the next access can be started.
→Tape has quite a long latency for random accesses since the deck must wind an average of one-third the tape length to move from one arbitrary data block to another
→ Access time to a hard disk or CD-ROM is usually measured in milliseconds.
→ Access time to RAM is usually measured in nanoseconds.
→The access time of Cache is very less compared to remaining .
→Tape has quite a long latency for random accesses since the deck must wind an average of one-third the tape length to move from one arbitrary data block to another
→ Access time to a hard disk or CD-ROM is usually measured in milliseconds.
→ Access time to RAM is usually measured in nanoseconds.
→The access time of Cache is very less compared to remaining .
Question 163 |
Which of the following is INCORRECT?
Non Maskable interrupts are reserved for unrecoverable memory error | |
Vectored interrupt mechanism reduces the need for searching all possible sources of interrupt | |
Priority interrupt mechanism enables preemption of high priority interrupt | |
System calls are implemented using software interrupts |
Question 163 Explanation:
→Priority Interrupt are systems, that establishes a Priority over the various sources(interrupt devices) to determine which condition is to be serviced first when two or more requests arrive simultaneously.
→This system may also determine which condition are permitted to interrupt to the computer while another interrupt is being serviced.
→This system may also determine which condition are permitted to interrupt to the computer while another interrupt is being serviced.
Question 164 |
Consider the following program fragment in assembly language :
mov ax, 0h
mov cx, 0A h
doloop:
dec ax
loop doloop
What is the value of ax and cx registers after the completion of the doloop ?
mov ax, 0h
mov cx, 0A h
doloop:
dec ax
loop doloop
What is the value of ax and cx registers after the completion of the doloop ?
ax=FFF5 h and cx=0 h | |
ax=FFF6 h and cx=0 h
| |
ax=FFF7 h and cx=0A h | |
ax=FFF5 h and cx=0A h
|
Question 164 Explanation:
Here ax is assigned value 0 and cx is assigned 0Ah which is equivalent to 10. Within the doloop we decrement the value of ax by 1 and the loop statement decrements cx by 1 untial cx becomes 1.
So
In 1st iteration: ax is decremented by 1, means its latest value will be -1. cx will be decremented by 1, so its latest value will be 9.
In 2nd iteration: ax will become -2. cx will become 8.
In 3rd iteration: ax will become -3. cx will become 7.
In 4th iteration: ax will become -4. cx will become 6.
In 5th iteration: ax will become -5. cx will become 5.
In 6th iteration: ax will become -6. cx will become 4.
In 7th iteration: ax will become -7. cx will become 3.
In 8th iteration: ax will become -8. cx will become 2.
In 9th iteration: ax will become -9. cx will become 1.
In 10th iteration: ax will become -10. cx will become 0.
At this stage the loop breaks as the value of cx is 0. Final value in ax is -10 which in hexadecimal equivalent to FFF6h and cx=0h
Hence option B is the answer.
So
In 1st iteration: ax is decremented by 1, means its latest value will be -1. cx will be decremented by 1, so its latest value will be 9.
In 2nd iteration: ax will become -2. cx will become 8.
In 3rd iteration: ax will become -3. cx will become 7.
In 4th iteration: ax will become -4. cx will become 6.
In 5th iteration: ax will become -5. cx will become 5.
In 6th iteration: ax will become -6. cx will become 4.
In 7th iteration: ax will become -7. cx will become 3.
In 8th iteration: ax will become -8. cx will become 2.
In 9th iteration: ax will become -9. cx will become 1.
In 10th iteration: ax will become -10. cx will become 0.
At this stage the loop breaks as the value of cx is 0. Final value in ax is -10 which in hexadecimal equivalent to FFF6h and cx=0h
Hence option B is the answer.
Question 165 |
Consider the following assembly program fragment :
stc
mov al, 11010110b
mov cl, 2
rcl al, 3
rol al, 4
shr al, cl
mul cl
The contents of the destination register ax (in hexadecimal) and the status of Carry Flag (CF) after the execution of above instructions, are:
stc
mov al, 11010110b
mov cl, 2
rcl al, 3
rol al, 4
shr al, cl
mul cl
The contents of the destination register ax (in hexadecimal) and the status of Carry Flag (CF) after the execution of above instructions, are:
ax=003CH; CF=0 | |
ax=001EH; CF=0 | |
ax=007BH; CF=1 | |
ax=00B7H; CF=1
|
Question 166 |
Match the following Layers and Protocols for a user browsing with SSL :
a-(iv), b-(i), c-(ii), d-(iii) | |
a-(iii), b-(ii), c-(i), d-(iv) | |
a-(ii), b-(iii), c-(iv), d-(i) | |
a-(iii), b-(i), c-(iv), d-(ii) |
Question 166 Explanation:
HTTP→ Application layer
TCP→ Transport layer
IP→ Network layer
PPP→ Data link layer
TCP→ Transport layer
IP→ Network layer
PPP→ Data link layer
Question 167 |
Consider the following assembly language instructions :
mov al, 15
mov ah, 15
xor al, al
mov cl, 3
shr ax, cl
add al, 90H
adc ah, 0
What is the value in ax register after execution of above instructions ?
mov al, 15
mov ah, 15
xor al, al
mov cl, 3
shr ax, cl
add al, 90H
adc ah, 0
What is the value in ax register after execution of above instructions ?
0270H | |
0170H | |
01E0H | |
0370H |
Question 167 Explanation:
Step-1: mov al, 15 → move 15 to lower part of 'ax' register
mov ah, 15 → move 15 to higher part of 'ax' register
XOR al,al → Convert 15 into binary number and perform XOR operation with ‘ax’
register. The final binary value is 0000111100000000
move cl,3 → move 3 to lower part of 'cx' register.
shr ax, cl → will shift right and rotate content of 'ax' register
The 'ax' register content looks like 0000000111100000
add al, 90H → add hexadecimal 90 to al
0000000111100000
0000000010010000
---------------------------
0000001001110000
-
---------------------------
adc ah,0 → addition with carry which does not affect 'ax' register.
Step-2: Finally the content of ‘ax’ register will be 0270H.
mov ah, 15 → move 15 to higher part of 'ax' register
XOR al,al → Convert 15 into binary number and perform XOR operation with ‘ax’
register. The final binary value is 0000111100000000
move cl,3 → move 3 to lower part of 'cx' register.
shr ax, cl → will shift right and rotate content of 'ax' register
The 'ax' register content looks like 0000000111100000
add al, 90H → add hexadecimal 90 to al
0000000111100000
0000000010010000
---------------------------
0000001001110000
-
---------------------------
adc ah,0 → addition with carry which does not affect 'ax' register.
Step-2: Finally the content of ‘ax’ register will be 0270H.
Question 168 |
The contents of Register (BL) and Register (AL) of 8085 microprocessor are 49H and 3AH respectively. The contents of AL, the status of carry flag (CF) and sign flag (SF) after executing ‘SUB AL, BL’ assembly language instruction, are
AL = 0FH; CF = 1; SF = 1 | |
AL = F0H; CF = 0; SF = 0 | |
AL = F1H; CF = 1; SF = 1 | |
AL = 1FH; CF = 1; SF = 1 |
Question 168 Explanation:
Initially BL=0100 1001 and AL=0011 1010
Step-1: We have to perform subtraction of AL and BL
AL= 0011 1010 ( Here, MSB and Second MSB bit taken borrow 1)
BL= 0111 1001
------------------
1111 0001
------------------
Step-2: Final result have to be stored in AL. AL = F1H; CF = 1; SF = 1
So, option C is the correct answer.
Step-1: We have to perform subtraction of AL and BL
AL= 0011 1010 ( Here, MSB and Second MSB bit taken borrow 1)
BL= 0111 1001
------------------
1111 0001
------------------
Step-2: Final result have to be stored in AL. AL = F1H; CF = 1; SF = 1
So, option C is the correct answer.
Question 169 |
Match the following w.r.t. Input/Output management :
a-iii, b-iv, c-i, d-ii | |
a-ii, b-i, c-iv, d-iii | |
a-iv, b-i, c-ii, d-iii | |
a-i, b-iii, c-iv, d-ii |
Question 169 Explanation:
Device controller→ Performs data transfer
The Device Controller works like an interface between a device and a device driver. I/O units (Keyboard, mouse, printer, etc.) typically consist of a mechanical component and an electronic component where electronic component is called the device controller.
Device driver → Processing of I/O request
Device drivers are modules that can be plugged into an OS to handle a particular device or category of similar devices.
Interrupt handler→ Extracts information from the controller register and store it in data buffer
Interrupt handlers have a multitude of functions, which vary based on what triggered the interrupt and the speed at which the interrupt handler completes its task. For example, pressing a key on a computer keyboard.
Kernel I/O subsystem→ I/O scheduling
Kernel provide many services related to I/O. Several services like scheduling, buffering, caching, spooling, device reservation and error handling. These are provided by the kernel’s I/O subsystem and build on the hardware and device driver infrastructure.
The Device Controller works like an interface between a device and a device driver. I/O units (Keyboard, mouse, printer, etc.) typically consist of a mechanical component and an electronic component where electronic component is called the device controller.
Device driver → Processing of I/O request
Device drivers are modules that can be plugged into an OS to handle a particular device or category of similar devices.
Interrupt handler→ Extracts information from the controller register and store it in data buffer
Interrupt handlers have a multitude of functions, which vary based on what triggered the interrupt and the speed at which the interrupt handler completes its task. For example, pressing a key on a computer keyboard.
Kernel I/O subsystem→ I/O scheduling
Kernel provide many services related to I/O. Several services like scheduling, buffering, caching, spooling, device reservation and error handling. These are provided by the kernel’s I/O subsystem and build on the hardware and device driver infrastructure.
Question 170 |
The content of the accumulator after the execution of the following 8085 assembly language program, is
MVI A, 35H
MOV B, A
STC
CMC
RAR
XRA B
MVI A, 35H
MOV B, A
STC
CMC
RAR
XRA B
00H | |
35H | |
EFH | |
2FH |
Question 170 Explanation:
MVI A, 35H ← Accumulator A = 35H = 0011 0101
MOV B, A ← B=A;
B = 35H= 0011 0101
STC ← Set the carry flag; Carry C=1
CMC ← Complement the carry flag; Carry C=0
RAR ← Rotate the Accumulator(A) right through Carry C
A C = 0011 0101 0 ← before Rotation
A C = 0001 1010 1 ← After Rotation
XRA B ← A= A ⊕ B
A 0001 1010
B 0011 0101
---------------
A ⊕ B = 0010 1111
--------------
= 2 F
MOV B, A ← B=A;
B = 35H= 0011 0101
STC ← Set the carry flag; Carry C=1
CMC ← Complement the carry flag; Carry C=0
RAR ← Rotate the Accumulator(A) right through Carry C
A C = 0011 0101 0 ← before Rotation
A C = 0001 1010 1 ← After Rotation
XRA B ← A= A ⊕ B
A 0001 1010
B 0011 0101
---------------
A ⊕ B = 0010 1111
--------------
= 2 F
Question 171 |
The content of the accumulator after the execution of the following 8085 assembly language program, is:
MVI A, 42H
MVI B, 05H
UGC: ADD B
DCR B
JNZ UGC
ADI 25H
HLT
82 H | |
78 H | |
76 H | |
47 H |
Question 171 Explanation:
Step-1: MVI A, 42H given 42 value in hexadecimal and storing value in Accumulator A.
For solving problem, convert (42) 16 into decimal is (66) 10
Step-2: MVI B, 05H given 05 value in hexadecimal and storing value in Accumulator B.
For solving problem, convert (05) 16 into decimal is (05) 10
Step-3: ADD B until UGC will fail. Contents of accumulator A value and B value will add.
66+5=71
Step-4: DCR B it means decrement by 1.
71+4=75
Step-5: JNZ means jump not equals to zero.
75+3=78
78+2=80
80+1=81
Step-6: It became false, then execute next statement.
ADI 25H means add 25H to (81) 10
(25) 16 = (37) 10
37+81=(118) 10
Finally
convert decimal value into Hexadecimal.
(118) 10 = (76) 16
Step-7: HLT means halt the program.
Note: We are converting hexadecimal into decimal for only calculation. without conversion also we can solve a problem.
For solving problem, convert (42) 16 into decimal is (66) 10
Step-2: MVI B, 05H given 05 value in hexadecimal and storing value in Accumulator B.
For solving problem, convert (05) 16 into decimal is (05) 10
Step-3: ADD B until UGC will fail. Contents of accumulator A value and B value will add.
66+5=71
Step-4: DCR B it means decrement by 1.
71+4=75
Step-5: JNZ means jump not equals to zero.
75+3=78
78+2=80
80+1=81
Step-6: It became false, then execute next statement.
ADI 25H means add 25H to (81) 10
(25) 16 = (37) 10
37+81=(118) 10
Finally
convert decimal value into Hexadecimal.
(118) 10 = (76) 16
Step-7: HLT means halt the program.
Note: We are converting hexadecimal into decimal for only calculation. without conversion also we can solve a problem.
Question 172 |
Pipelining improves performance by:
decreasing instruction latency | |
eliminating data hazards | |
exploiting instruction level parallelism | |
decreasing the cache miss rate |
Question 172 Explanation:
→ Pipelining improves performance by exploiting instruction level parallelism.
→ Instruction pipelining is a technique for implementing instruction-level parallelism within a single processor.
→ Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming instructions into a series of sequential steps (the eponymous "pipeline") performed by different processor units with different parts of instructions processed in parallel.
→ It allows faster CPU throughput than would otherwise be possible at a given clock rate, but may increase latency due to the added overhead of the pipelining process itself.
→ Instruction pipelining is a technique for implementing instruction-level parallelism within a single processor.
→ Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming instructions into a series of sequential steps (the eponymous "pipeline") performed by different processor units with different parts of instructions processed in parallel.
→ It allows faster CPU throughput than would otherwise be possible at a given clock rate, but may increase latency due to the added overhead of the pipelining process itself.
Question 173 |
What will be the hexadecimal value in the register ax (32-bit) after executing the following instructions?
mov al, 15
mov ah, 15
xor al, al
mov cl, 3
shr ax, cl
mov al, 15
mov ah, 15
xor al, al
mov cl, 3
shr ax, cl
0F00 h | |
0F0F h | |
01E0 h | |
FFFF h |
Question 173 Explanation:
Step-1: mov al, 15 ← Move 15 to lower part of 'ax' register
Step-2: mov ah, 15 ← Move 15 to higher part of 'ax' register
Step-3: xor al,al ← Perform Xor operation.
convert 15 into binary number is 00001111
00001111 ← al
00000000 ← al
-------------
00000000
--------------
Step-4: move cl,3 ← Move 3 to lower part of 'cx' register
Step-5: shr ax, cl ← It will shift right and rotate content of 'ax' register
Before shifting ‘ax’ value is 0000 1111 0000 0000
After 3 shift right operations then ‘ax’ will become 0000 0001 1110 0000
The value is nothing but 01E0 h (or) (01E0) 16
Step-2: mov ah, 15 ← Move 15 to higher part of 'ax' register
Step-3: xor al,al ← Perform Xor operation.
convert 15 into binary number is 00001111
00001111 ← al
00000000 ← al
-------------
00000000
--------------
Step-4: move cl,3 ← Move 3 to lower part of 'cx' register
Step-5: shr ax, cl ← It will shift right and rotate content of 'ax' register
Before shifting ‘ax’ value is 0000 1111 0000 0000
After 3 shift right operations then ‘ax’ will become 0000 0001 1110 0000
The value is nothing but 01E0 h (or) (01E0) 16
Question 174 |
Which of the following statements is false?
Top-down parsers are LL parsers where first L stands for left - to - right scan and second L stands for a leftmost derivation. | |
(000)* is a regular expression that matches only strings containing an odd number of zeroes, including the empty string. | |
Bottom-up parsers are in the LR family, where L stands for left - to - right scan and R stands for rightmost derivation. | |
The class of context - free languages is closed under reversal. That is, if L is any context- free language, then the language L R = {w R : w∈L} is context - free. |
Question 174 Explanation:
TRUE: Top-down parsers are LL parsers where first L stands for left - to - right scan and second L stands for a leftmost derivation.
FALSE: (000)* is a regular expression that matches any string containing at least 3 number of zeroes, including the empty string.
TRUE: Bottom-up parsers are in the LR family, where L stands for left - to - right scan and R stands for rightmost derivation.
TRUE: The class of context - free languages is closed under reversal. That is, if L is any context - free language, then the language L R = {w R : w∈L} is context - free.
FALSE: (000)* is a regular expression that matches any string containing at least 3 number of zeroes, including the empty string.
TRUE: Bottom-up parsers are in the LR family, where L stands for left - to - right scan and R stands for rightmost derivation.
TRUE: The class of context - free languages is closed under reversal. That is, if L is any context - free language, then the language L R = {w R : w∈L} is context - free.
Question 175 |
In the case of parallelization, Amdahl’s law states that if P is the proportion of a program that can be made parallel and (1 -P) is the proportion that cannot be parallelized, then the maximum speed-up that can be achieved by using N processors is:
1/((1−p)+ N .P) | |
1/((N −1)P +P) | |
1/((1−P )+ P /N) | |
1/((P)+(1-P)/N) |
Question 175 Explanation:
Amdahl’s law can be formulated in the following way:
where
● S latency is the theoretical speedup of the execution of the whole task;
● s is the speedup of the part of the task that benefits from improved system resources;
● p is the proportion of execution time that the part benefiting from improved resources originally occupied.
Furthermore,
shows that the theoretical speedup of the execution of the whole task increases with the improvement of the resources of the system and that regardless of the magnitude of the improvement, the theoretical speedup is always limited by the part of the task that cannot benefit from the improvement.
→ Amdahl's law applies only to the cases where the problem size is fixed. In practice, as more computing resources become available, they tend to get used on larger problems (larger datasets), and the time spent in the parallelizable part often grows much faster than the inherently serial work. In this case, Gustafson's law gives a less pessimistic and more realistic assessment of the parallel performance.
where
● S latency is the theoretical speedup of the execution of the whole task;
● s is the speedup of the part of the task that benefits from improved system resources;
● p is the proportion of execution time that the part benefiting from improved resources originally occupied.
Furthermore,
shows that the theoretical speedup of the execution of the whole task increases with the improvement of the resources of the system and that regardless of the magnitude of the improvement, the theoretical speedup is always limited by the part of the task that cannot benefit from the improvement.
→ Amdahl's law applies only to the cases where the problem size is fixed. In practice, as more computing resources become available, they tend to get used on larger problems (larger datasets), and the time spent in the parallelizable part often grows much faster than the inherently serial work. In this case, Gustafson's law gives a less pessimistic and more realistic assessment of the parallel performance.
Question 176 |
The Register or main memory location which contains the effective address of the operand is known as :
Pointer | |
Indexed register | |
Special Locations | |
Scratch Pad |
Question 176 Explanation:
→ The effective address of the operand is the contents of a register or main memory location, location whose address appears in the instruction.
→ Indirection is noted by placing the name of the register or the memory address given in the instruction in parentheses.
→ The register or memory location that contains the address of the operand is a pointer. When an execution takes place in such mode, instruction may be told to go to a specific address. Once it's there, instead of finding an operand, it finds an address where the operand is located.
Note:Two memory accesses are required in order to obtain the value of the operand (fetch operand address and fetch operand value).
Example: (textbook) ADD (A), R0
(address A is embedded in the instruction code and (A) is the operand address = pointer variable)
→ Indirection is noted by placing the name of the register or the memory address given in the instruction in parentheses.
→ The register or memory location that contains the address of the operand is a pointer. When an execution takes place in such mode, instruction may be told to go to a specific address. Once it's there, instead of finding an operand, it finds an address where the operand is located.
Note:Two memory accesses are required in order to obtain the value of the operand (fetch operand address and fetch operand value).
Example: (textbook) ADD (A), R0
(address A is embedded in the instruction code and (A) is the operand address = pointer variable)
Question 177 |
The principle of Locality of reference justifies the use of :
Virtual memory | |
Interrupts | |
Cache memory | |
Secondary memory |
Question 177 Explanation:
→ The principle of Locality of reference justifies the use of cache memory. The principle of locality, is the tendency of a processor to access the same set of memory locations repetitively over a short period of time.
→ Locality is merely one type of predictable behavior that occurs in computer systems. Systems that exhibit strong locality of reference are great candidates for performance optimization through the use of techniques such as the caching, prefetching for memory and advanced branch predictors at the pipelining stage of a processor core.
→ Locality is merely one type of predictable behavior that occurs in computer systems. Systems that exhibit strong locality of reference are great candidates for performance optimization through the use of techniques such as the caching, prefetching for memory and advanced branch predictors at the pipelining stage of a processor core.
Question 178 |
The first operating system of Microprocessor is __________ .
ATLAS | |
CP/M | |
SAGE | |
T.H.E. |
Question 178 Explanation:
The first operating system of Microprocessor is CP/M.
CP/M (Control Program/Monitor (or) Control Program for Microcomputers)
It is a mass-market operating system created in 1974 for Intel 8080/85-based microcomputers by Gary Kildall of Digital Research. Initially confined to single-tasking on 8-bit processors and no more than 64 kilobytes of memory, later versions of CP/M added multi-user variations and were migrated to 16-bit processors.
CP/M (Control Program/Monitor (or) Control Program for Microcomputers)
It is a mass-market operating system created in 1974 for Intel 8080/85-based microcomputers by Gary Kildall of Digital Research. Initially confined to single-tasking on 8-bit processors and no more than 64 kilobytes of memory, later versions of CP/M added multi-user variations and were migrated to 16-bit processors.
Question 179 |
The size of the ROM required to build an 8-bit adder/subtractor with mode control, carry input, carry output and two’s complement overflow output is given as
2 16 * 8 | |
2 18 * 10 | |
2 16 * 10 | |
2 18 * 8 |
Question 179 Explanation:
The size of the ROM required to build an 8-bit adder/subtractor with mode control, carry input, carry output and two’s complement overflow output is given as 2 18 * 10.
Question 180 |
The speed up of a pipeline processing over an equivalent non-pipeline processing is defined by the ratio :
Where n → no. of tasks
t<sub>n</sub>→ time of completion of each task
k → no. of segments of pipeline
t<sub>p</sub> → clock cycle time
S → speed up ratio
S =n tn/(k + n – 1)tp | |
S =n tn/(k + n + 1)tp | |
S =n tn/(k – n + 1)tp | |
S =(k + n – 1)tp/n tn |
Question 180 Explanation:
Without pipeline one task needs tn time. So, n tasks need n*tn time.
T without pipeline = n*tn
With pipeline: First task needs k cycles to finish. So time for 1st task will be k*tp
Each of the other n-1 tasks need tp time only to finish.
So, T pipeline = (k+n-1)*tp
Speed up = T without pipeline / T pipeline = n*tn / (k+n-1)*tp
Question 181 |
In which addressing mode, the effective address of the operand is generated by adding a constant value to the contents of register ?
Absolute | |
Indirect | |
Immediate | |
Index |
Question 181 Explanation:
1. An absolute address is represented by the contents of a register. This addressing mode is absolute in the sense that it is not specified relative to the current instruction address.
2. Indirect addressing is a scheme in which the address specifies which memory word or register contains not the operand but the address of the operand.
Immediate Operand:
The simplest way for an instruction to specify an operand is for the address part of the instruction actually to contain the operand itself rather than an address or other information describing where the operand is. Such an operand is called an immediate operand because it is automatically fetched from memory at the same time the instruction itself is fetched. It is immediately available for use.
Index mode:
The address of the operand is obtained by adding to the contents of the general register (called index register) a constant value. The number of the index register and the constant value are included in the instruction code
2. Indirect addressing is a scheme in which the address specifies which memory word or register contains not the operand but the address of the operand.
Immediate Operand:
The simplest way for an instruction to specify an operand is for the address part of the instruction actually to contain the operand itself rather than an address or other information describing where the operand is. Such an operand is called an immediate operand because it is automatically fetched from memory at the same time the instruction itself is fetched. It is immediately available for use.
Index mode:
The address of the operand is obtained by adding to the contents of the general register (called index register) a constant value. The number of the index register and the constant value are included in the instruction code
Question 182 |
A graphic display system has a frame buffer that is 640 pixels wide, 480 pixels high and 1 bit of color depth. If the access time for each pixel on the average is 200 nanoseconds, then the refresh rate of this frame buffer is approximately :
16 frames per second | |
19 frames per second | |
21 frames per second | |
23 frames per second |
Question 182 Explanation:
Given data,
- Width (or) wide =640 pixels
- Height (or) High =480 pixels
- Color depth =1 bit/pixel
- Access time of each pixel on the average =200ns
- Refresh rate of frame buffer=?
Step-1: Graphic display system =640*480
=307200
Step-2: Memory required for Graphic display system =640*480*1 =307200
Step-3: Total screen access time = Memory required for Graphic display system * Access time of each pixel
= 307200*200 ns
= 61440000 ns
Step-4: Refresh rate of frame buffer per second=(10 -9 )/61440000
= 16.27604166 frames per second
[ Note: 10 -9 =1000000000 ]
- Width (or) wide =640 pixels
- Height (or) High =480 pixels
- Color depth =1 bit/pixel
- Access time of each pixel on the average =200ns
- Refresh rate of frame buffer=?
Step-1: Graphic display system =640*480
=307200
Step-2: Memory required for Graphic display system =640*480*1 =307200
Step-3: Total screen access time = Memory required for Graphic display system * Access time of each pixel
= 307200*200 ns
= 61440000 ns
Step-4: Refresh rate of frame buffer per second=(10 -9 )/61440000
= 16.27604166 frames per second
[ Note: 10 -9 =1000000000 ]
Question 183 |
Which of the following statements is/are True regarding the solution to the visibility problem in 3D graphics ?
S1 : The Painter’s algorithm sorts polygons by depth and then paints (scan - converts) each Polygon onto the screen starting with the most nearest polygon.
S2 : Backface Culling refers to eliminating geometry with back facing normals.
S1 : The Painter’s algorithm sorts polygons by depth and then paints (scan - converts) each Polygon onto the screen starting with the most nearest polygon.
S2 : Backface Culling refers to eliminating geometry with back facing normals.
S1 only | |
S2 only | |
Both S1 and S2 | |
Neither S1 Nor S2 |
Question 183 Explanation:
Visibility problem in 3D graphics
1. Painter's algorithm
-A depth sorting method
-Surfaces are sorted in the order of decreasing depth
-Surfaces are drawn in the sorted order, and overwrite the pixels in the frame buffer
-Subtle difference from depth buffer approach: entire face drawn
-Two problems:
1. It can be nontrivial to sort the surfaces
2. There can be no solution for the sorting order
2. Back Face Culling
-Back faces: faces of opaque object which are “pointing away” from viewer
-Back face culling – remove back faces (supported by OpenGL)
How to detect back faces
-If we find backface, do not draw, save rendering resources
-There must be other forward face(s) closer to eye
-F is face of object we want to test if backface
-P is a point on F
-Form view vector, V as (eye – P)
-N is normal to face F
3. View-Frustum Culling
-Remove objects that are outside the viewing frustum
-Done by 3D clipping algorithm (e.g. Liang-Barsky)
4. Ray Tracing
-Ray tracing is another example of image space method
-Ray tracing: Cast a ray from eye through each pixel to the world.
5. Z(Depth buffer algorithm)
1. Painter's algorithm
-A depth sorting method
-Surfaces are sorted in the order of decreasing depth
-Surfaces are drawn in the sorted order, and overwrite the pixels in the frame buffer
-Subtle difference from depth buffer approach: entire face drawn
-Two problems:
1. It can be nontrivial to sort the surfaces
2. There can be no solution for the sorting order
2. Back Face Culling
-Back faces: faces of opaque object which are “pointing away” from viewer
-Back face culling – remove back faces (supported by OpenGL)
How to detect back faces
-If we find backface, do not draw, save rendering resources
-There must be other forward face(s) closer to eye
-F is face of object we want to test if backface
-P is a point on F
-Form view vector, V as (eye – P)
-N is normal to face F
3. View-Frustum Culling
-Remove objects that are outside the viewing frustum
-Done by 3D clipping algorithm (e.g. Liang-Barsky)
4. Ray Tracing
-Ray tracing is another example of image space method
-Ray tracing: Cast a ray from eye through each pixel to the world.
5. Z(Depth buffer algorithm)
Question 184 |
Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with memory mapped I/O, there is no explicit I/O instruction. Which one of the following is true for a CPU with memory mapped I/O ?
I/O protection is ensured by operating system routines. | |
I/O protection is ensured by a hardware trap. | |
I/O protection is ensured during system configuration. | |
I/O protection is not possible. |
Question 184 Explanation:
→ I/O protection can be ensured by operating system. Because all the user application are not modified by user mode. Those are sent to kernel mode as a system calls.
→ Normally user programs are prevented from handling I/O directly by I/O instructions in them , For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instruction privileged.
→ Normally user programs are prevented from handling I/O directly by I/O instructions in them , For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instruction privileged.
Question 185 |
Which of the following mapping is not used for mapping process in cache memory?
Associative mapping | |
Direct mapping | |
Set-Associative mapping | |
Segmented - page mapping |
Question 185 Explanation:
Segmented - page mapping is the mapping not used for mapping process in cache memory
Question 186 |
In 8085 microprocessor, what is the output of following program ? LDA 8000H MVI B, 30H ADD B STA 8001H
Read a number from input port and store it in memory | |
Read a number from input device with address 8000H and store it in memory at location 8001H | |
Read a number from memory at location 8000H and store it in memory location 8001H | |
Load A with data from input device with address 8000H and display it on the output device with address 8001H |
Question 186 Explanation:
→ 1st instruction "LDA 8000H" transfers data from memory location 8000H to Accumulator
→ 2nd instruction "MVI B, 30H" moves 30H to register B.
→ 3rd instruction "ADD B" adds contents of B with Accumulator and stores it back to Accumulator. So basically the contents of Accumulator are incremented by 30H.
→ 4th instruction "STA 8001H" stores the contents of Accumulator in memory location 8001H.
As none of the choices include the 'addition operation', we need to choose appropriate option from the given options.
→ Option 4 mentions about loading the content from 8000H to accumulator A. Hence option 4 is more appropriate.
→ 2nd instruction "MVI B, 30H" moves 30H to register B.
→ 3rd instruction "ADD B" adds contents of B with Accumulator and stores it back to Accumulator. So basically the contents of Accumulator are incremented by 30H.
→ 4th instruction "STA 8001H" stores the contents of Accumulator in memory location 8001H.
As none of the choices include the 'addition operation', we need to choose appropriate option from the given options.
→ Option 4 mentions about loading the content from 8000H to accumulator A. Hence option 4 is more appropriate.
Question 187 |
The branch logic that provides making capabilities in the control unit is known as
Controlled transfer | |
Conditional transfer | |
Unconditional transfer | |
None of the above |
Question 187 Explanation:
The branch logic that provides making capabilities in the control unit is known as controlled transfer.
Question 188 |
Cached and interleaved memories are ways of speeding up memory access between CPU’s and slower RAM. Which memory models are best suited (i.e. improves the performance most) for which programs ?
(i) Cached memory is best suited for small loops.
(ii) Interleaved memory is best suited for small loops
(iii) Interleaved memory is best suited for large sequential code.
(iv) Cached memory is best suited for large sequential code.
(i) Cached memory is best suited for small loops.
(ii) Interleaved memory is best suited for small loops
(iii) Interleaved memory is best suited for large sequential code.
(iv) Cached memory is best suited for large sequential code.
(i) and (ii) are true. | |
(i) and (iii) are true. | |
(iv) and (ii) are true. | |
(iv) and (iii) are true. |
Question 188 Explanation:
→ Interleaved memory is a design made to compensate for the relatively slow speed of dynamic random-access memory (DRAM) or core memory, by spreading memory addresses evenly across memory banks.
That way, contiguous memory reads and writes are using each memory bank in turn, resulting in higher memory throughputs due to reduced waiting for memory banks to become ready for desired operations.
→ A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory.
→ A cache is a smaller, faster memory, closer to a processor core, which stores copies of the data from frequently used main memory locations.
→ Loops consist of frequently used variables.
That way, contiguous memory reads and writes are using each memory bank in turn, resulting in higher memory throughputs due to reduced waiting for memory banks to become ready for desired operations.
→ A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory.
→ A cache is a smaller, faster memory, closer to a processor core, which stores copies of the data from frequently used main memory locations.
→ Loops consist of frequently used variables.
Question 189 |
Interrupts which are initiated by an instruction are
Internal | |
External | |
Hardware | |
Software |
Question 189 Explanation:
→ An interrupt is a signal to the processor emitted by hardware or software indicating an event that needs immediate attention.
→ A software interrupt is caused either by an exceptional condition in the processor itself, or a special instruction in the instruction set which causes an interrupt when it is executed.
→ The former is often called a trap or exception and is used for errors or events occurring during program execution that are exceptional enough that they cannot be handled within the program itself.
→ Hardware interrupts are used by devices to communicate that they require attention from the operating system.
→ A software interrupt is caused either by an exceptional condition in the processor itself, or a special instruction in the instruction set which causes an interrupt when it is executed.
→ The former is often called a trap or exception and is used for errors or events occurring during program execution that are exceptional enough that they cannot be handled within the program itself.
→ Hardware interrupts are used by devices to communicate that they require attention from the operating system.
Question 190 |
A complete microcomputer system consists of
Microprocessor | |
Memory | |
Peripheral equipment | |
All of the above |
Question 190 Explanation:
A complete microcomputer system consists of Microprocessor,Memory and Peripheral equipment.
Question 191 |
Pipelining strategy is called implement
instruction execution | |
instruction prefetch | |
instruction decoding | |
instruction manipulation |
Question 191 Explanation:
→ Instruction prefetch is a technique used in central processor units to speed up the execution of a program by reducing wait states.
→ Pipelining strategy is called implement instruction prefetch.
→ Pipelining strategy is called implement instruction prefetch.
Question 192 |
Start and stop bits are used in serial communications for
Error detection
| |
Error correction | |
Synchronization | |
Slowing down the communication |
Question 192 Explanation:
Start and stop bits are used in serial communications for Synchronization.
Question 193 |
On receiving an interrupt from an I/O device, the CPU
halts for predetermined time. | |
branches off to the interrupt service routine after completion of the current instruction. | |
branches off to the interrupt service routine immediately. | |
hands over control of address bus and data bus to the interrupting device. |
Question 194 |
The maximum amount of information that is available in one portion of the disk access arm for a removal disk pack (without further movement of the arm with multiple heads)
a plate of data | |
a cylinder of data | |
a track of data | |
a block of data |
Question 194 Explanation:
A cylinder of data having maximum amount of information that is available in one portion of the disk access arm for a removal disk pack (without further movement of the arm with multiple heads).
Question 195 |
CPU does not perform the operation
data transfer | |
logic operation | |
arithmetic operation | |
all of the above
|
Question 195 Explanation:
A central processing unit (CPU) is the electronic circuitry within a computer that carries out the instructions of a computer program by performing the basic arithmetic, logical, control and input/output (I/O) operations specified by the instructions.
Question 196 |
The number of address lines in a memory chip of size 8 192 × 8 is
8 | |
12 | |
13 | |
16 |
Question 197 |
Intel 8086 is a
8 bit | |
16 bit | |
32 bit | |
64 bit |
Question 198 |
The first operating system used in microprocessor is
Zenix | |
DOS | |
CP/M | |
Multics |
Question 199 |
The sequence of events that happen during a typical fetch operation is
PC ⟶ Mar ⟶ Memory ⟶ MDR ⟶ IR | |
PC ⟶ Memory ⟶ MDR ⟶ IR | |
PC ⟶ Memory ⟶ IR | |
PC ⟶ MAR ⟶ Memory ⟶ IR |
Question 200 |
The addressing mode used in an instruction of the form ADD X Y, is
absolute | |
immediate | |
indirect | |
index |
Question 201 |
The circumference of the two concentric disks are divided into 100 sections each. For the outer disk, 100 of the sections are painted red and 100 of the sections are painted blue.For the inner disk, the sections are painted red and blue in an arbitrary manner. It is possible to align the two disks so that____of the sections on the inner disks have their colours matched with the corresponding section on outer disk.
100 or more | |
125 or more | |
150 or more | |
175 or more
|
Question 201 Explanation:
→ We fix the larger disk first, then place the smaller disk on the top of the larger disk so that the centers and sectors coincide. There are 200 ways to place the smaller disk in such a manner.
→ For each such alignment, some sectors of the two disks may have the same color. Since each sector of the smaller disk will match the same color sector of the larger disk 100 times among all the 200 ways and there are 200 sectors in the smaller disk, the total number of matched color sectors among the 200 ways is 100 × 200 = 20,000.
→ Note that there are only 200 ways. Then there is at least one way that the number of matched color sectors is 20,000 / 200 = 100 or more.
→ For each such alignment, some sectors of the two disks may have the same color. Since each sector of the smaller disk will match the same color sector of the larger disk 100 times among all the 200 ways and there are 200 sectors in the smaller disk, the total number of matched color sectors among the 200 ways is 100 × 200 = 20,000.
→ Note that there are only 200 ways. Then there is at least one way that the number of matched color sectors is 20,000 / 200 = 100 or more.
Question 202 |
Block or Buffer caches are used to
improve disk performance | |
handle interrupts | |
increase the capacity of main memory | |
speed up main memory Read operations |
Question 202 Explanation:
Block or Buffer caches are used to speed up main memory Read operations. By reading the information from disk only once and then keeping it in memory until no longer needed, one can speed up all but the first read. This is called disk buffering, and the memory used for the purpose is called the buffer cache.
Question 203 |
An instruction used to set the carry flag in a computer can be classified as
data transfer | |
arithmetic | |
logical | |
program control |
Question 204 |
In a microprocessor, the address of next instruction to be executed is stored in
Stack pointer | |
Address latch | |
Program counter | |
Any general purpose register |
Question 205 |
Which of the following μP is a 8 bit processor ?
80286 | |
8085 | |
80386 | |
8086 |
Question 206 |
Start and stop bits are used in serial communication for
error detection | |
error correction | |
synchronization | |
slowing down the communication |
Question 207 |
The register or main memory location which contains the effective address of the operand is known as
pointer | |
special location | |
indexed register | |
None of the above |
Question 207 Explanation:
The register or main memory location which contains the effective address of the operand is known as pointer.
Question 208 |
In which addressing mode the operand is given explicitly in the instruction itself ?
Absolute mode | |
Immediate mode | |
Indirect mode | |
Index mode |
Question 208 Explanation:
Immediate addressing mode the operand is given explicitly in the instruction itself.
Question 209 |
In which addressing mode, the effective address of the operand is generated by adding a constant value to the contents of register ?
absolute mode | |
immediate mode | |
indirect mode | |
index mode |
Question 209 Explanation:
Absolute address is represented by the contents of a register. This addressing mode is absolute in the sense that it is not specified relative to the current instruction address.
Indirect addressing is a scheme in which the address specifies which memory word or register contains not the operand but the address of the operand.
Immediate Operand: The simplest way for an instruction to specify an operand is for the address part of the instruction actually to contain the operand itself rather than an address or other information describing where the operand is. Such an operand is called an immediate operand because it is automatically fetched from memory at the same time the instruction itself is fetched. It is immediately available for use.
Index mode: The address of the operand is obtained by adding to the contents of the general register (called index register) a constant value. The number of the index register and the constant value are included in the instruction code.
Indirect addressing is a scheme in which the address specifies which memory word or register contains not the operand but the address of the operand.
Immediate Operand: The simplest way for an instruction to specify an operand is for the address part of the instruction actually to contain the operand itself rather than an address or other information describing where the operand is. Such an operand is called an immediate operand because it is automatically fetched from memory at the same time the instruction itself is fetched. It is immediately available for use.
Index mode: The address of the operand is obtained by adding to the contents of the general register (called index register) a constant value. The number of the index register and the constant value are included in the instruction code.
Question 210 |
In the indirect addressing scheme, the second part of an instruction contains :
the operand in decimal form | |
the address of the location where the value of the operand is stored
| |
the address of the location where the address of the operand is stored
| |
the operand in an encoded form |
Question 210 Explanation:
→ In the indirect addressing scheme, the second part of an instruction contains the address of the location where the address of the operand is stored.
→ Indirect addressing is a scheme in which the address specifies which memory word or register contains not the operand but the address of the operand.
Example: LOAD R1, @R2 Load the content of the memory address stored at register R2 to register R1.
→ Indirect addressing is a scheme in which the address specifies which memory word or register contains not the operand but the address of the operand.
Example: LOAD R1, @R2 Load the content of the memory address stored at register R2 to register R1.
Question 211 |
Amdahl’s law states that the maximum speedup S achievable by a parallel computer with ‘p’ processors is given by :
S≤f+(1-f)/p | |
S≤f/p+(1-f) | |
S≤1/[f+(1-f)/p] | |
S≤1/[1-f+f/p] |
Question 211 Explanation:
Amdahl’s law can be formulated in the following way:
where
→Slatency is the theoretical speedup of the execution of the whole task;
→s is the speedup of the part of the task that benefits from improved system resources;
→p is the proportion of execution time that the part benefiting from improved resources originally occupied.
Furthermore,
shows that the theoretical speedup of the execution of the whole task increases with the improvement of the resources of the system and that regardless of the magnitude of the improvement, the theoretical speedup is always limited by the part of the task that cannot benefit from the improvement.
→ Amdahl's law applies only to the cases where the problem size is fixed. In practice, as more computing resources become available, they tend to get used on larger problems (larger datasets), and the time spent in the parallelizable part often grows much faster than the inherently serial work. In this case, Gustafson's law gives a less pessimistic and more realistic assessment of the parallel performance.
where
→Slatency is the theoretical speedup of the execution of the whole task;
→s is the speedup of the part of the task that benefits from improved system resources;
→p is the proportion of execution time that the part benefiting from improved resources originally occupied.
Furthermore,
shows that the theoretical speedup of the execution of the whole task increases with the improvement of the resources of the system and that regardless of the magnitude of the improvement, the theoretical speedup is always limited by the part of the task that cannot benefit from the improvement.
→ Amdahl's law applies only to the cases where the problem size is fixed. In practice, as more computing resources become available, they tend to get used on larger problems (larger datasets), and the time spent in the parallelizable part often grows much faster than the inherently serial work. In this case, Gustafson's law gives a less pessimistic and more realistic assessment of the parallel performance.
Question 212 |
The performance of a file system depends upon the cache hit rate. If it takes 1 msec to satisfy a request from the cache but 10 msec to satisfy a request if a disk read is needed, then the mean time (ms) required for a hit rate ‘h’ is given by :
1 | |
h + 10 (1 - h) | |
(1 - h) + 10 h | |
10 |
Question 212 Explanation:
Mean time = (Cache hit rate)*(cache access time) + (cache miss rate)(memory access time)
= Mean time = (h*1)+(1-h)(10)
= Mean time = h+(1-h)(10)
= Mean time = (h*1)+(1-h)(10)
= Mean time = h+(1-h)(10)
Question 213 |
Cache memory is :
High-Speed Register | |
Low-Speed RAM | |
Non-Volatile RAM | |
High-speed RAM
|
Question 213 Explanation:
Option-A is ruled out because it is not register. Registers are more faster than cache memory.
Option-B and D is ruled out because it is not a type RAM.
Option-C is more appropriate answer
Option-C is more appropriate answer
Question 214 |
In 8085 microprocessor which of the following flag(s) is (are) affected by an arithmetic operation ?
AC flag Only | |
CY flag Only | |
Z flag Only | |
AC, CY, Z flags |
Question 214 Explanation:
AC Flag: This flag is set if thee is a carry to fifth bit from the fourth bits if two numbers.
Question 215 |
In 8085 microprocessor the address bus is of __________ bits.
4 | |
8 | |
16 | |
32 |
Question 215 Explanation:
In 8085 microprocessor the address bus is of 16 bits and data bus is 8 bits.
Question 216 |
In the architecture of 8085 microprocessor match the following:
(a)-(iv), (b)-(i), (c)-(ii) | |
(a)-(iii), (b)-(iv), (c)-(ii) | |
(a)-(ii), (b)-(iii), (c)-(i) | |
(a)-(i), (b)-(ii), (c)-(iv) |
Question 216 Explanation:
Processing unit→ ALU
Arithmetic logic unit(ALU) is a fundamental building block of many types of computing circuits, including the central processing unit (CPU) of computers, FPUs, and graphics processing units (GPUs).
Instruction unit →Timing and control
Timing and Control unit is responsible for hardwired control unit and Microprogrammed control unit
Storage and Interface unit → General purpose Register
The general purpose register can store a data (or) a memory location address.
Arithmetic logic unit(ALU) is a fundamental building block of many types of computing circuits, including the central processing unit (CPU) of computers, FPUs, and graphics processing units (GPUs).
Instruction unit →Timing and control
Timing and Control unit is responsible for hardwired control unit and Microprogrammed control unit
Storage and Interface unit → General purpose Register
The general purpose register can store a data (or) a memory location address.
Question 217 |
Which of the following is correct statement ?
In memory - mapped I/O, the CPU can manipulate I/O data residing in interface registers that are not used to manipulate memory words. | |
The isolated I/O method isolates memory and I/O addresses so that memory address range is not affected by interface address assignment. | |
In asynchronous serial transfer of data the two units share a common clock. | |
In synchronous serial transmission of data the two units have different clocks. |
Question 217 Explanation:
FALSE: In memory - mapped I/O, the CPU can manipulate I/O data residing in interface registers that are used to manipulate memory words.
TRUE: The isolated I/O method isolates memory and I/O addresses so that memory address range is not affected by interface address assignment.
FALSE: In asynchronous serial transfer of data the two units share a different clock.
FALSE: In synchronous serial transmission of data the two units have common clocks.
TRUE: The isolated I/O method isolates memory and I/O addresses so that memory address range is not affected by interface address assignment.
FALSE: In asynchronous serial transfer of data the two units share a different clock.
FALSE: In synchronous serial transmission of data the two units have common clocks.
Question 218 |
A microinstruction format has micro-ops field which is divided into three subfields F1, F2, F3 each having seven distinct micro-operations, condition field CD for four status bits, branch field BR having four options used in conjunction with address field ADF. The address space is of 128 memory locations. The size of micro-instruction is:
17 | |
20 | |
24 | |
32 |
Question 218 Explanation:
Given data,
-- Micro-ops field F1 = 7 distinct micro operations
-- Micro-ops field F2 = 7 distinct micro operations
-- Micro-ops field F3 = 7 distinct micro operations
-- Condition field(CD) = 4 status bits
-- Branch Field(BR) = 4 options
-- Address space =128 memory locations
-- Size of micro operation=?
Given microinstruction format
-- Micro-ops field F2 = 7 distinct micro operations
-- Micro-ops field F3 = 7 distinct micro operations
-- Condition field(CD) = 4 status bits
-- Branch Field(BR) = 4 options
-- Address space =128 memory locations
-- Size of micro operation=?
Given microinstruction format
Question 219 |
Which of the following is an interrupt according to temporal relationship with system clock?
Maskable interrupt | |
Periodic interrupt | |
Division by zero | |
Synchronous interrupt |
Question 219 Explanation:
Synchronous interrupts are produced by the CPU control unit while executing instructions and are called synchronous because the control unit issues them only after terminating the execution of an instruction.
This interrupt according to temporal relationship with system clock.
Asynchronous interrupts are generated by other hardware devices at arbitrary times with respect to the CPU clock signals..
Maskable Interrupts - Those interrupts whose request can be denied by microprocessor.
eg- RST 1, RST2, RST 5, RST 6.5 etc..
Non maskable Interrupts - Interrupts whose request cannot be denied. eg -RST 4.5 or TRAP ,RESET IN.
. Periodic interrupts to cause a software task to be executed on a periodic basis.
This interrupt according to temporal relationship with system clock.
Asynchronous interrupts are generated by other hardware devices at arbitrary times with respect to the CPU clock signals..
Maskable Interrupts - Those interrupts whose request can be denied by microprocessor.
eg- RST 1, RST2, RST 5, RST 6.5 etc..
Non maskable Interrupts - Interrupts whose request cannot be denied. eg -RST 4.5 or TRAP ,RESET IN.
. Periodic interrupts to cause a software task to be executed on a periodic basis.
Question 220 |
The general configuration of the micro-programmed control unit is given below:
What are blocks B and C in the diagram respectively?
What are blocks B and C in the diagram respectively?
Block address register and cache memory | |
Control address register and control memory | |
Branch register and cache memory | |
Control address register and random access memory |
Question 220 Explanation:
Question 221 |
Match the following :
a-(iv), b-(iii), c-(i), d-(ii) | |
a-(iv), b-(i), c-(iii), d-(ii) | |
a-(iv), b-(ii), c-(i), d-(iii) | |
a-(iv), b-(iii), c-(ii), d-(i) |
Question 221 Explanation:
Implied → Specified implicitly in the definition of instruction
Immediate→ Registers which are in CPU
Register→ Specified in the register
Register Indirect→ Specified implicitly in the definition of instruction
Immediate→ Registers which are in CPU
Register→ Specified in the register
Register Indirect→ Specified implicitly in the definition of instruction
Question 222 |
In 8085 microprocessor, the digit 5 indicates that the microprocessor needs:
–5 volts, +5 volts supply | |
+5 volts supply only | |
–5 volts supply only | |
5 MHz clock |
Question 222 Explanation:
Before 8085 microprocessors require +5V, -5V and 12V. In 8085 microprocessor need +5 volts supply only.
Question 223 |
In 8085, which of the following performs : load register pair immediate operation?
LDAX rp | |
LHLD addr | |
LXI rp, data | |
INX rp |
Question 223 Explanation:
LDAX: Load accumulator indirect( This instruction copies the contents of that memory location into the accumulator. )
LHLD: Load H and L register direct ( This instruction loads the contents of the 16- bit memory location into the H and L register pair. )
LXI: Load register pair immediate( The instruction loads 16-bit data in the register pair designated in the operand.)
INX: Increment register pair by 1.( It will increment the register value by 1.)
LHLD: Load H and L register direct ( This instruction loads the contents of the 16- bit memory location into the H and L register pair. )
LXI: Load register pair immediate( The instruction loads 16-bit data in the register pair designated in the operand.)
INX: Increment register pair by 1.( It will increment the register value by 1.)
Question 224 |
8085 microprocessor has ____ bit ALU.
32 | |
16 | |
8 | |
4 |
Question 224 Explanation:
8085 microprocessor has 8 bit ALU. It performs arithmetic and logical operations like Addition, Subtraction, AND, OR, etc. on 8-bit data.
Question 225 |
The register that stores the bits required to mask the interrupts is ______.
Status register | |
Interrupt service register | |
Interrupt mask register | |
Interrupt request register |
Question 225 Explanation:
Status register(SR):
→ A status register is a collection of status flag bits for a processor.
→ The status register is a hardware register that contains information about the state of the processor. Individual bits are implicitly or explicitly read and/or written by the machine code instructions executing on the processor.
→ The status register lets an instruction take action contingent on the outcome of a previous instruction.
Interrupt service register(ISR):
→ Interrupt service routine(ISR) is a special block of code associated with a specific interrupt condition.
→ Interrupt handlers are initiated by hardware interrupts, software interrupt instructions, or software exceptions, and are used for implementing device drivers or transitions between protected modes of operation, such as system calls.
Interrupt mask register(IMR):
→ The Interrupt Mask Register is a read and write register.
→ This register enables or masks interrupts from being triggered on the external pins of the Cache Controller.
→ The IMR is used to disable (Mask) or enable (Unmask) individual interrupt request inputs. This is also an 8-bit register.
Interrupt request register(IRR):
→ It stores all the interrupt inputs that are requesting service.
→ It is an 8-bit register, one bit for each interrupt request.
→ It keeps track of which interrupt inputs are asking for service. If an interrupt input is unmasked, and has an interrupt signal on it, then the corresponding bit in the IRR will be set.
→ The content of this register can be read to know the status of pending interrupts.
→ A status register is a collection of status flag bits for a processor.
→ The status register is a hardware register that contains information about the state of the processor. Individual bits are implicitly or explicitly read and/or written by the machine code instructions executing on the processor.
→ The status register lets an instruction take action contingent on the outcome of a previous instruction.
Interrupt service register(ISR):
→ Interrupt service routine(ISR) is a special block of code associated with a specific interrupt condition.
→ Interrupt handlers are initiated by hardware interrupts, software interrupt instructions, or software exceptions, and are used for implementing device drivers or transitions between protected modes of operation, such as system calls.
Interrupt mask register(IMR):
→ The Interrupt Mask Register is a read and write register.
→ This register enables or masks interrupts from being triggered on the external pins of the Cache Controller.
→ The IMR is used to disable (Mask) or enable (Unmask) individual interrupt request inputs. This is also an 8-bit register.
Interrupt request register(IRR):
→ It stores all the interrupt inputs that are requesting service.
→ It is an 8-bit register, one bit for each interrupt request.
→ It keeps track of which interrupt inputs are asking for service. If an interrupt input is unmasked, and has an interrupt signal on it, then the corresponding bit in the IRR will be set.
→ The content of this register can be read to know the status of pending interrupts.
Question 226 |
Which of the following in 8085 microprocessor performs
HL = HL + HL?
HL = HL + HL?
DAD D | |
DAD H | |
DAD B | |
DAD SP |
Question 227 |
In ______ addressing mode, the operands are stored in the memory. The address of the corresponding memory location is given in a register which is specified in the instruction.
Register direct | |
Register indirect | |
Base indexed | |
Displacement |
Question 227 Explanation:
Register indirect: It is specified implicitly in the definition of instruction. Register indirect addressing mode, the operands are stored in the memory. The address of the corresponding memory location is given in a register which is specified in the instruction.
Index mode: The address of the operand is obtained by adding to the contents of the general register (called index register) a constant value. The number of the index register and the constant value are included in the instruction code.
Index mode: The address of the operand is obtained by adding to the contents of the general register (called index register) a constant value. The number of the index register and the constant value are included in the instruction code.
Question 228 |
8085 microprocessor has _____ hardware interrupts.
2 | |
3 | |
4 | |
5 |
Question 228 Explanation:
Question 229 |
Which of the following in 8085 microprocessor performs HL = HL + DE ?
DAD D | |
DAD H | |
DAD B | |
DAD SP |
Question 229 Explanation:
DAD: - Add register pair to HL register. The 16-bit contents of the specified register pair are
added to the contents of the HL register and the sum is stored in the HL register. The contents of the source register pair are not altered. If the result is larger than 16 bits, the CY flag is set. No other flags are affected.
HL = HL + DE means DAD D
HL = HL + DE means DAD D
Question 230 |
The register that stores all interrupt requests is:
Interrupt mask register | |
Interrupt service register | |
Interrupt request register | |
Status register |
Question 230 Explanation:
Status register(SR):
→ A status register is a collection of status flag bits for a processor.
→ The status register is a hardware register that contains information about the state of the processor. Individual bits are implicitly or explicitly read and/or written by the machine code instructions executing on the processor.
→ The status register lets an instruction take action contingent on the outcome of a previous instruction.
Interrupt service register(ISR):
→ Interrupt service routine(ISR) is a special block of code associated with a specific interrupt condition.
→ Interrupt handlers are initiated by hardware interrupts, software interrupt instructions, or software exceptions, and are used for implementing device drivers or transitions between protected modes of operation, such as system calls.
Interrupt mask register(IMR):
→ The Interrupt Mask Register is a read and write register.
→ This register enables or masks interrupts from being triggered on the external pins of the Cache Controller.
→ The IMR is used to disable (Mask) or enable (Unmask) individual interrupt request inputs. This is also an 8-bit register.
Interrupt request register(IRR):
→ It stores all the interrupt inputs that are requesting service.
→ It is an 8-bit register, one bit for each interrupt request.
→ It keeps track of which interrupt inputs are asking for service. If an interrupt input is unmasked, and has an interrupt signal on it, then the corresponding bit in the IRR will be set.
→ The content of this register can be read to know the status of pending interrupts.
→ A status register is a collection of status flag bits for a processor.
→ The status register is a hardware register that contains information about the state of the processor. Individual bits are implicitly or explicitly read and/or written by the machine code instructions executing on the processor.
→ The status register lets an instruction take action contingent on the outcome of a previous instruction.
Interrupt service register(ISR):
→ Interrupt service routine(ISR) is a special block of code associated with a specific interrupt condition.
→ Interrupt handlers are initiated by hardware interrupts, software interrupt instructions, or software exceptions, and are used for implementing device drivers or transitions between protected modes of operation, such as system calls.
Interrupt mask register(IMR):
→ The Interrupt Mask Register is a read and write register.
→ This register enables or masks interrupts from being triggered on the external pins of the Cache Controller.
→ The IMR is used to disable (Mask) or enable (Unmask) individual interrupt request inputs. This is also an 8-bit register.
Interrupt request register(IRR):
→ It stores all the interrupt inputs that are requesting service.
→ It is an 8-bit register, one bit for each interrupt request.
→ It keeps track of which interrupt inputs are asking for service. If an interrupt input is unmasked, and has an interrupt signal on it, then the corresponding bit in the IRR will be set.
→ The content of this register can be read to know the status of pending interrupts.
Question 231 |
The _____ addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction.
Base indexed | |
Base indexed plus displacement | |
Indexed | |
Displacement |
Question 232 |
In _____ method, the word is written to the block in both the cache and main memory, in parallel.
Write through | |
Write back | |
Write protected | |
Direct mapping |
Question 232 Explanation:
→ A cache memory contains copies of data stored in the main memory. When a change of data in a cache takes place (ex. a modification due to a processor write) the contents of the main memory and cache memory cells with the same address, are different. To eliminate this lack of data coherency two methods are applied:
write through, the new cache contents is written down to the main memory immediately after the write to the cache memory,
write back, the new cache contents is not written down to the main memory immediately after the change, but only when the given block of data is replaced by a new block fetched from the main memory or an upper level cache. After a data write to the cache, only state bits are changed in the modified block, indicating that the block has been modified (a dirty block).
The write back updating is more time efficient, since the block cells that were modified many times while being in the cache, are updated in the main memory only once.
write through, the new cache contents is written down to the main memory immediately after the write to the cache memory,
write back, the new cache contents is not written down to the main memory immediately after the change, but only when the given block of data is replaced by a new block fetched from the main memory or an upper level cache. After a data write to the cache, only state bits are changed in the modified block, indicating that the block has been modified (a dirty block).
The write back updating is more time efficient, since the block cells that were modified many times while being in the cache, are updated in the main memory only once.
Question 233 |
What will be the output at PORT1 if the following program is executed ?
MVI B, 82H
MOV A, B
MOV C, A
MVI D, 37H
OUT PORT1
HLT
MVI B, 82H
MOV A, B
MOV C, A
MVI D, 37H
OUT PORT1
HLT
37H | |
82H | |
B9H | |
00H |
Question 233 Explanation:
MOV instruction copies the data from one location to other
MVI B, 82H / Copy value 82H to register B
MOV A, B / Copy value of B (82H) to accumulator A
MOV C, A / Copy value of accumulator A (82H) to register C
MVI D, 37H / Copy value 37H to register D
OUT PORT1 /Copy value of accumulator A (82H) to PORT 1 (because still accumulator A is having 82H)
MVI B, 82H / Copy value 82H to register B
MOV A, B / Copy value of B (82H) to accumulator A
MOV C, A / Copy value of accumulator A (82H) to register C
MVI D, 37H / Copy value 37H to register D
OUT PORT1 /Copy value of accumulator A (82H) to PORT 1 (because still accumulator A is having 82H)
Question 234 |
Which of the following 8085 microprocessor hardware interrupt has the lowest priority?
RST 6.5 | |
RST 7.5 | |
TRAP | |
INTR |
Question 234 Explanation:
DI(Disable Interrupt): DI allows the microprocessor to reject the interrupt. In DI the interrupts are disabled immediately and no flags are affected.
SIM(Set Instruction Mask): It uses flags to disable the interrupts. Here “1” indicated that the interrupt is masked and “0” indicates the the instruction is not masked.
Question 235 |
A DMA controller transfers 32-bit words to memory using cycle stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer?
0.6% | |
0.12% | |
1.2% | |
2.5% |
Question 235 Explanation:
→ In one second, device is sending - 4800 characters to DMA
→ 1 character = 8 bits
→ So in one second, device is sending - (4800⨯8) bits to DMA
→ In one cycle, DMA sends - 32 bits.
→ To send (4800 ⨯ 8) bits DMA needs = (4800⨯8)/30 cycles = 1200 cycles
→ Now in one second CPU executes 106 instructions.
→ But because of cycle stealing, CPU has slow down and the % by which CPU gets slow down can be calculated as
= 1200/106 * 100
= 12/10000 * 100
=0.12%
→ 1 character = 8 bits
→ So in one second, device is sending - (4800⨯8) bits to DMA
→ In one cycle, DMA sends - 32 bits.
→ To send (4800 ⨯ 8) bits DMA needs = (4800⨯8)/30 cycles = 1200 cycles
→ Now in one second CPU executes 106 instructions.
→ But because of cycle stealing, CPU has slow down and the % by which CPU gets slow down can be calculated as
= 1200/106 * 100
= 12/10000 * 100
=0.12%
Question 236 |
A CPU handles interrupt by executing interrupt service subroutine __________.
by checking interrupt register after execution of each instruction | |
by checking interrupt register at the end of the fetch cycle | |
whenever an interrupt is registered | |
by checking interrupt register at regular time interval |
Question 236 Explanation:
CPU after completing the execution of a instruction checks the status of interrupt if there is a interrupt then CPU executes the interrupt service routine to service it else CPU stats executing next instruction.
Question 237 |
In the context of 3D computer graphics, which of the following statements is/are TRUE?
P: Orthographics transformations keep parallel lines parallel
Q: Orthographic transformations are affine transformations
Select the correct answer from the options given below:
P: Orthographics transformations keep parallel lines parallel
Q: Orthographic transformations are affine transformations
Select the correct answer from the options given below:
Both P and Q | |
Neither P and Q | |
Only P | |
Only Q |
Question 238 |
Which type of addressing mode, less number of memory references are required?
Immediate | |
Implied | |
register | |
indexed | |
None of the above |
Question 238 Explanation:
Excluded for evaluation
Question 239 |
Suppose that the register A and register K have the bit configuration. Only the three leftmost bits of A are compared with memory words because K has 1's in these positions. Because of its organization, this type of memory is uniquely suited to parallel seches by data association. This type of memory is known as
RAM | |
ROM | |
Content addressable memory | |
Secondary memory |
Question 239 Explanation:
Content-addressable memory (CAM) is a special type of computer memory used in certain very-high-speed searching applications. It is also known as associative memory or associative storage and compares input search data (tag) against a table of stored data, and returns the address of matching data (or in the case of associative memory, the matching data).
Question 240 |
For a magnetic disk with concentric circular tracks, the seek latency is not linearly proportional to the seek distance due to
Non-Uniform distribution of requests
| |
arm starting or stopping inertia | |
higher capacity of tracks on the periphery of the plate | |
use of unfair arm scheduling policies |
Question 240 Explanation:
For a magnetic disk with concentric circular tracks, the seek latency is not linearly proportional to the seek distance due to arm starting or stopping inertia.
Question 241 |
The fault can be easily diagnosed in the microprogram control unit using diagnostic tools by maintaining the contents of
Flags and Counters
| |
Registers and counters | |
Flags and registers | |
Flags, registers and counters
|
Question 241 Explanation:
The fault can be easily diagnosed in the microprogram control unit using diagnostics tools by maintaining the contents of flags, registers and counters.
Question 242 |
Consider the following statements regarding 2D transforms in computer graphics:
Both S1 and S2 are true | |
Only S1 is true | |
Only S2 is true
| |
Both S1 and S2 are false
|
Question 243 |
Consider a raster system with resolution 640 by 480. What size is frame buffer (in bytes) for this system to store 12 bits per pixel?
450 kilobytes | |
500 Kilobytes | |
350 kilobytes | |
400 kilobytes |
Question 243 Explanation:
8 bits = 1 byte.
A frame-buffer size of the systems are as follows:
= (640 x 480 x 12) bits / 8
= 450KB
A frame-buffer size of the systems are as follows:
= (640 x 480 x 12) bits / 8
= 450KB
Question 244 |
Consider a 32 - bit microprocessor, with a 16 - bit external data bus, driven by an 8 MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate for this microprocessor?
8 × 10 6 bytes/sec | |
4 × 10 6 bytes/sec | |
16 × 10 6 bytes/sec | |
4 × 10 9 bytes/sec |
Question 244 Explanation:
Question 245 |
The RST 7 instruction in 8085 microprocessor is equivalent to:
CALL 0010 H | |
CALL 0034 H | |
CALL 0038 H | |
CALL 003C H |
Question 245 Explanation:
Question 246 |
The CPU of a system having 1 MIPS execution rate needs 4 machine cycles on an average for executing an instruction. The fifty percent of the cycles use memory bus. A memory read/ write employs one machine cycle. For execution of the programs, the system utilizes 90 percent of the CPU time. For block data transfer, an IO device is attached to the system while CPU executes the
background programs continuously. What is the maximum IO data transfer rate if programmed IO data transfer technique is used?
500 Kbytes/sec | |
2.2 Mbytes/sec | |
125 Kbytes/sec | |
250 Kbytes/sec |
Question 246 Explanation:
Given, CPU speed 10 6 instruction/sec
1 CPU instruction = 4 machine cycles
CPU utilization = 90%
Programmed IO: each byte transfer requires 4 cycles (instructions), in status, check status branch, R/W data in memory maximum data transfer rate,
1 CPU instruction = 4 machine cycles
CPU utilization = 90%
Programmed IO: each byte transfer requires 4 cycles (instructions), in status, check status branch, R/W data in memory maximum data transfer rate,
Question 247 |
Which of the following is not a basic primitive of the Graphics Kernel System (GKS)?
POLYLINE | |
POLYDRAW | |
FILL AREA | |
POLYMARKER |
Question 247 Explanation:
Graphics Kernel System (GKS): GKS provides a set of drawing
features for two-dimensional vector graphics suitable for charting and similar duties. The calls are designed to be portable across different programming languages, graphics devices and hardware, so that applications written to use GKS will be readily portable to many platforms and devices.
The five main primitives in GKs are :
● Polyline: which draws a sequence of connected line segments.
● Fill Area: which displays a specified area.
● Cell array: which displays an image composed of a variety of colours or grey scales.
● Polymarker: which marks a sequence of points with the same symbol.
● Text: which draws a string of characters
The five main primitives in GKs are :
● Polyline: which draws a sequence of connected line segments.
● Fill Area: which displays a specified area.
● Cell array: which displays an image composed of a variety of colours or grey scales.
● Polymarker: which marks a sequence of points with the same symbol.
● Text: which draws a string of characters
Question 248 |
(a)-(iii), (b)-(i), (c)-(ii), (d)-(iv) | |
(a)-(iii), (b)-(i), (c)-(iv), (d)-(ii) | |
(a)-(iv), (b)-(iii), (c)-(ii), (d)-(i) | |
(a)-(ii), (b)-(iii), (c)-(iv), (d)-(i) |
Question 248 Explanation:
Spooling→ Overlapping I/O and computations
Multiprogramming → Allows several jobs in memory to improve CPU utilization
Time Sharing→ Allows many users to share a computer simultaneously by switching processor frequently
Distributed Computing→ Access to shared resources among geographically dispersed computers in a transparent way
Multiprogramming → Allows several jobs in memory to improve CPU utilization
Time Sharing→ Allows many users to share a computer simultaneously by switching processor frequently
Distributed Computing→ Access to shared resources among geographically dispersed computers in a transparent way
Question 249 |
The redundancy in images stems from:
pixel decorrelation | |
pixel correlation | |
pixel quantization | |
image size |
Question 249 Explanation:
The redundancy in images stems from pixel correlation
Question 250 |
A Non-pipelined system takes 30ns to process a task. The same task can be processed in a four-segment pipeline with a clock cycle of 10ns. Determine the speed up of the pipeline for 100 tasks
3 | |
4 | |
3.91 | |
2.91 |
Question 250 Explanation:
S=ntn / (n+k-1)tp
= 100*30/(100+4-1)*10
= 3000 / 1030
= 2.91
= 100*30/(100+4-1)*10
= 3000 / 1030
= 2.91
Question 251 |
The reduced Instruction Set Computer (RISC) characteristics are:
(a) Single cycle instruction execution
(b) Variable length instruction formats
(c) Instructions that manipulates operands in memory
(d) Efficient instruction pipeline
Choose the correct characteristics from the options given below:
(a) Single cycle instruction execution
(b) Variable length instruction formats
(c) Instructions that manipulates operands in memory
(d) Efficient instruction pipeline
Choose the correct characteristics from the options given below:
(a) and (b) | |
(b) and (c) | |
(a) and (d) | |
(c) and (d) |
Question 251 Explanation:
Common RISC characteristics
→ Load/store architecture (also called register-register or RR architecture) which fetches operands and results indirectly from main memory through a lot of scalar registers. Other architecture is storage-storage or SS in which source operands and final results are retrieved directly from memory.
→ Fixed length instructions which (a) are easier to decode than variable length instructions, and (b) use fast, inexpensive memory to execute a larger piece of code. → Hardwired controller instructions (as opposed to microcoded instructions). This is where RISC really shines as hardware implementation of instructions is much faster and uses less silicon real estate than a microstore area.
→ Fused or compound instructions which are heavily optimized for the most commonly used functions.
→ Pipelined implementations with the goal of executing one instruction (or more) per machine cycle.
→ Large uniform register set
→ Minimal number of addressing modes
→ no/minimal support for misaligned accesses
Characteristic of CISC:
→ Complex instruction, hence complex instruction decoding.
→ Instruction are larger than one word size.
→ Instruction may take more than a single clock cycle to get executed.
→ Less number of general purpose register as operation get performed in memory itself.
→ Complex Addressing Modes.
→ More Data types.
→ Load/store architecture (also called register-register or RR architecture) which fetches operands and results indirectly from main memory through a lot of scalar registers. Other architecture is storage-storage or SS in which source operands and final results are retrieved directly from memory.
→ Fixed length instructions which (a) are easier to decode than variable length instructions, and (b) use fast, inexpensive memory to execute a larger piece of code. → Hardwired controller instructions (as opposed to microcoded instructions). This is where RISC really shines as hardware implementation of instructions is much faster and uses less silicon real estate than a microstore area.
→ Fused or compound instructions which are heavily optimized for the most commonly used functions.
→ Pipelined implementations with the goal of executing one instruction (or more) per machine cycle.
→ Large uniform register set
→ Minimal number of addressing modes
→ no/minimal support for misaligned accesses
Characteristic of CISC:
→ Complex instruction, hence complex instruction decoding.
→ Instruction are larger than one word size.
→ Instruction may take more than a single clock cycle to get executed.
→ Less number of general purpose register as operation get performed in memory itself.
→ Complex Addressing Modes.
→ More Data types.
Question 252 |
A microinstruction format has microoperation field which is divided into 2 subfields F1 and F2. Each having 15 distinct micro operations condition field CD for four status bits. Branch field BR having four options used in conjunction with address field AD. The address space is of 128 memory words. The size of micro instruction is
19 | |
18 | |
17 | |
20 |
Question 253 |
A computer uses a memory unit of 512 K words of 32 bits each. A binary instruction code is stored in one word of the memory. The instruction has four parts: an addressing mode field to specify one of the two-addressing mode (direct and indirect), an operation code, a register code part to specify one of the 256 registers and an address part. How many bits are there in addressing mode part, opcode part, register code part and the address part?
1, 3, 9, 19 | |
1, 4, 9, 18 | |
1, 4, 8, 19 | |
1, 8, 8, 20 |
Question 253 Explanation:
Given data,
Memory unit= 512K words
512K words of 32 bits each.
Binary instruction code stored in 1 word of memory.
Instruction divided into 4 parts.
1. Operation code= ?
2. Register code= ?
3. Addressing mode (Direct and indirect)
4. Address port= ?
Addressing Mode part = 1 (Direct and indirect)
Operation Code = 32 - 1 - 18 - 8 bits = 5 bits
Register Code = 256 = 28 = 8 bits
Address port = 28 (256kB) * 210 (1024 bytes/kB) = 218 ⇒ 18 bits
final Answer is (1,5,8,18)
Note: None of the options given correct answer. We are given answer according to key given by NTA.
Memory unit= 512K words
512K words of 32 bits each.
Binary instruction code stored in 1 word of memory.
Instruction divided into 4 parts.
1. Operation code= ?
2. Register code= ?
3. Addressing mode (Direct and indirect)
4. Address port= ?
Addressing Mode part = 1 (Direct and indirect)
Operation Code = 32 - 1 - 18 - 8 bits = 5 bits
Register Code = 256 = 28 = 8 bits
Address port = 28 (256kB) * 210 (1024 bytes/kB) = 218 ⇒ 18 bits
final Answer is (1,5,8,18)
Note: None of the options given correct answer. We are given answer according to key given by NTA.
Question 254 |
Match List-I and List-II:
Choose the correct option from those given below:
(a)-(ii), (b)-(iii), (c)-(iv), (d)-(i) | |
(a)-(i), (b)-(ii), (c)-(iii), (d)-(iv) | |
(a)-(ii), (b)-(i), (c)-(iv), (d)-(iii) | |
(a)-(i), (b)-(ii), (c)-(iv), (d)-(iii) |
Question 254 Explanation:
Isolated I/O → Separate instructions for I/O and memory communication
Memory mapped I/O → Same set of control signal for I/O and memory communication
I/O interface → Resolve the differences in central computer and peripherals
Asynchronous data transfer → Requires control signals to be transmitted between the communicating units
Question 255 |
An instruction is stored at location 500 with it address field at location 501. The address field has the value 400. A processor register R1 contains the number 200. Match the addressing mode (List-I) given below with effective address (List-II) for the given instruction:
Choose the correct option from those given below:
(a)-(iii), (b)-(i), (c)-(iv), (d)-(ii) | |
(a)-(i), (b)-(ii), (c)-(iii), (d)-(iv) | |
(a)-(iv), (b)-(ii), (c)-(iii), (d)-(i) | |
(a)-(iv), (b)-(iii), (c)-(ii), (d)-(i) |
Question 255 Explanation:
Direct Address = 400
Relative Address = Next Instruction memory location + Direct Address value
= 502 + 400
= 902
Register indirect Address= 200
Indexed Address = Register Indirect Address + Direct Address
= 200 + 400
= 600
Question 256 |
(a)-(iv), (b)-(iii), (c)-(ii), (d)-(i) | |
(a)-(iv), (b).(iii), (c)-(i), (d)-(ii) | |
(a)-(iii), (b)-(iv), (c)-(i), (d)-(i) | |
(a)-(iii), (b)-(iv), (c)-(ii), (d)-(i) |
Question 256 Explanation:
Micro operation → Elementary operation performed on data stored in registers
Micro programmed control unit → Control Memory
Interrupts → Improve CPU utilization
Micro instruction→ Specify micro operations
Micro programmed control unit → Control Memory
Interrupts → Improve CPU utilization
Micro instruction→ Specify micro operations
Question 257 |
Which of the following addressing modes is more appropriate for accessing elements of an array?
Index mode | |
Auto increment mode | |
Displacement mode | |
Register mode |
Question 257 Explanation:
→The address of the operand is obtained by adding to the contents of the general register (called index register) a constant value.
→The number of the index register and the constant value are included in the instruction code.
→Index Mode is used to access an array whose elements are in successive memory locations. The content of the instruction code, represents the starting address of the array and the value of the index register, and the index value of the current element.
→By incrementing or decrementing index register different element of the array can be accessed.
→The number of the index register and the constant value are included in the instruction code.
→Index Mode is used to access an array whose elements are in successive memory locations. The content of the instruction code, represents the starting address of the array and the value of the index register, and the index value of the current element.
→By incrementing or decrementing index register different element of the array can be accessed.
Question 258 |
Which of the following statements related to Cache memory organization is FALSE?
In "write through" approach. main memory content is always invalid. | |
In "write back" approach, updates are made only in the cache and it minimizes memory writes. | |
Least Recently Used (LRU) replacement algorithm can be used in associative and set associative mappings.
| |
For direct mapping, no replacement algorithm is needed. |
Question 258 Explanation:
→Write through is a storage method in which data is written into the cache and the corresponding main memory location at the same time.
→The cached data allows for fast retrieval on demand, while the same data in main memory ensures that nothing will get lost if a crash, power failure, or other system disruption occurs.
→The cached data allows for fast retrieval on demand, while the same data in main memory ensures that nothing will get lost if a crash, power failure, or other system disruption occurs.
Question 259 |
Match the following.
I-B,II-C,III-D,IV-A | |
I-C,II-B,III-D,IV-A | |
I-A,II-D,III-B,IV-C | |
I-B,II-A,III-D,IV-C |
Question 259 Explanation:
The standard RAID levels comprise a basic set of RAID (redundant array of independent disks) configurations that employ the techniques of striping, mirroring, or parity to create large reliable data stores from multiple general-purpose computer hard disk drives (HDDs). The most common types are RAID 0 (striping), RAID 1 (mirroring) and its variants, RAID 5 (distributed parity), and RAID 6 (dual parity).
RAID levels and their associated data formats are standardized by the Storage Networking Industry Association (SNIA) in the Common RAID Disk Drive Format (DDF) standard
RAID levels and their associated data formats are standardized by the Storage Networking Industry Association (SNIA) in the Common RAID Disk Drive Format (DDF) standard
Question 260 |
If the address of the operand is embedded in the instruction code itself, then the addressing mode is termed as:
Register mode | |
Direct mode | |
Displacement mode | |
Immediate mode |
Question 260 Explanation:
In direct mode, the effective address of operand is present in the instruction itself.
Single memory reference to access data.
No additional calculations to find the effective address of the operand.
Single memory reference to access data.
No additional calculations to find the effective address of the operand.
Question 261 |
Interrupt generated due to which of the following operations does not belong to program-related interrupt category?
Division by zero | |
Attempt to execute an illegal machine instruction | |
Memory parity error | |
Reference outside a user’s allowed memory space |
Question 261 Explanation:
Memory parity errors can be caused by failing hardware or outside elements disrupting how computer memory functions.
Fixing parity errors involves removing the outside cause or failing hardware.
A memory parity error means that one or more stored data values carries a different value when it's recalled than when it was stored.
According to Cisco, parity errors are a type of data corruption.
Parity errors offset the charge value and can bring back invalid or incorrect commands for the computer.
Fixing parity errors involves removing the outside cause or failing hardware.
A memory parity error means that one or more stored data values carries a different value when it's recalled than when it was stored.
According to Cisco, parity errors are a type of data corruption.
Parity errors offset the charge value and can bring back invalid or incorrect commands for the computer.
Question 262 |
Consider a cache memory organization with m lines in which the cache is divided into v sets, each of which consists of k lines. The set associative mapping technique reduces to direct mapping when:
v=m and k=m | |
v=1 and k=m | |
v=m and k=1 | |
v=1 and k=1 |
Question 262 Explanation:
Question 263 |
A non-pipelined CPU has 12 general purpose registers(R0, R1, R2,........R12). Following operations are supported
ADD Ra, Rb, Rr Add Ra to Rb and store the result in Rr
MUL Ra, Rb, Rr Multiply Ra to Rb and store the result in Rr
MUL operations takes two clock cycles, ADD takes one clock cycle.
Calculate the minimum number of clock cycles required to compute the value of the expression XY+XYZ+YZ. The variables X, Y, Z are initially available in registers R0, R1 and R2 contents of these registers must not be modified.
ADD Ra, Rb, Rr Add Ra to Rb and store the result in Rr
MUL Ra, Rb, Rr Multiply Ra to Rb and store the result in Rr
MUL operations takes two clock cycles, ADD takes one clock cycle.
Calculate the minimum number of clock cycles required to compute the value of the expression XY+XYZ+YZ. The variables X, Y, Z are initially available in registers R0, R1 and R2 contents of these registers must not be modified.
5 | |
6 | |
7 | |
8 |
Question 263 Explanation:
To calculate XY+XYZ+YZ, we need at least 3 multiplication operations and 2 ADD operations.
Assuming R0 = X, R1 = Y, R2 = Z.
MUL R3, R0, R1
MUL R4, R3, R2
ADD R5, R4, R3
MUL R6, R1, R2
ADD R7, R5, R6
Total we need 3 multiplication operations and 2 add operations.
Total cycles needed = 3*2+2 = 8
Assuming R0 = X, R1 = Y, R2 = Z.
MUL R3, R0, R1
MUL R4, R3, R2
ADD R5, R4, R3
MUL R6, R1, R2
ADD R7, R5, R6
Total we need 3 multiplication operations and 2 add operations.
Total cycles needed = 3*2+2 = 8
Question 264 |
One instruction tries to write an operand before it is written by previous instruction. This may lead to a dependency called
True dependency | |
Anti dependency | |
Output dependency | |
Control hazard |
Question 264 Explanation:
When two instructions are updating an operand and if the ordering of the instructions changes the output this is nothing but Write After Write (WAW) dependency..which is also called output dependency.
Question 265 |
The immediate addressing mode can be used for
1. Loading internal registers with initial values
2. Perform arithmetic or logical operations on data contained in instructions Which of the following is true?
1. Loading internal registers with initial values
2. Perform arithmetic or logical operations on data contained in instructions Which of the following is true?
Only 1 | |
Only 2 | |
Both 1 and 2 | |
Immediate mode refers to data in cache |
Question 265 Explanation:
Immediate addressing mode can be used for both loading registers with initial values and for performing arithmetic or logical operations on data contained in instructions.
Question 266 |
Statement associated with registers of a CPU are given. Identify the false statement
The program counter holds the memory address of the instruction in execution | |
Only opcode is transferred to the control unit | |
An instruction in the instruction register consists of the opcode and the operand | |
The value of the counter is incremented by 1 once its value has been read to the memory address register |
Question 266 Explanation:
Program counter always holds the address of the next instruction, not the current instruction in execution. Hence the statement in option A is false.
Question 267 |
Which of the following affects the processing power assuming they do not influence each other.
Data bus capability
Addressing scheme
Clock speed
Data bus capability
Addressing scheme
Clock speed
3 only | |
1 and 3 only | |
2 and 3 only | |
1, 2 and 3 |
Question 267 Explanation:
"Though different addressing schemes take different amount of execution times that will not affect the processing power. So, out of the given components only data bus capability and clock speed affect the processing power."
Question 268 |
Consider a 5-segment pipeline with a clock cycle time 20ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute 100 instructions. (if an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline)
5 | |
4.03 | |
4.81 | |
4.17 |
Question 268 Explanation:
A 5 segment pipeline with clock cycle time of 20ns.
Time without pipeline for one instruction = 5*20 = 100ns.
For 100 instructions time without pipeline = 100*100ns = 10^4 ns.
With pipeline, it is given that on average for every 5 cycles there is one bubble or stall cycle which is introduced. So stall frequency = ⅕.
In general in a pipeline we have clocks per instruction CPI = 1. But when there are stall cycles, the updated CPI = (1 + stall frequency * no. of stall cycles) = (1+⅕*1) = 1.2
Execution time with the pipeline = no. of instructions * CPI * clock cycle time.
= 100 * 1.2 * 20 = 2400ns
Speed up = Time without pipeline / Time with pipeline
= 10^4 / 2400 = 100/24 = 4.17
Time without pipeline for one instruction = 5*20 = 100ns.
For 100 instructions time without pipeline = 100*100ns = 10^4 ns.
With pipeline, it is given that on average for every 5 cycles there is one bubble or stall cycle which is introduced. So stall frequency = ⅕.
In general in a pipeline we have clocks per instruction CPI = 1. But when there are stall cycles, the updated CPI = (1 + stall frequency * no. of stall cycles) = (1+⅕*1) = 1.2
Execution time with the pipeline = no. of instructions * CPI * clock cycle time.
= 100 * 1.2 * 20 = 2400ns
Speed up = Time without pipeline / Time with pipeline
= 10^4 / 2400 = 100/24 = 4.17
Question 269 |
Consider a 32-bit processor which supports 70 instructions. Each instruction is 32 bit long and has 4 fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is 8191. How many registers the processor has?
32 | |
64 | |
128 | |
16 |
Question 269 Explanation:
Given that each instruction is 32 bit long and it has 4 fields.
As there are 70 instructions, each opcode needs 7 bits as ceil(log70) = 7.
It is given that maximum value of the immediate operand is 8191.
Number of bits needed for the immediate operand = ceil(log8191) = 13.
Out of the total 32 bits, remaining bits for the two register identifiers = 32 - 7 - 13 = 32 - 20 = 12
These 12 bits are equally divided to identify the two registers. So to identify each register we need 6 bits. So there are a total of 2^6 = 64 registers.
As there are 70 instructions, each opcode needs 7 bits as ceil(log70) = 7.
It is given that maximum value of the immediate operand is 8191.
Number of bits needed for the immediate operand = ceil(log8191) = 13.
Out of the total 32 bits, remaining bits for the two register identifiers = 32 - 7 - 13 = 32 - 20 = 12
These 12 bits are equally divided to identify the two registers. So to identify each register we need 6 bits. So there are a total of 2^6 = 64 registers.
Question 270 |
A stack organised computer is characterised by instructions with
Indirect addressing | |
Direct addressing | |
Zero addressing | |
Index addressing |
Question 270 Explanation:
A stack organized computer is characterized by zero address instructions which will perform operations on the top elements of the stack.
For example ADD will do addition of top two elements of the stack and puts the result as the top most element.
For example ADD will do addition of top two elements of the stack and puts the result as the top most element.
Question 271 |
A computer which issues instructions in order, has only 2 registers and 3 opcodes ADD, SUB and MOV. Consider 2 different implementations of the following basic block:
Case 1 Case 2
t1=a+b; t2=c+d;
t2=c+d; t3=e-t2;
t3=e-t2; t1=a+b;
t4=t1-t2; t4=t1-t2;
Assume that all operands are initially in memory . Final value of computation also has to reside in memory. Which one is better in terms of memory accesses and by how many MOV instructions?
Case 1 Case 2
t1=a+b; t2=c+d;
t2=c+d; t3=e-t2;
t3=e-t2; t1=a+b;
t4=t1-t2; t4=t1-t2;
Assume that all operands are initially in memory . Final value of computation also has to reside in memory. Which one is better in terms of memory accesses and by how many MOV instructions?
Case 2,2 | |
Case 2,3 | |
Case 1,2 | |
Case 1,3 | |
None of the above |
Question 271 Explanation:
Case-1 is better by Case-2 by One more operation.
None of the answers are correct
Question 272 |
Which of the following is an efficient method of cache updating?Snoopy writes
Snoopy writes | |
Write through | |
Write within | |
Buffered write |
Question 272 Explanation:
There is no policy which is called as the write within policy. The other three options are the write policies which are used to avoid cache coherence.
Question 273 |
A magnetic disk has 100 cylinders, each with 10 tracks of 10 sector. If each sector contains 128 bytes, what is the maximum capacity of the disk in kilobytes?
1,280,000 | |
1280 | |
1250 | |
128,000 |
Question 273 Explanation:
There are 100 cylinders, each with 10 tracks, and 10 sectors. Each sector is 128 bytes.
Maximum capacity of the disk = 100*10*10*128 bytes
= 10^4 * 128 bytes
= (128*10^4 / 1024) KB
= (10^4/ 8) = 1250 KB
Maximum capacity of the disk = 100*10*10*128 bytes
= 10^4 * 128 bytes
= (128*10^4 / 1024) KB
= (10^4/ 8) = 1250 KB
Question 274 |
How many total bits are required for a direct-mapped cache with 128 KB of data and 1 word block size, assuming a 32-bit address and 1 word size of 4 bytes?
2 Mbits | |
1.7 Mbits | |
2.5 Mbits | |
1.5 Mbits |
Question 274 Explanation:
Size of a cache line = block size = 4 bytes
Number of lines in the cache = cache size / line size = 128KB / 4 bytes = 32K = 2^15
In a direct mapped cache the address is split into 3 fields (TAG, LINE, OFFSET)
Here OFFSET is the number bits needed to identify a word within the cache line.
As line size = word size, we don’t need any bits to identify the word within a block so OFFSET = 0.
As there are 2^15 lines in the cache, LINE needs 15 bits. From the 32 bits of physical address, TAG bits = 32 - 15 = 17 bits. TAG directory size = Number of cache lines * TAG bits = 2^15 * 17 = 544 K bits Cache data size = 128KB = 128 * 8 K bits = 1024 K bits Total cache size = TAG directory size + cache data size = 544 K + 1024 K = 1564 K bits = 1.53 M bits
Number of lines in the cache = cache size / line size = 128KB / 4 bytes = 32K = 2^15
In a direct mapped cache the address is split into 3 fields (TAG, LINE, OFFSET)
Here OFFSET is the number bits needed to identify a word within the cache line.
As line size = word size, we don’t need any bits to identify the word within a block so OFFSET = 0.
As there are 2^15 lines in the cache, LINE needs 15 bits. From the 32 bits of physical address, TAG bits = 32 - 15 = 17 bits. TAG directory size = Number of cache lines * TAG bits = 2^15 * 17 = 544 K bits Cache data size = 128KB = 128 * 8 K bits = 1024 K bits Total cache size = TAG directory size + cache data size = 544 K + 1024 K = 1564 K bits = 1.53 M bits
There are 274 questions to complete.