The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A₁₅ to A₀. What is the range of addresses (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?

A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor?

A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a 60-MHz clock. To service a cache miss, the memory controller first takes 1 cycle to accept the starting address of the block, it then takes 3 cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of 1 word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is ______ × 10⁶ bytes/sec.

A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M × 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2¹⁴. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is _________.

The following are some events that occur after a device controller issues an interrupt while process L is under execution.

• (P) The processor pushes the process status of L onto the control stack.

• (Q) The processor finishes the execution of the current instruction.

• (R) The processor executes the interrupt service routine.

• (S) The processor pops the process status of L from the control stack.

(T) The processor loads the new PC value based on the interrupt.

Consider the following processor design characteristics.

• I. Register-to-register arithmetic operations only

• II. Fixed-length instruction format

III. Hardwired control unit

Which of the characteristics above are used in the design of a RISC processor?

The size of the physical address space of a processor is 2^P bytes. The word length is 2^W bytes. The capacity of cache memory is 2^N bytes. The size of each cache block is 2^M words. For a K-way set-associative cache memory, the length (in number of bits) of the tag field is

A processor has 16 integer registers (R0, R1, …, R15) and 64 floating point registers (F0, F1, …, F63). It uses a 2-byte instruction format. There are four categories of instructions: Type-1, Type-2, Type-3 and Type-4. Type-1 category consists of four instructions, each with 3 integer register operands (3Rs). Type-2 category consists of eight instructions, each with 2 floating point register operands (2Fs). Type-3 category consists of fourteen instructions, each with one integer register operand and one floating point register operand (1R+1F). Type-4 category consists of N instructions, each with a floating point register operand (1F).

The maximum value of N is ________.

The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards.

The number of clock cycles required for completion of execution of the sequence of instructions is ___________.

Consider the C struct defined below:

    struct data   {
        int marks [100];
        char grade;
        int cnumber;
    };
    struct data student;

The base address of student is available in register R1. The field student.grade can be accessed efficiently using

Consider a two-level cache hierarchy with L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache is 0.1; the L2 cache experiences, on average, 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is __________.

Consider a RISC machine where each instruction is exactly 4 bytes long. Conditional and unconditional branch instructions use PC-relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Further the Offset is always with respect to the address of the next instruction in the program sequence. Consider the following instruction sequence

If the target of the branch instruction is i, then the decimal value of the Offset is ___________.

Instruction execution in a processor is divided into 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10 and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns. Two pipelined implementations of the processor are contemplated:

1. (i) a naive pipeline implementation (NP) with 5 stages and

1. (ii) an efficient pipeline (EP) where the OF stage is divided into stages OF1 and OF2 with execution times of

1. and

respectively.

The speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards is _________.

Consider a 2-way set associative cache with 256 blocks and uses LRU replacement. Initially the cache is empty. Conflict misses are those misses which occur due to contention of multiple blocks for the same cache set. Compulsory misses occur due to first time access to the block. The following sequence of accesses to memory blocks

is repeated 10 times. The number of conflict misses experienced by the cache is __________.

A cache memory unit with capacity of N words and block size of B words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ___________ bits.

In a two-level cache system, the access times of L₁ and L₂ caches are 1 and 8 clock cycles, respectively. The miss penalty from the L₂ cache to main memory is 18 clock cycles. The miss rate of L₁ cache is twice that of L₂. The average memory access time (AMAT) of this cache system is 2 cycles. The miss rates of L₁ and L₂ respectively are:

The read access times and the hit ratios for different caches in a memory hierarchy are as given below.

The read access time of main memory is 90 nanoseconds. Assume that the caches use the referred-word-first read policy and the write back policy. Assume that all the caches are direct mapped caches. Assume that the dirty bit is always 0 for all the blocks in the caches. In execution of a program, 60% of memory reads are for instruction fetch and 40% are for memory operand fetch. The average read access time in nanoseconds (up to 2 decimal places) is ___________.

Consider a machine with a byte addressable main memory of 2³² bytes divided into blocks of size 32 bytes. Assume that a direct mapped cache having 512 cache lines is used with this machine. The size of the tag field in bits is _____________.

A processor can support a maximum memory of 4GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least _________ bits.

The size of the data count register of a DMA controller is 16 bits. The processor needs to transfer a file of 29,154 kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is ________.

The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. The throughput increase of the pipeline is ________ percent.

A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit instruction word has an opcode, two register operands and an immediate operand. The number of bits available for the immediate operand field is __________.

Suppose the functions F and G can be computed in 5 and 3 nanoseconds by functional units U_F and U_G, respectively. Given two instances of U_F and two instances of U_G, it is required to implement the computation F(G(X_i)) for 1 ≤ i ≤ 10. Ignoring all other delays, the minimum time required to complete this computation is _________ nanoseconds.

Consider a processor with 64 registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register r identifier, and a twelve-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. If a program has 100 instructions, the amount of memory (in bytes) consumed by the program text is _________.

The width of the physical address on a machine is 40 bits. The width of the tag field in a 512 KB 8-way set associative cache is _________ bits.

Consider a 3 GHz (gigahertz) processor with a three-stage pipeline and stage latencies τ₁, τ₂, τ₃ and such that τ₁  = 3τ₂/4 = 2τ₃. If the longest pipeline stage is split into two pipeline stages of equal latency, the new frequency is _________ GHz, ignoring delays in the pipeline registers.

A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The latency to read a block from the cache is 1 ms and to read a block from the disk is 10 ms. Assume that the cost of checking whether a block exists in the cache is negligible. Available cache sizes are in multiples of 10 MB.

The smallest cache size required to ensure an average read latency of less than 6 ms is _______ MB.

For computers based on three-address instruction formats, each address field can be used to specify which of the following:

(S1) A memory operand
(S2) A processor register
(S3) An implied accumulator register

Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is __________.

Consider a disk pack with a seek time of 4 milliseconds and rotational speed of 10000 rotations per minute (RPM). It has 600 sectors per track and each sector can store 512 bytes of data. Consider a file stored in the disk. The file contains 2000 sectors. Assume that every sector access necessitates a seek, and the average rotational latency for accessing each sector is half of the time for one complete rotation. The total time (in milliseconds) needed to read the entire file is _________.

Assume that for a certain processor, a read request takes 50 nanoseconds on a cache miss and 5 nanoseconds on a cache hit. Suppose while running a program, it was observed that 80% of the processors read requests result in a cache hit. The average and access time in nanoseconds is  _______.

Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the main memory is implemented from memory location (0100)₁₆ and it grows upward. The stack pointer (SP) points to the top element of the stack. The current value of SP is (016E)₁₆. The CALL instruction is of two words, the first word is the op-code and the second word is the starting address of the subroutine (one word = 2 bytes). The CALL instruction is implemented as follows:

• Store the current value of PC in the stack.
• Store the value of PSW register in the stack.
• Load the starting address of the subroutine in PC.

The content of PC just before the fetch of a CALL instruction is (5FA0)₁₆. After execution of the CALL instruction, the value of the stack pointer is

Consider the sequence of machine instructions given below:

  MUL R5, R0, R1
  DIV R6, R2, R3
  ADD R7, R5, R6
  SUB R8, R7, R4 

In the above sequence, R0 to R8 are general purpose registers. In the instructions shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode (IF), (2) Operand Fetch (OF), (3) Perform Operation (PO) and (4) Write back the Result (WB). The IF, OF and WB stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD or SUB instruction, 3 clock cycles for MUL instruction and 5 clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instructions is

Consider the following reservation table for a pipeline having three stages S1, S2 and S3.

     Time -->
-----------------------------
      1    2   3    4     5
-----------------------------
S1  | X  |   |   |    |  X |    
S2  |    | X |   | X  |    |
S3  |    |   | X |    |    |

The minimum average latency (MAL) is ________.

Consider the following code sequence having five instructions I1 to I5. Each of these instructions has the following format.

     
          OP Ri, Rj, Rk 

where operation OP is performed on contents of registers Rj and Rk and the result is stored in register Ri.

     
          I1 : ADD R1, R2, R3
          I2 : MUL R7, R1, R3
          I3 : SUB R4, R1, R5
          I4 : ADD R3, R2, R4
          I5 : MUL R7, R8, R9 

Consider the following three statements:

     
          S1: There is an anti-dependence between instructions I2 and I5.
          S2: There is an anti-dependence between instructions I2 and I4.
          S3: Within an instruction pipeline an anti-dependence always creates one or more stalls. 

Which one of above statements is/are correct?

A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ________.

Consider two processors P₁ and P₂ executing the same instruction set. Assume that under identical conditions, for the same input, a program running on P₂ takes 25% less time but incurs 20% more CPI (clock cycles per instruction) as compared to the program running on P₁. If the clock frequency of P₁ is 1GHz, then the clock frequency of P₂ (in GHz) is _________.

A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address space is 4 GB. The number of bits for the TAG field is __________.

Suppose a stack implementation supports an instruction REVERSE, which reverses the order of elements on the stack, in addition to the PUSH and POP instructions. Which one of the following statements is TRUE with respect to this modified stack?

In designing a computer’s cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?

If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?

The value of a float type variable is represented using the single-precision 32-bit floating point format of IEEE-754 standard that uses 1 bit for sign, 8 bits for biased exponent and 23 bits for mantissa. A float type variable X is assigned the decimal value of −14.25. The representation of X in hexadecimal notation is

Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for 100 nanoseconds (ns) by the data, address, and control signals. During the same 100 ns, and for 500 ns thereafter, the addressed memory module executes one cycle accepting and storing the data. The (internal) operation of different memory modules may overlap in time, but only one request can be on the bus at any time. The maximum number of stores (of one word each) that can be initiated in 1 millisecond is ____________.

Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency.

P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns.
P2: Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns.
P3: Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns.
P4: Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 ns.

Which processor has the highest peak clock frequency?

An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies 1 ns, 2.2 ns, 2 ns, 1 ns, and 0.75 ns, respectively (ns stands for nanoseconds). To gain in terms of frequency, the designers have decided to split the ID/RF stage into three stages (ID, RF1, RF2) each of latency 2.2/3 ns. Also, the EX stage is split into two stages (EX1, EX2) each of latency 1 ns. The new design has a total of eight pipeline stages. A program has 20% branch instructions which execute in the EX stage and produce the next instruction pointer at the end of the EX stage in the old design and at the end of the EX2 stage in the new design. The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed. All instructions other than the branch instruction have an average CPI of one in both the designs. The execution times of this program on the old and the new design are P and Q nanoseconds, respectively. The value of P/Q is __________.

In a k-way set associative cache, the cache is divided into v sets, each of which consists of k lines. The lines of a set are placed in sequence one after another. The lines in set s are sequenced before the lines in set (s+1). The main memory blocks are numbered 0 onwards. The main memory block numbered j must be mapped to any one of the cache lines from

Consider the following sequence of micro-operations.

     MBR ← PC 
     MAR ← X  
     PC ← Y  
     Memory ← MBR

Which one of the following is a possible operation performed by this sequence?

A RAM chip has a capacity of 1024 words of 8 bits each (1K×8). The number of 2×4 decoders with enable line needed to construct a 16K×16 RAM from 1K×8 RAM is

Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I₁, I₂, I₃, ..., I₁₂ is executed in this pipelined processor. Instruction I₄ is the only branch instruction and its branch target is I₉. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is

The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have atmost two source operands and one destination operand. Assume that all variables are dead after this code segment.

   c = a + b;
   d = c * a;
   e = c + a;
   x = c * c;
   if (x > a) {
      y = a * a;
   }
   else {
     d = d * d;
     e = e * e;
  }

What is the minimum number of registers needed in the instruction set architecture of the processor to compile this code segment without any spill to memory? Do not apply any optimization other than optimizing register allocation.

The procedure given below is required to find and replace certain characters inside an input character string supplied in array A. The characters to be replaced are supplied in array oldc, while their respective replacement characters are supplied in array newc. Array A has a fixed length of five characters, while arrays oldc and newc contain three characters each. However, the procedure is flawed

void find_and_replace(char *A, char *oldc, char *newc) {
    for (int i = 0; i < 5; i++)
       for (int j = 0; j < 3; j++)
           if (A[i] == oldc[j]) A[i] = newc[j];
}

The procedure is tested with the following four test cases

(1) oldc = "abc", newc = "dab" (2) oldc = "cde", newc = "bcd" 
(3) oldc = "bca", newc = "cda" (4) oldc = "abc", newc = "bac" 

The tester now tests the program on all input strings of length five consisting of characters ‘a’, ‘b’, ‘c’, ‘d’ and ‘e’ with duplicates allowed. If the tester carries out this testing with the four test cases given above, how many test cases will be able to capture the flaw?

Register renaming is done in pipelined processors

A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit.

The number of bits in the tag field of an address is

A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit.

The size of the cache tag directory is

Consider a hypothetical processor with an instruction of type LW R1, 20 (R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand memory?

A computer handles several interrupt sources of which the following are relevant for this question.

. Interrupt from CPU temperature sensor (raises interrupt if CPU temperature is too high)
. Interrupt from Mouse(raises interrupt if the mouse is moved or a button is pressed)
. Interrupt from Keyboard(raises interrupt when a key is pressed or released)
. Interrupt from Hard Disk(raises interrupt when a disk read is completed)

Which one of these will be handled at the HIGHEST priority?

Consider an instruction pipeline with four stages (S1, S2, S3 and S4) each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure:

What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation?

An 8KB direct-mapped write-back cache is organized as multiple blocks, each of size 32-bytes. The processor generates 32-bit addresses. The cache controller maintains the tag information for each cache block comprising of the following.

1 Valid bit
1 Modified bit

As many bits as the minimum needed to identify the memory block mapped in the cache. What is the total size of memory needed at the cache controller to store meta-data (tags) for the cache?

An application loads 100 libraries at startup. Loading each library requires exactly one disk access. The seek time of the disk to a random location is given as 10 ms. Rotational speed of disk is 6000 rpm. If all 100 libraries are loaded from random locations on the disk, how long does it take to load all libraries? (The time to transfer data from the disk block once the head has been positioned at the start of the block may be neglected).

On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.

Initialize the address register
              Initialize the count to 500
        LOOP: Load a byte from device
              Store in memory at address given by address register
              Increment the address register
              Decrement the count
              If count != 0 go to LOOP

Assume that each statement in this program is equivalent to machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?

A 5-stage pipelined processor has Instruction Fetch(IF),Instruction Decode(ID),Operand Fetch(OF),Perform Operation(PO)and Write Operand(WO)stages.The IF,ID,OF and WO stages take 1 clock cycle each for any instruction.The PO stage takes 1 clock cycle for ADD and SUB instructions,3 clock cycles for MUL instruction,and 6 clock cycles for DIV instruction respectively.Operand forwarding is used in the pipeline.What is the number of clock cycles needed to execute the following sequence of instructions?

     Instruction           Meaning of instruction
  I0 :MUL R2 ,R0 ,R1	      R2 ¬ R0 *R1
  I1 :DIV R5 ,R3 ,R4  	      R5 ¬ R3/R4
  I2 :ADD R2 ,R5 ,R2	      R2 ¬ R5+R2
  I3 :SUB R5 ,R2 ,R6	      R5 ¬ R2-R6

A computer system has an L1 cache, an L2 cache, and a main memory unit connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times are 2 nanoseconds. 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory unit respectively.

When there is a miss in L1 cache and a hit in L2 cache, a block is transferred from L2 cache to L1 cache. What is the time taken for this transfer?

A computer system has an L1 cache, an L2 cache, and a main memory unit connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times are 2 nanoseconds. 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory unit respectively.

When there is a miss in both L1 cache and L2 cache, first a block is transferred from main memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. What is the total time taken for these transfers?

A CPU generally handles an interrupt by executing an interrupt service routine

Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown below:

What is the number of cycles needed to execute the following loop?

           for (i=1 to 2) {I1; I2; I3; I4;} 

Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocks and the request for memory blocks is in the following order:

        0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.

Which one of the following memory block will NOT be in cache if LRU replacement policy is used?

A hard disk has 63 sectors per track, 10 platters each with 2 recording surfaces and 1000 cylinders. The address of a sector is given as a triple , where c is the cylinder number, h is the surface number and s is the sector number. Thus, the 0^th sector is addressed as <0, 0, 0>, the 1^st sector as <0,0,1>, and so on.

The address <400, 16, 29> corresponds to sector number:

For a magnetic disk with concentric circular tracks, the seek latency is not linearly proportional to the seek distance due to

Which of the following is/are true of the auto-increment addressing mode?

I. It is useful in creating self-relocating code
II. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation
III. The amount of increment depends on the size of the data item accessed

Which of the following must be true for the RFE (Return From Exception) instruction on a general purpose processor?

I. It must be a trap instruction
II. It must be a privileged instruction
III. An exception cannot be allowed to occur during execution of an RFE instruction

For inclusion to hold between two cache levels L1 and L2 in a multi-level cache hierarchy, which of the following are necessary?

I. L1 must be a write-through cache
II. L2 must be a write-through cache
III. The associativity of L2 must be greater than that of L1
IV. The L2 cache must be at least as large as the L1 cache

Which of the following are NOT true in a pipelined processor?

I. Bypassing can handle all RAW hazards
II. Register renaming can eliminate all register carried WAR hazards
III. Control hazard penalties can be eliminated by dynamic branch prediction

The use of multiple register windows with overlap causes a reduction in the number of memory accesses for

I. Function locals and parameters
II. Register saves and restores
III. Instruction fetches

In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is

Consider a machine with a 2-way set associative data cache of size 64Kbytes and block size 16bytes. The cache is managed using 32 bit virtual addresses and the page size is 4Kbytes. A program to be run on this machine begins as follows:

double ARR[1024][1024];
int i, j;
 /* Initialize array ARR to 0.0 */
   for(i=0; i<1024; i++)
      for(j=0; j<1024; j++)
         ARR[i][j] = 0.0; 

The size of double is 8Bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored in row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the program are those to array ARR.

The total size of the tags in the cache directory is

Consider a machine with a 2-way set associative data cache of size 64Kbytes and block size 16bytes. The cache is managed using 32 bit virtual addresses and the page size is 4Kbytes. A program to be run on this machine begins as follows:

double ARR[1024][1024];
int i, j;
 /* Initialize array ARR to 0.0 */
   for(i=0; i<1024; i++)
      for(j=0; j<1024; j++)
         ARR[i][j] = 0.0; 

The size of double is 8Bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored in row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the program are those to array ARR.

Which of the following array elements has the same cache index as ARR[0][0]?

Consider a machine with a 2-way set associative data cache of size 64Kbytes and block size 16bytes. The cache is managed using 32 bit virtual addresses and the page size is 4Kbytes. A program to be run on this machine begins as follows:

double ARR[1024][1024];
int i, j;
 /* Initialize array ARR to 0.0 */
   for(i=0; i<1024; i++)
      for(j=0; j<1024; j++)
         ARR[i][j] = 0.0; 

The size of double is 8Bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored in row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the program are those to array ARR.

The cache hit ratio for this initialization loop is

Delayed branching can help in the handling of control hazards

For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false

Delayed branching can help in the handling of control hazards

The following code is to run on a pipelined processor with one branch delay slot:

I1: ADD R2 ← R7+R8
I2 : SUB R4 ← R5-R6
I3 : ADD R1 ← R2+R3
I4 : STORE Memory [R4] ← [R1]
     BRANCH to Label if R1 == 0 

Which of the instructions I1, I2, I3 or I4 can legitimately occupy the delay slot without any other program modification?

Consider a 4-way set associative cache consisting of 128 lines with a line size of 64 words. The CPU generates a 20-bit address of a word in main memory. The number of bits in the TAG, LINE and WORD fields are respectively:

Consider a disk pack with 16 surfaces, 128 tracks per surface and 256 sectors per track. 512 bytes of data are stored in a bit serial manner in a sector. The capacity of the disk pack and the number of bits required to specify a particular sector in the disk are respectively:

Consider a pipelined processor with the following four stages:

  IF: Instruction Fetch
  ID: Instruction Decode and Operand Fetch
  EX: Execute
  WB: Write Back

The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?

  ADD R2, R1, R0       R2 <- R0 + R1
  MUL R4, R3, R2       R4 <- R3 * R2
  SUB R6, R5, R4       R6 <- R5 - R4

In a simplified computer the instructions are:

  OP Rj,Ri - Performs Rj OP Ri and stores the result in register Ri. 
  OP m,Ri  - Performs val OP Ri and stores the result in Ri. val denotes the content of memory location m.
  MOV m,Ri - Moves the content of memory location m to register Ri.
  MOV Ri,m - Moves the content of register Ri to memory location m.

The computer has only to registers, and OP is either ADD or SUB. Consider the following basic block:

  t1 = a+b
  t2 = c+d
  t3 = e-t2
  t4 = t1-t3 

Assume that all operands are initially in memory. The final value of the computation should be in memory. What is the minimum number of MOV instructions in the code generated for this basic block?

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

       Instruction      Operation     Instruction size (no. of words)
       MOV R1,(3000)   R1 ← m[3000]                2
 LOOP: MOV R2,(R3)     R2 ← M[R3]                  1
       ADD R2,R1       R2 ← R1 + R2                1
       MOV (R3),R2     M[R3] ← R2                  1
       INC R3          R3 ← R3 + 1                 1
       DEC R1          R1 ← R1 - 1                 1
       BNZ LOOP        Branch on not zero          2
       HALT            Stop                        1 

Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal.

Assume that the memory is word addressable. The number of memory references for accessing the data in executing the program completely is:

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

       Instruction      Operation     Instruction size (no. of words)
       MOV R1,(3000)   R1 ← m[3000]                2
 LOOP: MOV R2,(R3)     R2 ← M[R3]                  1
       ADD R2,R1       R2 ← R1 + R2                1
       MOV (R3),R2     M[R3] ← R2                  1
       INC R3          R3 ← R3 + 1                 1
       DEC R1          R1 ← R1 - 1                 1
       BNZ LOOP        Branch on not zero          2
       HALT            Stop                        1 

Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal.

Assume that the memory is word addressable. After the execution of this program, the content of memory location 2010 is:

Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.

       Instruction      Operation     Instruction size (no. of words)
       MOV R1,(3000)   R1 ← m[3000]                2
 LOOP: MOV R2,(R3)     R2 ← M[R3]                  1
       ADD R2,R1       R2 ← R1 + R2                1
       MOV (R3),R2     M[R3] ← R2                  1
       INC R3          R3 ← R3 + 1                 1
       DEC R1          R1 ← R1 - 1                 1
       BNZ LOOP        Branch on not zero          2
       HALT            Stop                        1 

Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal.

Assume that the memory is byte addressable and the word size is 32 bits. If an interrupt occurs during the execution of the instruction “INC R3”, what return address will be pushed on to the stack?

Consider a machine with a byte addressable main memory of 2¹⁶ bytes. Assume that a direct mapped data cache consisting of 32 lines of 64 bytes each is used in the system. A 50 × 50 two-dimensional array of bytes is stored in the main memory starting from memory location 1100H. Assume that the data cache is initially empty. The complete array is accessed twice. Assume that the contents of the data cache do not change in between the two accesses.

How many data cache misses will occur in total?

Consider a machine with a byte addressable main memory of 2¹⁶ bytes. Assume that a direct mapped data cache consisting of 32 lines of 64 bytes each is used in the system. A 50 × 50 two-dimensional array of bytes is stored in the main memory starting from memory location 1100H. Assume that the data cache is initially empty. The complete array is accessed twice. Assume that the contents of the data cache do not change in between the two accesses.

Which of the following lines of the data cache will be replaced by new blocks in accessing the array for the second time?

A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)?

A CPU has a cache with block size 64 bytes. The main memory has k banks, each bank being c bytes wide. Consecutive c − byte chunks are mapped on consecutive banks with wrap-around. All the k banks can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by accessing all the k banks in parallel. Each iteration requires decoding the bank numbers to be accessed in parallel and this takes. k/2 ns The latency of one bank access is 80 ns. If c = 2 and k = 24, the latency of retrieving a cache block starting at address zero from main memory is:

A CPU has a five-stage pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new instructions following a conditional branch until the branch outcome is known. A program executes 10⁹ instructions out of which 20% are conditional branches. If each instruction takes one cycle to complete on average, the total execution time of the program is:

Consider a new instruction named branch-on-bit-set (mnemonic bbs). The instruction “bbs reg, pos, label” jumps to label if bit in position pos of register operand reg is one. A register is 32 bits wide and the bits are numbered 0 to 31, bit in position 0 being the least significant. Consider the following emulation of this instruction on a processor that does not have bbs implemented.

temp ← reg & mask 
Branch to label if temp is non-zero. 

The variable temp is a temporary register. For correct emulation, the variable mask must be generated by:

Consider two cache organizations: The first one is 32 KB 2-way set associative with 32-byte block size. The second one is of the same size but direct mapped. The size of an address is 32 bits in both cases. A 2-to-1 multiplexer has a latency of 0.6 ns while a kbit comparator has a latency of k/10 ns. The hit latency of the set associative organization is h₁ while that of the direct mapped one is h₂.

The value of h₁ is:

Consider two cache organizations: The first one is 32 KB 2-way set associative with 32-byte block size. The second one is of the same size but direct mapped. The size of an address is 32 bits in both cases. A 2-to-1 multiplexer has a latency of 0.6 ns while a kbit comparator has a latency of k/10 ns. The hit latency of the set associative organization is h₁ while that of the direct mapped one is h₂.

The value of h₂ is:

A CPU has a 32 KB direct mapped cache with 128-byte block size. Suppose A is a two-dimensional array of size 512×512 with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.

P1: for (i=0; i<512; i++) {
      for (j=0; j<512; j++) {
         x += A[i][j]; 
      }
    }

P2: for (i=0; i<512; i++) {
      for (j=0; j<512; j++) {
        x += A[j][i];
      }
    } 

P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.

The value of M1 is:

A CPU has a 32 KB direct mapped cache with 128-byte block size. Suppose A is a two-dimensional array of size 512×512 with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2.

P1: for (i=0; i<512; i++) {
      for (j=0; j<512; j++) {
         x += A[i][j]; 
      }
    }

P2: for (i=0; i<512; i++) {
      for (j=0; j<512; j++) {
        x += A[j][i];
      }
    } 

P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2.

The value of the ratio M1/M2 is:

Which one of the following is true for a CPU having a single interrupt request line and a single interrupt grant line?

What is the swap space in the disk used for?

Consider a three word machine instruction

ADD A[R0], @B

The first operand (destination) "A[R0]" uses indexed addressing mode with R0 as the index register. The second operand (source) "@B" uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand).

The number of memory cycles needed during the execution cycle of the instruction is

Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side.

     (1) A[1] = B[J];     (a) Indirect addressing
     (2) while [*A++];    (b) Indexed addressing
     (3) int temp = *x;   (c) Auto increment

Consider a direct mapped cache of size 32 KB with block size 32 bytes. The CPU generates 32 bit addresses. The number of bits needed for cache indexing and the number of tag bits are respectively.

A 5 stage pipelined CPU has the following sequence of stages:

IF — Instruction fetch from instruction memory.
RD — Instruction decode and register read.
EX — Execute: ALU operation for data and address computation.
MA — Data memory access - for write access, the register read at RD stage is used.
WB — Register write back. 

Consider the following sequence of instructions:

I1 : L R0, 1oc1; R0 <= M[1oc1]
I2 : A R0, R0 1; R0 <= R0 + R0
I3 : S R2, R0 1; R2 <= R2 - R0
Let each stage take one clock cycle.

What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of I₁?

A device with data transfer rate 10 KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be 4 μsec. The byte transfer time between the device interfaces register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program-controlled mode?

Consider a disk drive with the following specifications:

16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in cycle stealing mode whereby whenever one byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a 4 byte word from the memory in each DMA cycle. Memory cycle time is 40 nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is:

Consider the following data path of a CPU.

The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR.

The instruction "add R0, R1" has the register transfer interpretation R0 <= R0+R1. The minimum number of clock cycles needed for execution cycle of this instruction is:

Consider the following data path of a CPU.

The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR.

The instruction "call Rn, sub" is a two word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is

      Rn <= PC + 1;
      PC <= M[PC]; 

The minimum number of CPU clock cycles needed during the execution cycle of this instruction is:

Which of the following addressing modes are suitable for program relocation at run time?

(i)  Absolute addressing     (ii) Based addressing
(iii) Relative addressing     (iv) Indirect addressing 

Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.

 Instruction 	     Operation 	      Instruction Size(in words)
 MOV R1,5000; 	 ;R1 ← Memory[5000] 	         2
 MOV R2(R1); 	 ;R2 ← Memory[(R1)] 	         1
 ADD R2,R3; 	 ;R2 ← R2 + R3 	                 1
 MOV 6000,R2; 	 ;Memory[6000] ← R2 	         2
 HALT 	         ;Machine halts 	         1 

Consider that the memory is byte addressable with size 32 bits, and the program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be

Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.

 Instruction 	     Operation 	      Instruction Size(in words)
 MOV R1,5000; 	 ;R1 ← Memory[5000] 	         2
 MOV R2(R1); 	 ;R2 ← Memory[(R1)] 	         1
 ADD R2,R3; 	 ;R2 ← R2 + R3 	                 1
 MOV 6000,R2; 	 ;Memory[6000] ← R2 	         2
 HALT 	         ;Machine halts 	         1 

Let the clock cycles required for various operations be as follows:

Register to/ from memory transfer     : 3 clock cycles 
ADD with both operands in register    : 1 clock cycle 
Instruction fetch and decode          : 2 clock cycles per word  

The total number of clock cycles required to execute the program is

Consider a small two-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, use the least recently used (LRU) scheme. The number of cache misses for the following sequence of block addresses is 8, 12, 0, 12, 8

The microinstructions stored in the control memory of a processor have a width of 26 bits. Each microinstruction is divided into three fields: a micro-operation field of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX.

How many bits are there in the X and Y fields, and what is the size of the control memory in number of words?

A hard disk with a transfer rate of 10 Mbytes/ second is constantly transferring data to memory using DMA. The processor runs at 600 MHz, and takes 300 and 900 clock cycles to initiate and complete DMA transfer respectively. If the size of the transfer is 20 Kbytes, what is the percentage of processor time consumed for the transfer operation?

A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, the total time taken to process 1000 data items on this pipeline will be

For a pipelined CPU with a single ALU, consider the following situations

I. The j + 1-st instruction uses the result of the j-th instruction as an operand
II. The execution of a conditional jump instruction
III. The j-th and j + 1-st instructions require the ALU at the same time 

Which of the above can cause a hazard?

Using a larger block size in a fixed block size file system leads to:

Consider the following assembly language program for a hypothetical processor. A, B, and C are 8 bit registers. The meanings of various instructions are shown as comments.

     MOV B, # 0   	;   B ← 0
     MOV C, # 8	        ;   C ← 8
Z :  CMP C, # 0	        ;   compare C with 0
     JZX	        ;   jump to X if zero flag is set
     SUB C, # 1	        ;   C ← C - 1
     RRC A, # 1 	;   right rotate A through carry by one bit. Thus:
                        ;   if the initial values of A and the carry flag are a7...a0 and
                        ;   c0 respectively, their values after the execution of this
                        ;   instruction will be c0a7...a1 and a0 respectively.
     JC Y	        ;   jump to Y if carry flag is set
     JMP Z	        ;   jump to Z
Y :  ADD B, # 1	        ;   B ← B + 1
     JMP Z	        ;   jump to Z
X :	

If the initial value of register A is A₀ the value of register B after the program execution will be

Consider the following assembly language program for a hypothetical processor. A, B, and C are 8 bit registers. The meanings of various instructions are shown as comments.

     MOV B, # 0   	;   B ← 0
     MOV C, # 8	        ;   C ← 8
Z :  CMP C, # 0	        ;   compare C with 0
     JZX	        ;   jump to X if zero flag is set
     SUB C, # 1	        ;   C ← C - 1
     RRC A, # 1 	;   right rotate A through carry by one bit. Thus:
                        ;   if the initial values of A and the carry flag are a7...a0 and
                        ;   c0 respectively, their values after the execution of this
                        ;   instruction will be c0a7...a1 and a0 respectively.
     JC Y	        ;   jump to Y if carry flag is set
     JMP Z	        ;   jump to Z
Y :  ADD B, # 1	        ;   B ← B + 1
     JMP Z	        ;   jump to Z
X :	

Which of the following instructions when inserted at location X will ensure that the value of register A after program execution is the same as its initial value?

A device employing INTR line for device interrupt puts the CALL instruction on the data bus while

In 8085 which of the following modifies the program counter?

In serial data transmission, every byte of data is padded with a ‘0’ in the beginning and one or two ‘1’s at the end of byte because

Which of the following is not a form of memory?

In the absolute addressing mode

What are the states of the Auxiliary Carry (AC) and Carry Flag (dCY) after executing the following 8085 program?

   MVI H, 5DH
   MVI L, 6BH
   MOV A, H
   ADD L 

The performance of a pipelined processor suffers if

Horizontal microprogramming

In a C program, an array is declared as float A[2048]. Each array element is 4 Bytes in size, and the starting address of the array is 0×00000000. This program is run on a computer that has a direct mapped data cache of size 8 Kbytes, with block (line) size of 16 Bytes.

(a) Which elements of the array conflict with element A[0] in the data cache? Justify your answer briefly.

(b) If the program accesses the elements of this array one by one in reverse order i.e., starting with the last element and ending with the first element, how many data cache misses would occur? Justify your answer briefly. Assume that the data cache is initially empty and that no other data or instruction accesses are to be considered.

More than one word is put in one cache block to

A low memory can be connected to 8085 by using

Suppose a processor does not have any stack pointer register. Which of the following statements is true?

A processor needs software interrupt to

A CPU has two modes-privileged and non-privileged. In order to change the mode from privileged to non-privileged

Where does the swap space reside?

Which of the following requires a device driver?

Which is the most appropriate match for the items in the first column with the items in the second column

X. Indirect Addressing        I. Array implementation
Y. Indexed Addressing         II. Writing re-locatable code
Z. Base Register Addressing   III. Passing array as parameter 

Consider the following data path of a simple non-pilelined CPU. The registers A, B, A₁, A₂, MDR, the bus and the ALU are 8-bit wide. SP and MAR are 16-bit registers. The MUX is of size 8 × (2:1) and the DEMUX is of size 8 × (1:2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally.

The CPU instruction “push r”, where = A or B, has the specification

     M [SP] ← r
     SP ← SP - 1

How many CPU clock cycles are needed to execute the “push r” instruction?

Consider a disk with following specifications: 20 surface, 1000 tracks/surface, 16 sectors/track, data density 1 KB/sector, rotation speed 3000 rpm. The operating system initiates the transfer between the disk and the memory sector-wise. Once the head has been placed on the right track, the disk reads a sector in a single scan. It reads bits from the sector while the head is passing over the sector. The read bits are formed into bytes in a serial-in-parallel-out buffer and each byte is then transferred to memory. The disk writing is exactly a complementary process.

For parts (c) and (d) below, assume memory read-write time = 0.1 microsecond/byte, interrupt driven transfer has an interrupt overhead = 0.4 microseconds, the DMA initialization and termination overhead is negligible compared to the total sector transfer time. DMA requests are always granted.

(a) What is the total capacity of the disk?
(b) What is the data transfer rate?
(c) What is the percentage of time the CPU is required for this disk I/O for bytewise interrupts driven transfer?
(d) What is the maximum percentage of time the CPU is held up for this disk I/O for cycle-stealing DMA transfer?

A CPU has 32-bit memory address and a 256 KB cache memory. The cache is organized as a 4-way set associative cache with cache block size of 16 bytes.

(a) What is the number of sets in the cache?
(b) What is the size (in bits) of the tag field per cache block?
(c) What is the number and size of comparators required for tag matching?
(d) How many address bits are required to find the byte offset within a cache block?
(e) What is the total amount of extra memory (in bytes) required for the tag bits?

Consider a 5-stage pipeline – IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (memory), and WB (Write Back). All (memory or register) reads take place in the second phase of a clock cycle and writes occur in the first phase of the clock cycle. Consider the execution of the following instruction sequence:

      11:      sub r2, r3, r4;         /*   r2 ← r3 – r4    */
      12:      sub r4, r2, r3;         /*   r4 ← r2 – r3    */
      13:      sw r2, 100(r1)          /*   M[r1+100] ← r2  */
      14:      sub r3, r4, r2;         /*   r3 ← r4 – r2    */  

(a) Show all data dependencies between the four instructions.
(b) Identify the data hazards.
(c) Can all hazards be avoided by forwarding in this case?

Consider a disk with the 100 tracks numbered from 0 to 99 rotating at 3000 rpm. The number of sectors per track is 100. the time to move the head between two successive tracks is 0.2 millisecond.

(a) Consider a set of disk requests to read data from tracks 32, 7, 45, 5 and 10. Assuming that the elevator algorithm is used to schedule disk requests, and the head is initially at track 25 moving up (towards larger track numbers), what is the total seek time for servicing the requests?
(b) Consider an initial set of 100 arbitrary disk requests and assume that no new disk requests arrive while servicing these requests. If the head is initially at track 0 and the elevator algorithm is used to schedule disk requests, what is the worst case time to complete all the requests?

To put the 8085 microprocessor in the wait state

Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non-pipelined but identical CPU, we can say that

The 8085 microprocessor responds to the present of an interrupt

The most appropriate matching for the following pairs

    X: Indirect addressing            1 : Loops
    Y: Immediate addressing           2 : Pointers
    Z: Auto decrement addressing      3: Constants  

is

Consider the 8085 instruction IN 09H stored as follows:

And the following incomplete timing diagram for the instruction:

(a) Write the contents of the boxes, A, B, C and D in hexadecimal in your answer sheet. Do not draw any pictures.

(b) Write the state of both ALE and pins at time units T1, T2, T3 and T4.

(c) How do you generate the signal that tells the peripheral to put the data on the bus? Answer by completing the following statement in your answer book:
By combining signals …………….

Consider the following 8085 program segment, where registers B and C contain BCD values:

 S1: MVI     A, 99H
     MVI     D, 00H
     SUB     C
     ADD     B
     DAA
 S2: JC      S3 
     MOV     E, A
     MVI     A, 99H
     SUB     E
     MOV     E, A
     JZ      S4
     MVI     D, FFH
     JMP     S4
 S3: INC     A
     DAA
     MOV     E, A
 S4: ………… 

(a) For the two pairs (B = 44, C = 25) and (B = 33, C = 46) at S1,
(i) Find the values in register A when control reaches S2.
(ii) Find the values in registers D and E when control reaches S4.
(b) What, in general, is the value of D and E as a function of B and C when control reaches S4.

An instruction pipeline has five stages where each stage takes 2 nanoseconds and all instructions use all five stages. Branch instructions are not overlapped, i.e., the instruction after the branch is not fetched till the branch instruction is completed. Under ideal conditions.
(a) Calculate the average instruction execution time assuming that 20% of all instruction executed are branch instructions. Ignore the fact that some branch instructions may be conditional.
(b) If a branch instruction is a conditional branch instruction, the branch need not be taken. If the branch is not taken, the following instructions can be overlapped. When 80% of all branch instructions are conditional branch instructions, and 50% of the conditional branch instructions are such that the branch is taken, calculate the average instruction execution time.

The main memory of a computer has 2 cm blocks while the cache has 2c blocks. If the cache uses the set associative mapping scheme with 2 blocks per set, then block k of the main memory maps to the set

Raid configurations of the disks are used to provide

Arrange the following configuration for CPU in decreasing order of operating speeds: Hard wired control, vertical microprogramming, horizontal microprogramming.

The main differences(s) between a CISC and A RISC processor is/are that a RISC processor typically

A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor?

In serial communication employing 8 data bits, a parity bit and 2 stop bits, the minimum band rate required to sustain a transfer rate of 300 characters per second is