A 5 stage pipelined CPU has the following sequence of stages: IF — Instruction fetch from instruction memory. RD — Instruction decode and register read. EX […]

किसी भी समतलीय ग्राफ़ को शीर्ष-रंग देने के लिए पर्याप्त रंगों की न्यूनतम संख्या ________ है। Correct Answer: A Question 13 Explanation:  The 4-colour theorem of […]

Correct Answer: A Question 8 Explanation:  Since the given expression is in 0/0 form, so we can apply L-Hospital rule. A 1