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January 10, 2024

Pipelining

Question 14 We have two designs D1 and D2 for a synchronous pipeline processor. D1 has 5 pipeline stages with execution times of 3 nsec, 2 […]
January 10, 2024

GATE 2000

Question 8 Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non-pipelined but identical CPU, we […]
January 11, 2024

Process-Scheduling

Question 10 The arrival time, priority, and duration of the CPU and I/O bursts for each of three processes P1, P2 and P3 are given in the table below. […]