October 12, 2023
Question 23 Comparing the time T1 taken for a single instruction on a pipelined CPU, with time T2 taken on a no-pipelined but identical CPU, we […]
October 12, 2023
Question 42 A 4 kilobyte (KB) byte-addressable memory is realized using four 1 KB memory blocks. Two input address lines (IA4 and IA3) are connected to […]
October 13, 2023
Question 1 Consider a system with 2 level caches. Access times of Level 1 cache, Level 2 cache and main memory are 1 ns, 10ns, and […]
October 13, 2023
Question 2 If we use internal data forwarding to speed up the performance of a CPU (R1, R2 and R3 are registers and M[100] is a […]