December 5, 2023

Question 542 – DMA

Two control signals in microprocessor which are related to Direct Memory Access (DMA) are Correct Answer: D Question 11 Explanation:  HOLD (Hold) is a control signal […]
December 5, 2023

GATE 2022

Question 24 Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache […]
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