March 14, 2025
Question 35 For inclusion to hold between two cache levels L1 and L2 in a multi-level cache hierarchy, which of the following are necessary? I. L1 […]
March 14, 2025
Question 36 Which of the following are NOT true in a pipelined processor? I. Bypassing can handle all RAW hazards II. Register renaming can eliminate all […]
March 14, 2025
Question 37 The use of multiple register windows with overlap causes a reduction in the number of memory accesses for I. Function locals and parameters II. […]
March 14, 2025
Question 38 In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is A Before effective address calculation has […]