December 9, 2024
Question 15 A dynamic RAM has a memory cycle time of 64 nsec. It has to be refreshed 100 times per msec and each refresh takes […]
December 9, 2024
Question 18 Consider a Direct Mapped Cache with 8 cache blocks (numbered 0-7). If the memory block requests are in the following order 3, 5, 2, […]
December 11, 2024
Question 9 Consider a small two-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, use the least recently used (LRU) […]
December 17, 2024
Question 300 In a cache memory, if address has 9 bits in Tag field and 12 bits in index field, the size of main memory and […]