February 13, 2025

TNPSC-2012-Polytechnic-CS

Question 5 The CPU of a computer takes instruction from the memory and executes them. This process is called A Load cycle B Time sequences C […]
February 14, 2025

GATE-2024-CS1(Forenoon)

Question 30 Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of […]
February 17, 2025

UGC NET CS 2017 Jan- paper-3

Question 1 Which of the following is an interrupt according to temporal relationship with system clock? A Maskable interrupt B Periodic interrupt C Division by zero […]
February 17, 2025

UGC NET CS 2017 Jan- paper-3

Question 3 The general configuration of the micro-programmed control unit is given below:  What are blocks B and C in the diagram respectively? A Block address […]