| Computer Organisation | |||
| Easy | Medium | Difficult | |
| 2020 | 1. Interruption | 1. Cache 2. Registers | 1. Pipeline 2. Cache |
| 2019 | 1.Cache Memory | 1.DRAM | 1.Cache |
| 2018 | — | 1.DRAM 2.Interrupts 3.RISC and CISC 4.Associativity and Precedence | 1.Cache memory 2.Machine Instructions 3.Pipelining |
| 2017 Set-1 | — | 1.Static single assignment 2.Cache Memory | 1.Addressing Modes 2.Compilation 3.Cache Memory(2) 4.Instruction Cycle 5.Pipelining |
| 2017 Set-2 | 1.Cache Memory | 1.Left recursion grammar | 1.Cache Memory(2) |
| 2016 Set-1 | 1.Memory Interfacing | –1 | 1.DMA 2.Pipelining |
| 2016 Set-2 | 1.Instruction Set | 1.Machine Instructions 2.Cache Memory | 1.Pipelining(2) 2.Cache Memory |
| 2015 Set-1 | 1. Machine Instructions 2. Pipelining | — | 1. Secondary Storage |
| 2015 Set-2 | 1. Cache | — | 1. Secondary storage 2. Machine Instructions 3. Pipelining |
| 2015 Set-3 | — | 1. Cache | 1. Pipelining(2) |
| 2014 Set-1 | — | 1. Machine instructions 2. Pipelining | 1. Cache 2. Speedup |
| 2014 Set-2 | 1. Cache | — | 1. Cache(2) 2. Instruction cycle |
| 2014 Set-3 | 1. Pipelining | 1. DAG | 1. Pipelining 2. Cache |
| 2013 | — | 1. Machine instructions | 1. Cache 2. Secondary storage 3. Pipelining 4. Memory spilling (2) |
| 2012 | 1. Pipelining | 1. Cache(2) | — |
| 2011 | 1. Interrupt | 1. Addressing Modes 2. Pipelining | 1. Cache 2. Secondary storage 3. DMA |
| 2010 | — | 1. Memory Interfacing 2. Pipelining 3. Memory hierarchy(2) | — |
