| Computer Organization | |||
| Easy | Medium | Difficult | |
| 2020 | 1. Operand Instructions
2. Program Counter 3. Basics 4. Addressing Modes 5. Cache basics |
1. Addressing mode
2. Addressing Modes 3. Direct-mapped cache |
1. Big endian and little endian
2. Pipelining 3. Pipeline 4. Assembly code |
| 2018 | 1.MIcroprogram
2.Memory mapped I/O |
1.Memory address
2.Pipelining 3.Architecture |
— |
| 2017(Dec) | 1.DMA | 1.Cache memory
2.Addressing modes |
1.cache memory
2.Pipeline |
| 2017(May) | 1.RAM
2.Addressing modes |
— | — |
| 2016 | 1.Pipelines
2.Architecture 3.Addressing modes |
— | 1.pipeline |
| 2015 | 1.Memory operations | 1.RAM
2.Addressing instructions |
— |
| 2014 | — | 1.buffering techniques
2.Mis 3.RAM(2) 4.Memory Management |
— |
| 2013 | — | 1.Pipeline
2.Cache Memory 3.Flags |
1.DMA
2.Mis |
| 2011 | 1.Addressing Modes
2.Associate memory 3.DMA |
1.Mis
2.Address memory 3.Address bus 4.Memory Management |
1.Pipelines |
| 2009 | 1.Addressing Modes(2)
2.RISC/CISC |
1.Symetrix/Asymmetric
2.MIs 3.Instruction Set 4.IO Systems 5.Addressing Modes |
1.Address Modes
2.Pipeline 3.Booth’s algorithm |
| 2008 | 1.pipelines
2.Interrupts 3.Peripherals 4.Address Registers 5.Cache Memory |
1.Architecture | — |
| 2007 | 1.DRAM
2.Big endian |
— | — |
